CN113206098B - Three-dimensional memory and method for manufacturing three-dimensional memory - Google Patents

Abstract

The present invention provides a three-dimensional memory including peripheral circuit chips. The peripheral circuit chip includes: a first substrate; a first circuit element layer, disposed on the first substrate, and includes a first device layer and a first connection layer, and the first connection layer is used for signal transmission of the first device layer; A second substrate disposed on the first circuit element layer; and a second circuit element layer disposed on the second substrate and including a second device layer and a second connection layer for the second device Layer signal transmission. Since the devices in the peripheral circuit chip can be arranged on different substrates, the area of the peripheral circuit chip can be effectively reduced, which is beneficial to increase the storage density of the three-dimensional memory.

Description

Three-dimensional memory and method for manufacturing three-dimensional memory

technical field

The invention relates to a semiconductor device and a manufacturing method thereof, especially a three-dimensional memory including a memory array chip and a peripheral circuit chip and a manufacturing method thereof.

Background technique

With the increasing integration of three-dimensional memory, three-dimensional memory has developed from 32 layers to 64 layers or even higher layers. As the number of layers increases, the complexity of the memory array increases, which leads to the corresponding peripheral circuits. Increased design complexity. Generally speaking, the increase of storage density will increase the process difficulty of designing peripheral circuits in a limited area and increase the area of peripheral circuits.

Contents of the invention

The present invention provides a three-dimensional memory including peripheral circuit chips and a manufacturing method thereof, which can at least partly solve the above-mentioned problems in the prior art.

According to an aspect of the present invention, there is provided a three-dimensional memory including a peripheral circuit chip, wherein the peripheral circuit chip includes: a first substrate; a first circuit element layer disposed on the first substrate, and includes a first device layer and The first connection layer, the first connection layer is used for signal transmission of the first device layer; the second substrate, arranged on the first circuit element layer; and the second circuit element layer, arranged on the second substrate, and includes The second device layer and the second connection layer, the second connection layer is used for signal transmission of the second device layer.

In an embodiment, the first device layer may include a plurality of first transistors, the second device layer may include a plurality of second transistors, and the operating voltage of the first transistor may be greater than that of the second transistor.

In an embodiment, the size of the first transistor may be larger than the size of the second transistor.

In an embodiment, each of the first connection layer and the second connection layer may include a conductive material, and a melting point of the conductive material of the first connection layer may be greater than or equal to a melting point of the conductive material of the second connection layer.

In an embodiment, the conductive material of the first connection layer may be WSi or TiSi, and the conductive material of the second connection layer may be TiSi or CoSi.

In an embodiment, the peripheral circuit chip may further include: a third substrate disposed on the second circuit element layer; a third circuit element layer disposed on the third substrate and including a third device layer and a third connection layer, and the third connection layer is used for signal transmission of the third device layer.

In an embodiment, the peripheral circuit chip may further include at least one of a first interconnection layer, a second interconnection layer, and a third interconnection layer. The first interconnection layer may electrically connect the first connection layer and the second connection layer for signal transmission between the first device layer and the second device layer. The second interconnection layer may electrically connect the third connection layer with one of the first connection layer and the second connection layer for signal transmission between the third connection layer and the one connection layer. The third interconnection layer may electrically connect the third connection layer with the other connection layer of the first connection layer and the second connection layer for signal transmission between the third connection layer and the other connection layer.

In an embodiment, at least one of the first interconnection layer, the second interconnection layer, and the third interconnection layer may include W.

In an embodiment, the first device layer may include a plurality of first transistors, the second device layer may include a plurality of second transistors, and the third device layer may include a plurality of third transistors. In an embodiment, an operating voltage of at least one first transistor may be greater than an operating voltage of at least one second transistor, and an operating voltage of at least one second transistor may be greater than an operating voltage of at least one third transistor.

In an embodiment, a size of at least one first transistor may be larger than a size of at least one second transistor, and a size of at least one second transistor may be larger than a size of at least one third transistor.

In an embodiment, at least one of the first transistor, the second transistor and the third transistor may be a metal oxide semiconductor field effect transistor.

In an embodiment, each of the first connection layer, the second connection layer, and the third connection layer may include a conductive material, and the melting point of the conductive material of the first connection layer may be greater than or equal to the melting point of the conductive material of the second connection layer. , and the melting point of the conductive material of the second connection layer may be greater than or equal to the melting point of the conductive material of the third connection layer.

In an embodiment, the conductive material of the first connection layer may be WSi or TiSi, the conductive material of the second connection layer may be TiSi or CoSi, and the conductive material of the third connection layer may be NiSi.

In an implementation manner, the first connection layer may further include a first dielectric layer for electrically isolating the conductive material of the first connection layer, and the second connection layer may also include a second dielectric layer for the second dielectric layer to The third connection layer is used to electrically isolate the conductive material of the second connection layer, and the third connection layer may further include a third dielectric layer, and the third dielectric layer is used to electrically isolate the conductive material of the third connection layer.

In an embodiment, the three-dimensional memory further includes a memory array chip, wherein the memory array chip may include a memory array layer and a first bonding layer disposed on the memory array layer, and the memory array layer includes a plurality of For the storage string, the first bonding layer is used for bonding with the second bonding layer in the peripheral circuit chip.

In an embodiment, a second bonding layer may be disposed on the second circuit element layer.

According to another aspect of the present invention, there is provided a method for manufacturing a three-dimensional memory, the method includes forming a peripheral circuit chip based on a first substrate, including: sequentially forming a first device layer on the first substrate and for the first A first connection layer for signal transmission of the device layer; a second substrate is formed on the first connection layer, and a second device layer and a second connection layer for signal transmission of the second device layer are sequentially formed on the second substrate ; and forming a bonding layer with conductive contacts on the second connection layer.

In an embodiment, the first device layer may include a plurality of first transistors, the second device layer may include a plurality of second transistors, and an operating voltage of at least one first transistor may be greater than an operating voltage of at least one second transistor.

In an embodiment, a size of at least one first transistor may be greater than a size of at least one second transistor.

In an embodiment, forming the first connection layer may include: forming a first dielectric layer on the first device layer; and forming conductive wiring and conductive contacts for signal transmission in the first dielectric layer using a first conductive material. In an embodiment, forming the second connection layer may include: forming a second dielectric layer on the second device layer; and forming conductive wiring and conductive contacts for signal transmission in the second dielectric layer using a second conductive material. In an embodiment, the melting point of the first conductive material is greater than or equal to the melting point of the second conductive material.

In an embodiment, the method may further include: forming a third substrate on the second connection layer, and sequentially forming a third device layer and a signal transmission third connection layer for the third device layer on the third substrate , wherein the bonding layer is formed on the third connection layer.

In an embodiment, the method may further include forming at least one of a first interconnection layer, a second interconnection layer, and a third interconnection layer, wherein the first interconnection layer may connect the first connection layer to the second The connection layer is electrically connected, the second interconnection layer can electrically connect the second connection layer and the third connection layer, and the third interconnection layer can electrically connect the first connection layer and the third connection layer; and on the third connection layer A bonding layer with conductive contacts is formed.

In an embodiment, the first device layer may include a plurality of first transistors, the second device layer may include a plurality of second transistors, and the third device layer may include a plurality of third transistors. In an embodiment, an operating voltage of at least one first transistor may be greater than an operating voltage of at least one second transistor, and an operating voltage of at least one second transistor may be greater than an operating voltage of at least one third transistor.

In an embodiment, a size of at least one first transistor may be larger than a size of at least one second transistor, and a size of at least one second transistor may be larger than a size of at least one third transistor.

In an embodiment, forming the first connection layer may include: forming a first dielectric layer on the first device layer; and forming conductive wiring and conductive contacts for signal transmission in the first dielectric layer using a first conductive material. In an embodiment, forming the second connection layer may include: forming a second dielectric layer on the second device layer; and forming conductive wiring and conductive contacts for signal transmission in the second dielectric layer using a second conductive material. In an embodiment, forming the third connection layer may include: forming a third dielectric layer on the third device layer; and forming conductive wiring and conductive contacts for signal transmission in the third dielectric layer using a third conductive material. In an embodiment, the melting point of the conductive material of the first conductive layer may be greater than or equal to the melting point of the conductive material of the second conductive layer, and the melting point of the conductive material of the second conductive layer may be greater than or equal to that of the conductive material of the third conductive layer. melting point.

In the three-dimensional memory and manufacturing method of the above embodiment, since the devices in the peripheral circuit chip can be arranged on different substrates, the area of the peripheral circuit chip can be effectively reduced, which is beneficial to increase the storage density of the three-dimensional memory. At the same time, since devices with different operating voltages are formed on different substrates, the preparation process can be simplified and the stability of the devices can be improved.

Description of drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept. In the attached picture:

1 is a schematic cross-sectional view illustrating a peripheral circuit chip of a three-dimensional memory according to the prior art;

2 is a schematic cross-sectional view illustrating a peripheral circuit chip of a three-dimensional memory according to an exemplary embodiment of the present invention;

3 is a schematic cross-sectional view illustrating a NAND memory including a NAND memory array chip and the peripheral circuit chip of FIG. 2 according to an exemplary embodiment of the present invention;

4 is a schematic cross-sectional view illustrating a peripheral circuit chip of a three-dimensional memory according to another exemplary embodiment of the present invention;

5 is a schematic cross-sectional view of a NAND memory including a NAND memory array chip and the peripheral circuit chip of FIG. 4 according to another exemplary embodiment of the present invention;

6 is a flowchart illustrating a part of a method of manufacturing a three-dimensional memory including the peripheral circuit chip shown in FIG. 2 according to the present invention; and

FIG. 7 is a flowchart illustrating a part of a method of manufacturing a three-dimensional memory including the peripheral circuit chip shown in FIG. 4 according to the present invention.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings. The exemplary embodiments mentioned herein are only used to explain the present invention, and are not intended to limit the scope of the present invention.

The use of cross-hatching and/or shading is generally provided in the figures to clarify boundaries between adjacent elements. Accordingly, neither the presence nor absence of cross-hatching or shading conveys or indicates any assumptions about particular materials, material properties, dimensions, proportions, commonality between illustrated elements, and/or any other characteristics, properties, properties, etc. of the elements. preference or request unless otherwise stated. Furthermore, in the drawings, the size and relative sizes and shapes of elements have been adjusted for clarity and/or descriptive purposes. It should be understood that the drawings are only examples and are not strictly drawn to scale.

Throughout the specification, the same reference numerals refer to the same elements. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the terms "approximately," "about," and similar terms are used to denote approximations, not degrees, and are intended to illustrate what would be recognized by one of ordinary skill in the art, among measured or calculated values. inherent bias. It should be understood that in this specification, expressions such as first and second are only used to distinguish one feature from another, and do not represent any limitation on the features, especially do not represent any sequential order.

It should also be understood that expressions such as "comprising", "having" and/or "comprising" in this specification are open rather than closed expressions, which mean that there are stated features, elements and/or parts, but not The presence of one or more other features, elements, components and/or combinations thereof is excluded. Furthermore, expressions such as "at least one of," when preceding a list of listed features, modify the entire list of features and do not modify just the individual elements of the list. Additionally, the use of "may" when describing embodiments of the present invention means "one or more embodiments of the present invention." Also, the word "exemplary" is intended to mean an example or illustration.

The various exemplary embodiments may vary, but are not necessarily exhaustive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment may be used or practiced in another exemplary embodiment without departing from the inventive concepts.

Unless otherwise indicated, the exemplary embodiments shown are to be understood as providing exemplary features of varying details of some of the ways in which the inventive concept can be implemented in practice. Thus, unless otherwise stated, the features, molecules, components, modules, layers, films, panels, regions and/or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") can be used without departing from the present invention. Otherwise combined, separated, interchanged and/or rearranged under contemplation.

It should be noted that references in the specification to "one embodiment/example," "implementation/example," "exemplary embodiment/example," "some implementations/example," etc. mean that the described embodiments Embodiments/embodiments may include a particular feature, structure, or characteristic, but not necessarily every implementation/embodiment includes that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same implementation/embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment/example, whether or not explicitly described, it would be within the purview of those skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments/embodiments. within the scope of knowledge.

It should be understood that "on", "on" and "on" in this disclosure are to be construed in the broadest manner such that "on" does not merely mean "directly on a "on something", but also includes the meaning of "on something" with intermediate features or layers in between, and "on" or "right on" means not only "on something" or "on something "on" meaning, but also can include the meaning of "on" or "directly on" with no intervening features or layers (ie, directly on). The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. A layer may extend across the entire substructure or superstructure, or may have a smaller extent than that of the substructure or superstructure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces. Layers may extend laterally, vertically and/or along the tapered surface. A substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, on, and/or below. Layers may include multiple layers. For example, a connection layer may include one or more conductor and contact layers (in which interconnect/bond lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term "about" indicates a value for a given quantity that may vary based on the particular technology node associated with the subject semiconductor device. The term "about" may refer to a value of a given quantity that varies, for example, within 10%-30% of that value (e.g., ±10%, ±20%, or ±30% of the value) based on a particular technology node. %).

It should be noted that the diagrams provided in the embodiments are only schematically illustrating the basic concept of the present invention, and thus only the components related to the present invention are shown in the diagrams rather than the number, shape and size of the components in actual implementation Drawing, the shape, quantity and proportion of each component can be changed arbitrarily during its actual implementation, and the layout of components may also be more complicated.

It should also be understood that unless explicitly defined or contradicted by context, the specific steps involved in the described methods of the present invention are not necessarily limited to the recited order, for example, a particular process sequence may be performed differently than the described order. For example, two consecutively described processes may be performed substantially simultaneously, or performed in an order reverse to that described.

The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

FIG. 1 is a schematic cross-sectional view showing a peripheral circuit chip of a related art three-dimensional memory.

In the prior art three-dimensional memory, the peripheral circuit chip 20 includes a substrate 201 and a circuit element layer 200 on the substrate 201 .

Circuit element layer 200 includes any suitable digital, analog, and mixed-signal control and sensing circuitry for facilitating three-dimensional memory, including but not limited to page buffers, decoders (e.g., row and column decoders), sense Amplifiers, drivers (e.g., word line drivers), charge pumps, current and voltage references, or any active or passive components of circuitry (e.g., transistors, diodes, resistors, or capacitors), and thus, circuit element layer 200 includes The device layer 210 (which includes devices such as transistors 211, etc.) realizing these functions and the connection layer 220 (which includes connection wiring 221, contacts 222, etc.) for receiving electrical signals from the device layer 210 or transmitting electrical signals to the device layer 210 ). Devices in the device layer 210 are electrically connected to each other through connection wiring 221 and contacts 222 in the connection layer 220 . The peripheral circuit chip 20 also includes a bonding layer 230 for bonding the peripheral circuit chip 20 to a memory array chip (not shown), and the bonding layer 230 includes conductive contacts 231 . The position where the substrate of the storage array chip is located may overlap with the position where the substrate 201 of the peripheral circuit chip 20 is located in the thickness direction perpendicular to the substrate 201 of the peripheral circuit chip 20 (such as the three-dimensional memory in the X-tacking technology, where The peripheral circuit chip 20 and the memory array chip are vertically stacked), or may overlap in a lateral direction with the substrate 201 (for example, the peripheral circuit chip 20 and the memory array chip are horizontally placed side by side).

Since the peripheral circuit chip 20 in the prior art includes only one substrate, and therefore the circuit element layer 200 is disposed on the same substrate. This architecture will lead to an increase in the area required for peripheral circuits when the storage density increases.

In order to reduce the design area of peripheral circuits, the present invention proposes a structure different from that of the prior art three-dimensional memory. A three-dimensional memory according to an embodiment of the present invention will be described below with reference to FIGS. 2 to 5 .

2 is a schematic cross-sectional view illustrating a peripheral circuit chip of a three-dimensional memory according to an exemplary embodiment of the present invention.

As shown in FIG. 2 , a three-dimensional memory according to an exemplary embodiment of the present invention may include a memory array chip (not shown) and a peripheral circuit chip 40 .

The peripheral circuit chip 40 may include a substrate 401 , a first circuit element layer 402 on the substrate 401 , a substrate 403 and a second circuit element layer 404 on the substrate 403 .

The substrate 401 may include single crystal silicon, polycrystalline silicon, amorphous silicon, germanium (Ge) substrate, silicon germanium (SiGe), gallium arsenide (GaAs), SOI (Silicon-on-insulator, silicon-on-insulator) substrate Or GOI (Germanium-on-insulator, germanium-on-insulator), salicide or any other suitable material. In one embodiment of the present invention, the substrate 401 may be, for example, a silicon wafer, but the present invention is not limited thereto.

The first circuit element layer 402 may include any suitable digital, analog, and mixed-signal control and sensing circuitry for facilitating three-dimensional memory, including but not limited to page buffers, decoders (e.g., row decoders and column decoders) , sense amplifiers, drivers (eg, word line drivers), charge pumps, current and voltage references, or any active or passive components of the circuit (eg, transistors, diodes, resistors, or capacitors), and therefore, the first The circuit element layer 402 may include a device layer (which includes devices such as transistors) for implementing these functions and a connection layer (which includes connection wiring and contacts, etc.) for receiving electrical signals from the device layer or transmitting electrical signals to the device layer. . For example, the first circuit element layer 402 may include a first device layer 410 for realizing at least a part of functions of the peripheral circuit chip 40 and a first connection layer 420 for signal transmission of the first device layer 410 . The first device layer 410 may include various devices constituting a part of a circuit of the peripheral circuit chip 40 , for example, a plurality of first transistors 411 as shown in FIG. 2 .

The devices in the first device layer 410 can receive electrical signals or transmit electrical signals through the connection wiring 421 and connection access (via) contacts 422 (hereinafter also referred to as "contacts 422") in the first connection layer 420. . The first connection layer 420 may include a plurality of connection wirings 421 and contacts 422 according to chip design requirements. The first connection layer 420 may further include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers", not shown), in which connection wirings 421 and contacts 422 may be formed. In other words, the first connection layer 420 may include the connection wiring 421 and the contact 422 in the ILD layer. The connection wiring 421 and the contact 422 in the first connection layer 420 may include conductive materials including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layer in the first connection layer 420 may also include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof, to connect the connection wiring 421 in the first connection layer 420 and contacts 422 etc. are electrically isolated from other components. The connection wiring 421 and the contact 422 in the first connection layer 420 may be formed of a conductive material deposited by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition ( PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof. The manufacturing process for forming the connection wiring 421 and the contact 422 may also include photolithography, chemical mechanical polishing (CMP), wet/dry etching, or any other suitable process. The ILD layer of the first connection layer 420 may be formed of a dielectric material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

The substrate 403 may be formed through a single crystal silicon growth process, or may be formed by first growing polycrystalline silicon and then heat-treating the polycrystalline silicon. It should be understood that the substrate 403 is not limited to a silicon substrate, and may also be any other suitable material such as a germanium substrate.

The devices in the second device layer 430 can receive electrical signals or transmit electrical signals through the connection wiring 441 and the connection access (via) contacts 442 (hereinafter also referred to as "contacts 442") in the second connection layer 440. . The second connection layer 440 may include a plurality of connection wirings 441 and contacts 442 according to chip design requirements. The second connection layer 440 may further include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers", not shown), in which connection wirings 441 and contacts 442 may be formed. In other words, the second connection layer 440 may include the connection wiring 441 and the contact 442 in the ILD layer. The connection wiring 441 and the contact 442 in the second connection layer 440 may include conductive materials including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layer in the second connection layer 440 may also include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof, to connect the connection wiring 441 in the second connection layer 440 and contacts 442 etc. are electrically isolated from other components. Similar to the first connection layer 420, the connection wiring 441 and the contacts 442 in the second connection layer 440 may also be formed of conductive materials deposited by one or more thin film deposition processes, including but not limited to chemical CVD , PVD, ALD, electroplating, electroless plating or any combination thereof. The manufacturing process for forming the connection wiring 441 and the contact 442 may also include photolithography, CMP, wet/dry etching, or any other suitable process. The ILD layer of the second connection layer 440 may also be formed from a dielectric material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

The first device layer 410 and the second device layer 430 include a plurality of first transistors 411 and a plurality of second transistors 431 formed on substrates 401 and 403 , respectively. It should be understood that in the present invention, a transistor formed "on" a substrate may mean that the whole or part of the transistor is formed in the substrate (eg, below the top surface of the substrate) and/or directly on the substrate, which means Depending on the material of the substrate and the type and material of the transistors, the invention does not impose any restrictions on this. Transistors 411 and 431 may be formed by various processes including, but not limited to, photolithography, dry/wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. For example, in the case where the substrate is a silicon substrate, a doped region may be formed in the silicon substrate, for example, by ion implantation and/or thermal diffusion, to serve as, for example, a source region and/or a drain region of a transistor; An isolation region (eg, STI) is formed in a silicon substrate, for example, through wet/dry etching and thin film deposition processes, but the present invention is not limited thereto.

The peripheral circuit chip 40 may also include a first interconnection layer (not shown), which is used to electrically connect the first connection layer 420 with the second connection layer 440, so as to realize the connection between the first circuit element layer 402 and the second circuit element layer. Signal transmission is performed between layers 404 . The first interconnection layer may include a plurality of interconnections 451 (also referred to herein as “contacts”) according to chip design requirements, for example, including vertical interconnection (via) contacts. The first interconnect layer may also include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers", not shown), in which contacts 451 may be formed. In other words, the first interconnect layer may include contacts 451 located in the ILD layer. Contacts 451 in the first interconnect layer may include conductive materials including, but not limited to, such as W, Co, Cu, Al, and the like. In an optional embodiment, the conductive material of the first interconnection layer is W. The ILD layer in the first interconnect layer may also include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof, to connect the contacts 451 in the first interconnect layer etc. are electrically isolated from other components. It should be understood that although the peripheral circuit chip 40 includes the first interconnection layer electrically connecting the first connection layer 420 and the second connection layer 440 in the embodiment described above with reference to FIG. 2 , the present invention is not limited thereto. According to an exemplary embodiment of the inventive concept, the peripheral circuit chip 40 may also not include the first interconnection layer.

The peripheral circuit chip 40 may further include a bonding layer 490 for bonding the peripheral circuit chip 40 to the memory array chip. Bonding layer 490 is located on substrate 401, first circuit element layer 402, substrate 403, and second circuit element layer 404, and may include a plurality of bonding contacts 491 and a dielectric that electrically isolates bonding contacts 491 ( not shown). Bonding contacts 491 may include conductive materials including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of bonding layer 490 may be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts 491 in bonding layer 490 and the surrounding dielectric may be used for hybrid bonding.

According to the inventive concept, since the peripheral circuit chip 40 includes two substrates 401 and 403 and two circuit element layers 402 and 404 formed on the two substrates, compared with the prior art shown in FIG. More devices can be integrated per unit area, which can effectively reduce the peripheral area.

Further, considering that the performance of the transistor formed first in the lower layer and its connection wiring and contacts may be affected by the process of the transistor formed later in the upper layer, and that the resistivity of the contact contacting the transistor with a lower operating voltage is usually required to be very low, In order to simplify the process of forming the transistors in the circuit element layer and improve the stability of the transistors, the transistors with different operating voltages to be used in the peripheral circuit chip 40 can be formed on different substrates respectively, that is, the transistors with different operating voltages can be formed on different substrates. Voltage transistors are formed in different circuit element layers respectively. In a preferred embodiment of the present invention, transistors with higher operating voltages (hereinafter referred to as "high-voltage transistors") and connection wiring and contacts formed of high-temperature-resistant conductive materials are formed in the lower first circuit element layer 402 , and a transistor with a lower operating voltage (hereinafter simply referred to as "low voltage transistor") and connection wiring and contacts formed of a conductive material with a very small resistivity are formed in the upper second circuit element layer 404, for example, the second circuit element layer 404. The operating voltage of each of the first transistors 411 may be greater than the operating voltage of each of the second transistors 431 . The transistor may be any type of transistor, for example, may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). More specifically, the transistor may be, for example, a Complementary Metal Oxide Semiconductor (CMOS) transistor. According to some embodiments, the transistors may achieve high speed using advanced logic processes (eg, technology nodes of 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, etc.). It should also be understood that the high pressure and low pressure here are relative terms and are not particularly limited. In an exemplary embodiment as shown in FIG. 2 , for example, the operating voltage of the high voltage transistor may be greater than 10 volts (V), eg, 15V to 35V, and the operating voltage of the low voltage transistor may be less than 5V, eg, 3.3V. In a preferred embodiment of the present invention, the size of the high voltage transistor may be larger than that of the low voltage transistor. For example, the thickness of the gate layer of the high-voltage transistor may be greater than that of the low-voltage transistor, and for example, the thickness of the gate layer of the high-voltage transistor may be, for example, more than three times the thickness of the gate layer of the low-voltage transistor. In a preferred embodiment of the present invention, the operating voltage of each of the first transistors 411 may be greater than the operating voltage of each of the second transistors 431 . Furthermore, in a preferred embodiment of the present invention, the size of each of the first transistors 411 may be larger than the size of each of the second transistors 431 .

As mentioned above, the lower high-voltage transistors are formed earlier than the upper low-voltage transistors. In order to avoid damage to the high-voltage transistors and their connection wiring (first connection layer 420) when forming low-voltage transistors, the conductive material of the first connection layer 420 needs to be high temperature resistant. and has good electrical conductivity so that the performance of the devices in the first device layer 410 will not be affected by the subsequent process of forming the second circuit element layer 404 . Because the low-voltage transistor of the upper layer has a smaller operating voltage, the resistivity of the contact is required to be low. Therefore, the resistivity of the connection wiring and the contact (conductive material) of the second connection layer 440 connected to the low-voltage transistor of the upper layer is required to be low. The process temperature of the connection wiring and contacts of the connection layer 440 should be less than the melting point of the connection wiring and contacts (conductive material) of the first connection layer 420, and therefore, the connection wiring and contacts (conductive material) of the first connection layer 420 The melting point of is greater than or equal to the melting point of the connection wiring and contacts (conductive material) of the second connection layer 440 . Accordingly, the resistivity of the connection wiring and contacts (conductive material) of the second connection layer 440 is smaller than the resistivity of the connection wiring and contacts (conductive material) of the first connection layer 420 .

In some exemplary embodiments of the present invention, the connection wiring 441 and the contact 442 of the second connection layer 440 may include WSi or TiSi, which may be formed by any appropriate WSi process or TiSi process, and the first connection layer 420 The connection wiring 421 and the contact 422 may include TiSi, CoSi or NiSi, which may be formed by any suitable TiSi process, CoSi process or NiSi process. For example, when the connection wiring 421 and the contact 422 of the first connection layer 420 include WSi, the connection wiring 441 and the contact 442 of the second connection layer 440 may include TiSi, CoSi or NiSi; When the contact 421 and the contact 422 include TiSi, the connection wiring 441 and the contact 442 of the second connection layer 440 may include CoSi or NiSi, but the present invention is not limited thereto. In some exemplary embodiments of the present invention, for example, the conductive material of the first connection layer 420 can still maintain the required contact with the gate, source or drain of the first transistor 411 at least 500 degrees Celsius (°C). resistance so that the performance of the first transistor 411 will not be affected, and the conductive material of the second connection layer 440 can still maintain the required contact resistance with the second transistor 431 at about 450° C. so that the performance of the second transistor 431 will not be affected. Affected.

It has been described above that the operating voltage of each of the first transistors 411 is greater than the operating voltage of each of the second transistors 431 and the size of each of the first transistors 411 is greater than the size of each of the second transistors 431. implementation. However, it should be understood that the present invention is not limited thereto. For example, in some other implementation manners, the working voltage of at least one first transistor 411 may be greater than that of the second transistor 431 . In yet other embodiments, the size of at least one first transistor 411 may be larger than the size of at least one second transistor 431 .

The three-dimensional memory including the peripheral circuit chip 40 shown in FIG. 2 of the present invention will be described below by taking the NAND three-dimensional memory in the X-tacking technology as an example. However, it should be understood that the peripheral circuit chip 40 shown in FIG. 2 can be arranged side by side with the storage array chip to form a three-dimensional memory, and can also be stacked with the storage array chip in a face-to-face manner. There is no limitation on the combination method and the type and specific structure of the memory array chip.

FIG. 3 is a schematic cross-sectional view of a NAND memory array chip including the peripheral circuit chip shown in FIG. 2 according to an exemplary embodiment.

For ease of understanding, in FIG. 3, a NAND three-dimensional memory is shown as an example of a three-dimensional memory, and a NAND memory array chip is shown as an example of a memory array chip 30, but it should be understood that the three-dimensional memory of the present invention is not limited to a NAND three-dimensional memory. Memory, and the corresponding memory array chips 30 are not limited to NAND memory array chips, any other type of three-dimensional memory and corresponding memory array chips are also applicable.

As shown in FIG. 3, the memory array chip 30 may include a substrate 301, a NAND memory array layer 310, a connection layer 340 for signal transmission of the NAND memory array layer 310, and a bonding layer for bonding with peripheral circuit chips. 360.

The storage array chip 30 can be bonded face-to-face with the peripheral circuit chip 40 at the bonding interface BB by the bonding contact 362 in the bonding layer 360 and the bonding contact 491 (referring to FIG. 2 ) in the bonding layer 490 . In some embodiments, bonding interface BB is disposed between bonding layer 360 and bonding layer 490 as a result of hybrid bonding (also referred to as “hybrid metal-dielectric bonding”). Hybrid bonding is a direct bonding technique (i.e., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can achieve both metal-metal bonding and dielectric- Dielectric bonding. In some embodiments, bonding interface BB is where bonding layer 360 and bonding layer 490 meet and bond. The bonding interface BB may have a certain thickness, for example, the distance from the top surface of the bonding layer 490 of the peripheral circuit chip 40 to the bottom surface of the bonding layer 360 of the memory array chip 30 .

The connection layer 340 may include a plurality of connection wirings 341 and connection access (via) contacts 342 (eg, bit line contacts and word line contacts, hereinafter collectively referred to as "contacts 342"). The connection layer 340 may further include one or more ILD layers (not shown), in which connection wirings 341 and contacts 342 may be formed. The connection wiring 341 and the contact 342 in the connection layer 340 may include conductive materials including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof.

A NAND memory array layer 310 may be formed on the substrate 301 . The substrate 301 may be a thinned semiconductor substrate. In some embodiments, the substrate 301 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium (Ge) substrate, silicon germanium (SiGe), gallium arsenide (GaAs), SOI (Silicon-on-insulator, silicon-on-insulator) substrate or GOI (Germanium-on-insulator, germanium-on-insulator), salicide or any other suitable material. The substrate 301 may also include isolation regions and doped regions (eg, used as an array common source (ACS) for the 3D NAND channel structure 318, not shown). Isolation regions (not shown) may extend across the entire thickness or a portion of the thickness of the substrate 301 to electrically isolate the doped regions. In some embodiments, an oxide layer including silicon oxide is disposed between the stack structure and the substrate 301 .

In the NAND memory array layer 310, memory cells are provided in the form of an array of 3D NAND channel structures 318 (also referred to as "strings"). According to some embodiments, each 3D NAND channel structure 318 extends vertically through a plurality of pairs each comprising a conductor layer 314 and a dielectric layer 316 . The stacked and interleaved conductor layers 314 and dielectric layers 316 are also referred to herein as a stack structure. According to some embodiments, the alternating conductor layers 314 and dielectric layers 316 in the stack alternate in the vertical direction. In other words, each conductor layer 314 may be bordered on two sides by two dielectric layers 316, and each dielectric layer 316 may be bordered on two sides by two conductor layers 314, except those at the top or bottom of the stack. . The conductor layers 314 may all have the same thickness or different thicknesses. Similarly, dielectric layers 316 may all have the same thickness or different thicknesses. The conductor layer 314 may comprise a conductor material including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. Dielectric layer 316 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

The NAND memory array layer 310 may also include a common source structure (not shown), which runs through the stack structure and has a distance from the channel structure 318, and the common source structure includes a common source hole (not shown) and is arranged in a common A fill layer (not shown) in the source hole. The NAND memory array layer 310 may further include a ladder structure formed at the edge of the stacked structure and connected to the channel structure 318 through the conductor layer 314 . A plurality of contacts 342 in the connection layer 340 may be provided on the ladder structure for signal transmission.

In some embodiments, each 3D NAND channel structure 318 is a "charge trapping" type of NAND channel structure comprising a semiconductor channel (not shown) and a memory film (not shown). In some embodiments, the semiconductor channel includes silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping/storage layer"), and a blocking layer. Each 3D NAND channel structure 318 may have a cylindrical shape (eg, pillar shape). According to some embodiments, the semiconductor channel, the tunneling layer of the memory film, the memory layer, and the barrier layer are sequentially arranged in this order in a direction from the center of the pillar toward the outer surface. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, high-k (high-k) dielectric, or any combination thereof. In some embodiments of the present invention, the barrier layer may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO). In another example, the barrier layer may include a high-k dielectric layer, such as an aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), or tantalum oxide (Ta ₂ O ₅ ) layer, among others.

In some embodiments, the 3D NAND channel structure 318 may also include multiple control gates (each control gate is part of a word line). Each conductive layer 314 in the stacked structure can serve as a control gate for each memory cell of the 3D NAND channel structure 318 (thus the conductive layer 314 can also be referred to as a gate layer 314). In some embodiments, each 3D NAND channel structure 318 includes two plugs 311 and 319 at respective ends in the vertical direction. The plug 311 may include a semiconductor material, such as single crystal silicon, epitaxially grown from the substrate 301 . The plug 319 may serve as a channel controlled by the source select gate of the 3D NAND channel structure 318. The plug 311 may be at one end of the 3D NAND channel structure 318 and be in contact with the semiconductor channel. Another plug 319 may include a semiconductor material (eg, polysilicon). By covering the other end of the 3D NAND channel structure 318 during fabrication of the memory array chip 30, the plug 319 can be used as an etch stop layer to prevent etching of the dielectric filled in the 3D NAND channel structure 318, such as silicon oxide and silicon nitride . In some embodiments, the plug 319 serves as the drain of the 3D NAND channel structure 318.

It should be understood that the 3D NAND channel structure 318 is not limited to a "charge trapping" type of 3D NAND channel structure, and may be a "floating gate" type of 3D NAND channel structure in other embodiments. The substrate 301 may comprise polysilicon as a source plate of a "floating gate" type 3D NAND channel structure.

As shown in FIG. 3 , the memory array chip 30 may further include a pad lead-out interconnection layer 350 on the substrate 301 . Pad lead-out interconnect layer 350 may include interconnects, such as contact pads 352 , in one or more ILD layers. The pad lead-out interconnection layer 350 and the connection layer 340 may be formed on opposite sides of the substrate 301 . In some embodiments, the interconnects in the pad-out interconnection layer 350 may transmit electrical signals between the three-dimensional memory and external circuits, eg, for pad-out purposes.

In some embodiments, the memory array chip 30 further includes one or more contacts 354 extending through the substrate 301 to electrically connect pads leading out the interconnection layer 350 and the connection layers 340 and 490 . As a result, the peripheral circuit chip 40 and the memory array chip 30 may be electrically connected through the connection layers 340 and 490 and the bonding contacts 362 and 491 . In addition, the peripheral circuit chip 40 and the memory array chip 30 may be electrically connected to an external circuit through the contact 354 and the pad lead-out interconnection layer 350 .

It should be understood that the memory array chip 30 shown in FIG. 3 is only exemplary, and the memory array chip 30 according to the embodiment of the present invention is not limited thereto.

4 is a schematic cross-sectional view of a peripheral circuit chip of a three-dimensional memory according to another exemplary embodiment of the present invention. 5 is a schematic cross-sectional view of a NAND memory including a NAND memory array chip and the peripheral circuit chip of FIG. 4 according to another exemplary embodiment of the present invention.

In order to avoid redundancy, in the following description, only differences from the above-mentioned exemplary embodiments will be described, and descriptions of parts that are the same as or similar to the above-mentioned embodiment will be omitted or simplified.

As shown in FIG. 4, a peripheral circuit chip 60 of a three-dimensional memory according to another exemplary embodiment of the present invention may include a substrate 601, a first circuit element layer 602, a substrate 603, a second circuit element layer 604, a substrate 605 and the third circuit element layer 606.

The first layer of circuit elements 602, the second layer of circuit elements 604, and the third layer of circuit elements 606 may include any suitable digital, analog, and mixed-signal control and sensing circuitry for facilitating three-dimensional memory, including but not limited to page buffers. , decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current and voltage references, or any active or passive components of a circuit (e.g., transistor , diodes, resistors, or capacitors), and therefore, the first circuit element layer 602, the second circuit element layer 604, and the third circuit element layer 606 may respectively include device layers (which include devices such as transistors) that implement these functions and a connection layer (including connection wiring, contacts, etc.) for receiving electrical signals from the device layer or transmitting electrical signals to the device layer. For example, the first circuit element layer 602 may include a first device layer 610 and a first connection layer 620, the second circuit element layer 604 may include a second device layer 630 and a second connection layer 640, and the third circuit element layer 606 may A third device layer 660 and a third connection layer 670 are included.

As mentioned above, the substrate 601 may include single crystal silicon, polycrystalline silicon, amorphous silicon, germanium (Ge) substrate, silicon germanium (SiGe), gallium arsenide (GaAs), SOI (Silicon-on-insulator, on-insulator silicon) substrate or GOI (Germanium-on-insulator, germanium-on-insulator), salicide or any other suitable material.

As mentioned above, considering that the performance of the transistor formed first in the lower layer and its connecting wiring and contacts may be affected by the process of the transistor formed later in the upper layer, and the resistivity of the contact contacting the transistor with a lower operating voltage is usually required to be very low , in order to simplify the process of forming the transistors in the circuit element layer and improve the stability of the transistors, the transistors with different operating voltages to be used in the peripheral circuit chip 60 can be respectively formed on different substrates, that is, with different Transistors for operating voltages are respectively formed in different circuit element layers. In the example shown in FIG. 4, the devices in the first device layer 610 may include high-voltage devices (eg, high-voltage transistors), the devices in the second device layer 630 may include low-voltage devices (eg, low-voltage transistors), and the devices in the second device layer 630 may include low-voltage devices (eg, low-voltage transistors), and The devices in the three-device layer 660 may include very low voltage devices (for example, very low voltage transistors), for example, the operating voltage of each of the first transistors 611 may be greater than the operating voltage of each of the second transistors 631, and the second The operating voltage of each of the transistors 631 may be greater than that of each of the third transistors 661 . It should be noted that the high voltage, low voltage and extremely low voltage here are all relative terms, which can be divided according to chip design, and there is no special limitation. In the exemplary embodiment shown in FIG. 4 , for example, high voltage may represent greater than 10 volts, low voltage may represent 2.2 volts to 6 volts, and very low voltage may represent less than 1.8 volts. In a preferred embodiment of the present invention, the size of the high-voltage transistor can be larger than that of the low-voltage transistor, and the size of the low-voltage transistor can be larger than that of the very low-voltage transistor. For example, the thickness of the gate layer of the high-voltage transistor can be larger than that of the low-voltage transistor. The thickness of the gate layer, and the thickness of the gate layer of the low-voltage transistor may be greater than the thickness of the gate layer of the extremely low-voltage transistor, for example, the size of each of the first transistors 611 may be greater than that of each of the second transistors 631 size, and the size of each of the second transistors 631 may be larger than the size of each of the third transistors 661.

In the embodiment shown in FIG. 4, the melting point of the conductive material of the connecting wiring 621 and the contact 622 of the first connection layer 620 may be greater than or equal to that of the conductive material of the connecting wiring 641 and the contact 642 of the second connection layer 640. and the melting point of the conductive material of the connection wiring 641 and the contact 642 of the second connection layer 640 may be greater than or equal to the melting point of the conductive material of the connection wiring 671 and the contact 672 of the third connection layer 670 . In some examples of the present invention, the resistivity of the conductive material of the connection wiring 671 and the contact 672 of the third connection layer 670 may be smaller than the resistivity of the conductive material of the connection wiring 641 and the contact 642 of the second connection layer 640, and The resistivity of the conductive material of the connection wiring 641 and the contact 642 of the second connection layer 640 may be smaller than the resistivity of the conductive material of the connection wiring 621 and the contact 622 of the first connection layer 620 . In some exemplary embodiments of the present invention, the conductive material of the first connection layer 620 may be silicide such as WSi or TSi, the conductive material of the second connection layer 640 may be silicide such as TSi or CoSi, and the third The conductive material of the connection layer 670 may be silicide such as NiSi, but the invention is not limited thereto. For example, when the connection wiring 621 and the contact 622 of the first connection layer 620 include WSi, the connection wiring 641 and the contact 642 of the second connection layer 640 may include TiSi, CoSi, and the connection wiring 671 and The contact 672 may include NiSi; when the connection wiring 621 and the contact 622 of the first connection layer 620 include TiSi, the connection wiring 641 and the contact 642 of the second connection layer 640 may include CoSi, and the connection of the third connection layer 670 The wiring 671 and the contact 672 may be NiSi; however, the present invention is not limited thereto. In an exemplary embodiment of the present invention, the conductive material of the first connection layer 620 can still maintain the required contact resistance with the gate, source or drain of the first transistor 611 at least 500 degrees Celsius (° C.) The performance of the first transistor 611 is not affected, and the conductive material of the second connection layer 640 can still maintain the required contact resistance with the second transistor 631 at a temperature of at least 450° C. so that the performance of the second transistor 631 is not affected; However, the present invention is not limited thereto.

It has been described above that the operating voltage of the first transistor 611 is greater than the operating voltage of the second transistor 631, the operating voltage of the second transistor 631 is greater than the operating voltage of the third transistor 661, and the size of the first transistor 611 is greater than the size of the second transistor 631, The size of the second transistor 631 is larger than the preferred embodiment of the size of the third transistor 661 . However, it should be understood that the present invention is not limited thereto. For example, in some other embodiments, the operating voltage of at least one first transistor 611 may be greater than the operating voltage of at least one second transistor 631, and the operating voltage of at least one second transistor 631 The voltage may be greater than the operating voltage of at least one third transistor 661 . In yet other embodiments, the size of at least one first transistor 611 may be larger than the size of at least one second transistor 631 , and the size of at least one second transistor 631 may be larger than the size of at least one third transistor 661 .

The peripheral circuit chip 60 may further include a first interconnection layer having a contact 651 electrically connecting the first connection layer 620 with the second connection layer 640 . The peripheral circuit chip 60 may further include a second interconnection layer having a contact 655 electrically connecting the second connection layer 640 with the third connection layer 670 . Although in the embodiment described with reference to FIG. The second interconnection layer, but those skilled in the art should understand that the present invention is not limited thereto. For example, in other embodiments of the present invention, the peripheral circuit chip 60 may not include these interconnection layers according to chip design requirements, or may also include a third interconnection layer electrically connecting the first connection layer 620 and the third connection layer 670 . or the peripheral circuit chip 60 may include at least one of the first interconnection layer, the second interconnection layer and the third interconnection layer according to chip design requirements.

In the following, the peripheral circuit chip 60 in FIG. 4 includes the first interconnection layer and the second interconnection layer as an example for illustration, but the present invention is not limited thereto. Each of the first interconnect layer and the second interconnect layer may include multiple interconnects (also referred to as "contacts"), such as vertical interconnect access (via) contacts, as required by the chip design . Each of the contact 651 of the first interconnection layer and the contact 655 of the second interconnection layer may be formed using a conductive material (including but not limited to such as W, Co, Cu, Al, etc.). In an optional embodiment, the conductive material of at least one of the contact 651 of the first interconnection layer and the contact 655 of the second interconnection layer is W. Each of the first interconnection layer and the second interconnection layer may further include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers", not shown), which may Contacts are formed. The ILD layer in each of the first interconnect layer and the second interconnect layer may also include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof, to Contacts and the like in each of the first interconnection layer and the second interconnection layer are electrically isolated from other elements.

Transistors in the first device layer 610, the second device layer 630, and the third device layer 660 may be formed on substrates 601, 603, and 605, respectively. As mentioned above, in the present invention, a transistor formed "on" a substrate may mean that the whole or part of the transistor is formed in the substrate (eg, below the top surface of the substrate) and/or directly on the substrate, It depends on the material of the substrate and the type and material of the transistor.

The substrates 603 and 605 can be formed by a single crystal silicon growth process, respectively, or can be formed by first growing polysilicon and then heat-treating the polysilicon. It should be understood that the substrates 603 and 605 are not limited to silicon substrates, and may also be any other suitable materials such as germanium substrates.

Similar to the example of FIG. 2 , the peripheral circuit chip 60 may further include a bonding layer 690 for bonding the peripheral circuit chip 60 to the memory array chip. The bonding layer 690 may include a plurality of conductive contacts 691, and the conductive contacts 691 may be bonded with corresponding conductive contacts in the memory array chip to form a three-dimensional memory. As shown in FIG. 5 , the NAND memory array chip 30 can be bonded with the peripheral circuit chip 60 through corresponding bonding contacts in the bonding layers 690 and 360 to form a NAND three-dimensional memory. It should be understood that the peripheral circuit chip 60 shown in FIG. 4 can be applied to any three-dimensional memory, not limited to the NAND three-dimensional memory shown in FIG. 5 .

A method of manufacturing a three-dimensional memory including a peripheral circuit chip according to the present invention will be described below with reference to FIGS. 6 to 7 .

FIG. 6 is a flowchart illustrating a part of a method of manufacturing a three-dimensional memory including the peripheral circuit chip shown in FIG. 2 according to the present invention. FIG. 7 is a flowchart illustrating a method of manufacturing a three-dimensional memory including the peripheral circuit chip shown in FIG. 4 according to the present invention.

According to an exemplary embodiment of the present invention, the method 1000 of manufacturing a three-dimensional memory may form a peripheral circuit chip based on a first substrate.

Referring to FIG. 2 and FIG. 6, the method 1000 may include: step S110, sequentially forming the first device layer 410 and the first connection layer 420 for signal transmission of the first device layer 410 on the first substrate 401; step S120, Form a second substrate 403 on the first connection layer 420, and form a second device layer 430 and a second connection layer 440 for signal transmission of the second device layer 430 on the second substrate 403; Step S130, in A bonding layer 490 having conductive contacts (ie, bonding contacts 491 ) is formed on the second connection layer 440 .

As described with reference to FIG. 2 , the first device layer 410 may include a plurality of first transistors 411 , and the second device layer 430 may include a plurality of second transistors 431 . In a preferred embodiment according to the present invention, the operating voltage of each of the first transistors 411 may be greater than the operating voltage of each of the second transistors 431 . In yet another preferred embodiment of the present invention, the size of each of the first transistors 411 may be larger than the size of each of the second transistors 431, for example, the gate layer of each of the first transistors 411 The thickness may be greater than that of the gate layer of each of the second transistors 431 . However, the present invention is not limited thereto. For example, in some other implementations, the operating voltage of at least one first transistor 411 may be greater than the operating voltage of at least one second transistor 431 . In yet other embodiments, the size of at least one first transistor 411 may be larger than the size of at least one second transistor 431 .

Forming the first connection layer 420 may include: forming a first dielectric layer on the first device layer 410; and forming conductive wiring (connecting wiring 421) and contacts for signal transmission in the first dielectric layer using a first conductive material 422. In the concept of the present invention, the first conductive material includes but not limited to W, Co, Cu, Al, silicide or any combination thereof, and the first dielectric material includes but not limited to silicon oxide, silicon nitride, silicon oxynitride, low k dielectric or any combination thereof. In some embodiments of the present invention, the first conductive material may be WSi or TiSi.

Forming the second connection layer 440 may include: forming a second dielectric layer on the second device layer 430; and forming conductive wiring (connecting wiring 441) and contacts for signal transmission in the second dielectric layer using a second conductive material. 442. In an embodiment of the present invention, the second conductive material includes but not limited to W, Co, Cu, Al, silicide or any combination thereof, and the second dielectric material includes but not limited to silicon oxide, silicon nitride, silicon oxynitride , low-k dielectrics, or any combination thereof. In some embodiments of the present invention, the second conductive material may be TiSi, CoSi or NiSi. According to an exemplary embodiment of the present invention, the melting point of the first conductive material may be greater than or equal to the melting point of the second conductive material.

In addition, according to chip design requirements, the method 1000 may further include: before forming the bonding layer 490 , forming a first interconnection layer electrically connecting the first connection layer 420 and the second connection layer 440 . According to some exemplary embodiments of the present invention, the first interconnection layer may include W.

According to an exemplary embodiment of the present invention, the method 2000 of manufacturing a three-dimensional memory may form a peripheral circuit chip based on a first substrate.

4 and 7, the method 2000 may include: step S210, sequentially forming the first device layer 610 and the first connection layer 620 for signal transmission of the first device layer 610 on the first substrate 601; step S220, Form a second substrate 603 on the first connection layer 620, and sequentially form a second device layer 630 and a second connection layer 640 for signal transmission of the second device layer 630 on the second substrate 603; step S230, Form a third substrate 605 on the second connection layer 640, and sequentially form a third device layer 660 and a third connection layer 670 for signal transmission of the third device layer 660 on the third substrate 605; step S240, A bonding layer 690 having conductive contacts 691 is formed on the third connection layer 670 .

As described with reference to FIG. 4 , the first device layer 610 may include a plurality of first transistors 611 , the second device layer 630 may include a plurality of second transistors 631 , and the third device layer 660 may include a plurality of third transistors 661 . In a preferred embodiment according to the present invention, the operating voltage of each of the first transistors 611 can be greater than the operating voltage of each of the second transistors 631, and the operating voltage of each of the second transistors 631 can be greater than the operating voltage of each of the third transistors 661 . In another preferred embodiment according to the present invention, the size of each of the first transistors 611 may be larger than that of each of the second transistors 631, and the size of each of the second transistors 631 may be larger than that of the first transistors 631. The size of each of the three transistors 661. For example, the thickness of the gate layer of each of the first transistors 611 may be greater than the thickness of the gate layer of each of the second transistors 631, and the thickness of the gate layer of each of the second transistors 631 may be greater than The thickness of the gate layer of each of the third transistors 661. However, it should be understood that the present invention is not limited thereto. For example, in some other implementations, the operating voltage of at least one first transistor 611 may be greater than the operating voltage of at least one second transistor 631, and the operating voltage of at least one second transistor 631 may be greater than that of at least one third transistor 661. Operating Voltage. In some other embodiments of the present invention, the size of at least one first transistor 611 may be larger than the size of at least one second transistor 631 , and the size of at least one second transistor 631 may be larger than the size of at least one third transistor 661 .

Forming the first connection layer 620 may include: forming a first dielectric layer on the first device layer 610; and forming conductive wiring (connecting wiring 621) and contacts for signal transmission in the first dielectric layer using a first conductive material. 622. In the concept of the present invention, the first conductive material includes but not limited to W, Co, Cu, Al, silicide or any combination thereof, and the first dielectric material includes but not limited to silicon oxide, silicon nitride, silicon oxynitride, low k dielectric or any combination thereof. In some embodiments of the present invention, the first conductive material may be WSi or TiSi.

Forming the second connection layer 640 may include: forming a second dielectric layer on the second device layer 630; and forming conductive wiring (connecting wiring 641) and contacts for signal transmission in the second dielectric layer using a second conductive material. 642. In an embodiment of the present invention, the second conductive material includes but not limited to W, Co, Cu, Al, silicide or any combination thereof, and the second dielectric material includes but not limited to silicon oxide, silicon nitride, silicon oxynitride , low-k dielectrics, or any combination thereof. In some embodiments of the present invention, the second conductive material may be TiSi or CoSi.

Forming the third connection layer 670 may include: forming a third dielectric layer on the third device layer 660; forming a conductive wiring (connecting wiring 671) and a contact 672 for signal transmission in the third dielectric layer using a third conductive material . In an embodiment of the present invention, the third conductive material includes but not limited to W, Co, Cu, Al, silicide or any combination thereof, and the second dielectric material includes but not limited to silicon oxide, silicon nitride, silicon oxynitride , low-k dielectrics, or any combination thereof. In some embodiments of the present invention, the third conductive material may be NiSi. According to an exemplary embodiment of the present invention, the melting point of the first conductive material may be greater than or equal to the melting point of the second conductive material, and the melting point of the second conductive material may be greater than or equal to the melting point of the third conductive material.

In addition, according to chip design requirements, the method 2000 may further include forming at least one of the first interconnection layer, the second interconnection layer and the third interconnection layer, wherein the first interconnection layer connects the first connection layer 620 and the second interconnection layer The two connection layers 640 are electrically connected, the second interconnection layer is electrically connected to the second connection layer 640 and the third connection layer 670 , and the third interconnection layer is electrically connected to the first connection layer 620 and the third connection layer 670 . According to some exemplary embodiments of the present invention, at least one of the first interconnection layer, the second interconnection layer and the third interconnection layer includes W.

After the peripheral circuit chip according to the present invention is fabricated using the method described with reference to FIGS. 6 to 7, the corresponding memory array chip and the peripheral circuit chip may be bonded to form a three-dimensional memory.

The above description is only an embodiment of the present invention and an illustration of the applied technical principles. Those skilled in the art should understand that the scope of protection involved in the present invention is not limited to the technical solution formed by the specific combination of the above-mentioned technical features, and should also cover the technical solution formed by the above-mentioned technical features or other technical solutions without departing from the technical conception. Other technical solutions formed by any combination of equivalent features. For example, a technical solution formed by replacing the above-mentioned features with technical features disclosed in the present invention (but not limited to) having similar functions.

Claims (22)

1. A three-dimensional memory comprising a peripheral circuit chip and a memory array chip corresponding thereto, the peripheral circuit chip for facilitating signal control and sensing of the three-dimensional memory, the peripheral circuit chip comprising:

a first substrate;

a first circuit element layer disposed on the first substrate and including a first device layer and a first connection layer for signal transmission of the first device layer;

a second substrate disposed on the first circuit element layer; and

a second circuit element layer disposed on the second substrate and including a second device layer and a second connection layer for signal transmission of the second device layer,

wherein the first device layer comprises a plurality of first transistors, the second device layer comprises a plurality of second transistors, an

Wherein an operating voltage of each of the plurality of first transistors is greater than an operating voltage of each of the plurality of second transistors,

wherein each of the first connection layer and the second connection layer comprises a conductive material, a melting point of the conductive material of the first connection layer is greater than or equal to a melting point of the conductive material of the second connection layer, and a resistivity of the conductive material of the second connection layer is less than a resistivity of the conductive material of the first connection layer.

2. The three-dimensional memory of claim 1, wherein a size of each of the plurality of first transistors is larger than a size of each of the plurality of second transistors.

3. The three-dimensional memory according to claim 1, wherein the conductive material of the first connection layer is WSi or TiSi and the conductive material of the second connection layer is TiSi or CoSi.

4. The three-dimensional memory according to any one of claims 1 to 3, wherein the peripheral circuit chip further comprises:

a third substrate disposed on the second circuit element layer; and

a third circuit element layer disposed on the third substrate and including a third device layer and a third connection layer for signal transmission of the third device layer.

5. The three-dimensional memory of claim 4, wherein the peripheral circuit chip further comprises at least one of a first interconnect layer, a second interconnect layer, and a third interconnect layer,

wherein:

the first interconnect layer electrically connecting the first connection layer with the second connection layer for signal transmission between the first device layer and the second device layer,

the second interconnect layer electrically connecting the third connection layer with one of the first connection layer and the second connection layer for signal transmission between the third connection layer and the one connection layer; and

the third interconnect layer electrically connects the third connection layer with the other of the first connection layer and the second connection layer for signal transmission between the third connection layer and the other connection layer.

6. The three-dimensional memory of claim 5, wherein at least one of the first interconnect layer, the second interconnect layer, and the third interconnect layer comprises W.

7. The three-dimensional memory according to claim 4,

wherein the third device layer includes a plurality of third transistors, an

Wherein an operating voltage of each of the plurality of second transistors is greater than an operating voltage of each of the plurality of third transistors.

8. The three-dimensional memory of claim 7, wherein a size of each of the plurality of first transistors is greater than a size of each of the plurality of second transistors, and a size of each of the plurality of second transistors is greater than a size of each of the plurality of third transistors.

9. The three-dimensional memory according to claim 8, wherein at least one of the first transistor, the second transistor, and the third transistor is a metal oxide semiconductor field effect transistor.

10. The three-dimensional memory according to claim 4,

wherein each of the first connection layer, the second connection layer, and the third connection layer comprises a conductive material,

wherein a melting point of the conductive material of the second connection layer is greater than or equal to a melting point of the conductive material of the third connection layer, and a resistivity of the conductive material of the third connection layer is less than a resistivity of the conductive material of the second connection layer.

11. The three-dimensional memory according to claim 10, wherein the conductive material of the first connection layer is WSi or TiSi, the conductive material of the second connection layer is TiSi or CoSi, and the conductive material of the third connection layer is NiSi.

12. The three-dimensional memory of claim 11,

wherein the first connection layer further comprises a first dielectric layer for electrically isolating the conductive material of the first connection layer,

wherein the second connection layer further comprises a second dielectric layer for electrically isolating the conductive material of the second connection layer, an

Wherein the third connection layer further comprises a third dielectric layer for electrically isolating the conductive material of the third connection layer.

13. The three-dimensional memory of claim 1, wherein the memory array chip comprises a memory array layer comprising a plurality of memory strings disposed in a stacked configuration and a first bonding layer disposed on the memory array layer for bonding with a second bonding layer in the peripheral circuit chip.

14. The three-dimensional memory of claim 13, wherein the second bonding layer is disposed on the second circuit element layer.

15. A method for fabricating a three-dimensional memory, the method comprising forming a peripheral circuit chip based on a first substrate, the peripheral circuit chip for facilitating signal control and sensing of the three-dimensional memory, the three-dimensional memory further comprising a memory array chip corresponding to the peripheral circuit chip, comprising:

sequentially forming a first device layer and a first connecting layer for signal transmission of the first device layer on the first substrate;

forming a second substrate on the first connection layer, and sequentially forming a second device layer and a signal transmission second connection layer for the second device layer on the second substrate; and

forming a bonding layer having conductive contacts on the second connection layer,

wherein the first device layer comprises a plurality of first transistors, the second device layer comprises a plurality of second transistors, an

Wherein an operating voltage of each of the plurality of first transistors is greater than an operating voltage of each of the plurality of second transistors,

wherein the first connection layer comprises a first conductive material, the second connection layer comprises a second conductive material, the first conductive material has a melting point greater than or equal to a melting point of the second conductive material, and the second conductive material has a resistivity less than the resistivity of the first conductive material.

16. The method of claim 15, wherein a size of each of the plurality of first transistors is larger than a size of each of the plurality of second transistors.

17. The method of claim 15, wherein,

forming the first connection layer includes:

forming a first dielectric layer on the first device layer;

forming conductive wiring and conductive contacts for signal transmission in the first dielectric layer using the first conductive material,

forming the second connection layer includes:

forming a second dielectric layer on the second device layer;

conductive wiring and conductive contacts for signal transmission are formed in the second dielectric layer using the second conductive material.

18. The method according to any one of claims 15-17, further comprising: forming a third substrate on the second connection layer, and sequentially forming a third device layer and a signal transmission third connection layer for the third device layer on the third substrate, an

Wherein the bonding layer is located on the third connection layer.

19. The method of claim 18, wherein,

the third device layer includes a plurality of third transistors, an

An operating voltage of each of the plurality of second transistors is greater than an operating voltage of each of the plurality of third transistors.

20. The method of claim 19, wherein a size of each of the plurality of first transistors is greater than a size of each of the plurality of second transistors, and a size of each of the plurality of second transistors is greater than a size of each of the plurality of third transistors.

21. The method of claim 18, wherein,

forming the first connection layer includes:

forming a first dielectric layer on the first device layer;

forming conductive wiring and conductive contacts for signal transmission in the first dielectric layer using the first conductive material,

forming the second connection layer includes:

forming a second dielectric layer on the second device layer;

forming conductive wiring and conductive contact for signal transmission in the second dielectric layer using the second conductive material, an

Forming the third connection layer includes:

forming a third dielectric layer on the third device layer;

forming conductive wiring and conductive contact for signal transmission in the third dielectric layer using a third conductive material, an

Wherein a melting point of the second conductive material is greater than or equal to a melting point of the third conductive material, and a resistivity of the third conductive material is less than a resistivity of the second conductive material.

22. The method of claim 18, further comprising:

forming at least one of a first interconnect layer, a second interconnect layer, and a third interconnect layer,

wherein the first interconnect layer electrically connects the first connection layer with the second connection layer, the second interconnect layer electrically connects the second connection layer with the third connection layer, and the third interconnect layer electrically connects the first connection layer with the third connection layer.

Images