CN112992830B - Semiconductor structure and method for manufacturing the same - Google Patents

Semiconductor structure and method for manufacturing the same Download PDF

Info

Publication number
CN112992830B
CN112992830B CN201911213085.0A CN201911213085A CN112992830B CN 112992830 B CN112992830 B CN 112992830B CN 201911213085 A CN201911213085 A CN 201911213085A CN 112992830 B CN112992830 B CN 112992830B
Authority
CN
China
Prior art keywords
layer
forming
material layer
groove
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201911213085.0A
Other languages
Chinese (zh)
Other versions
CN112992830A (en
Inventor
吴秉桓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN201911213085.0A priority Critical patent/CN112992830B/en
Publication of CN112992830A publication Critical patent/CN112992830A/en
Application granted granted Critical
Publication of CN112992830B publication Critical patent/CN112992830B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/11013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8536—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/85365—Shape, e.g. interlocking features

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises a supporting layer, a welding pad and a welding pad, wherein the supporting layer comprises a welding pad area, a plurality of grooves are formed in the welding pad area of the supporting layer, the welding pad is positioned on the supporting layer and at least positioned in the welding pad area, and the welding pad is partially embedded into the grooves. In the semiconductor structure, the supporting layer with the plurality of grooves is formed in the bonding pad area below the bonding pad, even if the bonding pad is flat and most of the bonding pad can be displaced under the action of bonding pressure in the bonding process of the bonding wire, the bottom of the bonding wire can be partially sunk into the grooves due to the supporting layer with the grooves below the bonding pad, so that the contact surface of the bonding wire and the bonding pad is uneven, the adhesiveness of the bonding wire and the bonding pad is increased, and the falling risk of the bonding wire is reduced.

Description

Semiconductor structure and preparation method thereof
Technical Field
The application relates to the technical field of semiconductor device manufacturing, in particular to a semiconductor structure and a preparation method thereof.
Background
In the prior art, in order to increase the adhesion between the bonding wire and the bonding Pad, the surface of the bonding Pad needs to be roughened before the bonding wire bonding process when the bonding wire bonding (wire bonding) process is performed on the bonding Pad (Pad), and then, because the bonding Pad is generally soft aluminum, the bonding Pad is flattened quickly under the action of bonding pressure (bonding force) during the bonding wire bonding process, so that the effect of enhancing the adhesion between the bonding wire and the bonding Pad cannot be achieved. Meanwhile, because the bonding wires flatten the bonding pads below the bonding wires, current can only flow from the two side areas of the bonding wires during operation, which can cause the current amount during operation to be obviously reduced, and if the opening in the protective layer is too small or the bonding wires are askew, the bonding wires are adjacent to the protective layer, the protective layer can be lifted upwards or split under the bonding pad layer which is discharged outwards after extrusion, or the bonding pads are overflowed, so that the quality problem is caused.
Disclosure of Invention
Based on this, it is necessary to provide a semiconductor structure and a method for manufacturing the same in view of the above-mentioned problems in the prior art.
To achieve the above object, in one aspect, the present invention provides a semiconductor structure, comprising:
The support layer comprises a pad area, wherein the support layer in the pad area is provided with a plurality of grooves;
and the welding pad is positioned on the supporting layer and at least positioned in the welding pad area, and the welding pad is partially embedded into the groove.
In the semiconductor structure, the supporting layer with the plurality of grooves is formed in the bonding pad area below the bonding pad, even if the bonding pad is flat and most of the bonding pad can be displaced under the action of bonding pressure in the bonding process of the bonding wire, the bottom of the bonding wire can be partially sunk into the grooves due to the supporting layer with the grooves below the bonding pad, so that the contact surface of the bonding wire and the bonding pad is uneven, the adhesiveness of the bonding wire and the bonding pad is increased, and the falling risk of the bonding wire is reduced.
In one embodiment, the supporting layer is of a single-layer structure, the supporting layer comprises a dielectric layer or a polymer layer, and the depth of the groove is smaller than or equal to the thickness of the supporting layer.
In one embodiment, the support layer is a laminated structure, and the support layer includes:
the first material layer is internally provided with an initial groove, and the depth of the initial groove is smaller than or equal to the thickness of the first material layer;
the second material layer is positioned on the upper surface of the first material layer, the side wall of the initial groove and the bottom of the initial groove, and the thickness of the second material layer is smaller than the depth of the initial groove.
In one embodiment, the support layer is a laminated structure, and the support layer includes:
a first material layer;
The second material layer is positioned on the upper surface of the first material layer, a plurality of grooves are formed in the second material layer, and the depth of each groove is smaller than or equal to the thickness of the second material layer.
In one embodiment, the first material layer is a dielectric layer and the second material layer is a polymer layer, or the first material layer is a polymer layer and the second material layer is a dielectric layer.
In one embodiment, the semiconductor structure further comprises:
A substrate having an integrated circuit formed therein;
The support layer is positioned on the upper surface of the passivation layer;
the rewiring layer is positioned on the supporting layer and connected with the integrated circuit and the welding pad;
A seed layer located between the support layer and the bond pad, between the rewiring layer and the support layer, and between the rewiring layer and the integrated circuit;
The protective layer is positioned on the upper surface of the supporting layer and covers the rewiring layer and the welding pad, and an opening is formed in the protective layer and exposes the welding pad;
And one end of the bonding wire is positioned in the opening and is connected with the bonding pad.
In one example, the bottom of the bonding wire is spaced from the bottom of the groove. The bottom of bonding wire has the interval with the bottom of recess, can make bonding wire and recess bottom between remain the bonding pad, during operation, electric current can circulate through the bonding pad in the recess in addition to circulate through the bonding pad of bonding wire both sides to the electric current volume during operation increases.
In one example, the protective layer of the lower portion of the opening has a gap therein such that the width of the lower portion of the opening is greater than the width of the upper portion of the opening. Through forming the breach in the protection layer of opening lower part, can form the buffer space in opening lower part, the breach can hold the bonding wire extrusion pad of arranging outward, avoids the protection layer to lift up or split, prevents the bonding pad excessive to ensure the quality of product.
The invention also provides a preparation method of the semiconductor structure, which comprises the following steps:
forming a supporting layer, wherein the supporting layer comprises a bonding pad area, and a plurality of grooves are formed in the bonding pad area of the supporting layer;
And forming a welding pad at least in the welding pad area of the supporting layer, wherein the welding pad is partially embedded into the groove.
In the preparation method of the semiconductor structure, the supporting layer with the plurality of grooves is formed in the bonding pad area below the bonding pad, even if the bonding pad is flat and most of the bonding pad can be displaced under the action of bonding pressure in the bonding process of the bonding wire, as the supporting layer with the grooves is arranged below the bonding pad, part of the area of the bottom of the bonding wire can sink into the grooves, so that the contact surface between the bonding wire and the bonding pad is in a convex-concave shape, the adhesiveness between the bonding wire and the bonding pad is increased, and the falling risk of the bonding wire is reduced.
In one embodiment, forming the support layer includes the steps of:
Forming a dielectric layer;
and etching the dielectric layer to form the groove in the dielectric layer, wherein the depth of the groove is smaller than or equal to the thickness of the dielectric layer.
In one embodiment, forming the support layer includes the steps of:
forming a polymer layer;
and exposing and developing the polymer layer to form the grooves in the polymer layer, wherein the depth of the grooves is smaller than or equal to the thickness of the polymer layer.
In one embodiment, forming the support layer includes the steps of:
Forming a first material layer;
Forming a second material layer on the upper surface of the first material layer;
And forming the groove in the second material layer, wherein the depth of the groove is smaller than or equal to the thickness of the second material layer.
In one embodiment, forming the support layer includes the steps of:
Forming a first material layer;
forming an initial groove in the first material layer, wherein the depth of the initial groove is smaller than or equal to the thickness of the first material layer;
and forming a second material layer on the upper surface of the first material layer, the side wall and the bottom of the initial groove.
In one embodiment, the first material layer is a dielectric layer and the second material layer is a polymer layer, or the first material layer is a polymer layer and the second material layer is a dielectric layer.
In one embodiment, the support layer is formed further comprising the following steps:
Providing a substrate, wherein an integrated circuit is formed in the substrate;
forming a passivation layer on the upper surface of the substrate, wherein the support layer is formed on the upper surface of the passivation layer;
Forming an interconnection hole in the supporting layer and the passivation layer before forming the welding pad in the groove, wherein the interconnection hole exposes the integrated circuit region;
forming a rewiring layer on the supporting layer while forming the welding pad in the welding pad area of the supporting layer, wherein the rewiring layer is connected with the welding pad and the integrated circuit;
The method further comprises the step of forming a seed layer on the upper surface of the supporting layer and in the interconnection hole before forming the welding pad and the rerouting layer, wherein the welding pad and the rerouting layer are formed on the upper surface of the seed layer;
The method further comprises the following steps after forming the bonding pad in the bonding pad area of the supporting layer:
Forming a protective layer on the upper surface of the supporting layer, wherein the protective layer covers the rewiring layer and the welding pad;
forming an opening in the protection layer, wherein the opening exposes the welding pad;
And providing a bonding wire, and connecting one end of the bonding wire with the bonding pad.
Drawings
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure in accordance with one embodiment of the present invention;
fig. 2 to 25 are schematic cross-sectional structures of structures obtained at various steps in a method for fabricating a semiconductor structure according to an embodiment of the present invention, wherein fig. 20 to 25 are schematic cross-sectional structures of different semiconductor structures according to another embodiment of the present invention.
Reference numerals illustrate:
10. support layer
101. A first material layer
102. A second material layer
103. Groove
104. Initial groove
11. Substrate
12. Passivation layer
13. Seed layer
14. Welding pad
15. Rewiring layer
16. Protective layer
161. An opening
162. Notch
163. Bottom protective layer
164. Top protective layer
17. Bonding wire
18. Alloy layer
19. Patterning mask layer
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to and integrated with the other element or intervening elements may also be present. The terms "mounted," "one end," "the other end," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In one embodiment, as shown in fig. 1, a method for fabricating a semiconductor structure according to the present invention includes the following steps:
S11, forming a supporting layer, wherein the supporting layer comprises a bonding pad area, and a plurality of grooves are formed in the bonding pad area of the supporting layer;
And S12, forming a welding pad at least in the welding pad area of the supporting layer, wherein the welding pad is partially embedded into the groove.
In the method for manufacturing the semiconductor structure, the supporting layer 10 with the plurality of grooves 103 in the pad area is formed under the bonding pad 14, namely, the supporting layer 10 with the grooves 103 in the pad area is formed first, then the bonding pad 14 is formed in the pad area of the supporting layer 10, and even if the bonding pad 14 is flat and most of the bonding pad 14 is displaced under the action of bonding pressure in the bonding wire bonding process, the supporting layer 10 with the grooves 103 is arranged under the bonding pad 14, part of the area at the bottom of the bonding wire is sunk into the grooves 103, so that the contact surface between the bonding wire and the bonding pad 14 is uneven, the adhesion between the bonding wire and the bonding pad 14 is increased, and the falling risk is reduced.
In one example, as shown in fig. 2, step S11 further includes the following steps:
Providing a substrate 11, wherein an integrated circuit structure (not shown) is formed in the substrate 11;
A passivation layer 12 is formed on the upper surface of the substrate 11, and a support layer 10 is formed on the upper surface of the passivation layer 12 in step S11.
In one example, the base 11 may include, but is not limited to, a silicon substrate.
In one example, the passivation layer 12 covers the upper surface of the substrate 11. The passivation layer 12 may include a single layer structure or a stacked structure including a plurality of material layers. Passivation layer 12 may include, but is not limited to, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
In an alternative example, the support layer 10 is a single layer structure, and the step S11 may include the steps of:
s111, forming a dielectric layer, namely a supporting layer 10, wherein the dielectric layer is formed on the upper surface of the passivation layer 12 as shown in FIG. 2, specifically, the dielectric layer can be formed by adopting a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process or the like, and the dielectric layer can comprise, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer or the like;
S112, etching the dielectric layer to form a groove 103 in the dielectric layer, wherein the depth of the groove 103 can be smaller than or equal to the thickness of the dielectric layer, specifically, firstly, forming a patterned mask layer 19 on the upper surface of the dielectric layer, as shown in FIG. 2, wherein the patterned mask layer 19 can comprise but is not limited to a patterned photoresist layer, then, carrying out dry etching or wet etching on the dielectric layer based on the patterned mask layer 19 to form the groove 103 in the dielectric layer, and finally, removing the patterned mask layer 19, as shown in FIGS. 3 and 4.
When the depth of the groove 103 may be smaller than the thickness of the dielectric layer, as shown in fig. 3, the depth of the groove 103 may be set according to practical needs, for example, the depth of the groove 103 may be 1/3, 2/3, or 3/4 of the thickness of the dielectric layer, or, of course, in other examples, the depth of the groove 103 may be equal to the thickness of the dielectric layer, as shown in fig. 4, that is, the groove 103 penetrates through the dielectric layer in the thickness direction.
In another alternative example, the support layer 10 is a single layer structure, and the step S11 may include the steps of:
s111, forming a polymer layer, namely a supporting layer 10, specifically, forming a polymer layer on the upper surface of the passivation layer 12 by using, but not limited to, spin coating process, wherein the polymer layer may include, but not limited to, a Polyimide (PI) layer or a polybenzoxazole (Polybenzox, PBO) layer;
And S112, exposing and developing the polymer layer to form a groove 103 in the polymer layer, wherein the depth of the groove 103 can be smaller than or equal to the thickness of the polymer layer, specifically, exposing and developing the polymer layer directly based on a double exposure process or a light shielding/transmitting alternating photomask to form the groove 103 in the polymer layer, and the formed structure can be shown in figures 3 and 4.
While the depth of the groove 103 may be smaller than the thickness of the polymer layer, as shown in fig. 3, the depth of the groove 103 may be set according to practical needs, for example, the depth of the groove 103 may be 1/3, 2/3, or 3/4 of the thickness of the polymer layer, or the like, and of course, in other examples, the depth of the groove 103 may be equal to the thickness of the polymer layer, as shown in fig. 4, that is, the groove 103 penetrates the polymer layer in the thickness direction.
In yet another example, the support layer 10 is a laminated structure, and the step S11 includes the steps of:
s111, forming a first material layer 101;
S112, forming a second material layer 102 on the upper surface of the first material layer 101, wherein the second material layer 102 and the first material layer 101 together form the supporting layer 10;
and S113, forming a groove 103 in the second material layer 102, wherein the depth of the groove 103 is smaller than or equal to the thickness of the second material layer 102.
In one example, the first material layer 101 may be a polymer layer and the second material layer 102 may be a dielectric layer, at this time, in step S111, the first material layer 101 may be formed on the upper surface of the passivation layer 12 by using, but not limited to, a spin-coating process, the first material layer 101 may include, but not limited to, a polyimide layer or a polybenzoxazole layer, in step S112, the second material layer 102 may be formed by using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like, the second material layer 102 may include, but not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like, in step S113, the patterned mask layer 19 may include, but not limited to, a patterned photoresist layer, in step S111, may include, but not limited to, a polyimide layer or a polybenzoxazole layer, in step S112, the second material layer 102 may be formed by using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, a atomic layer deposition process, or the like, in step S112, the second material layer 102 may include, but not limited to be formed on the upper surface of the second material layer 102, and may be formed, in a patterned mask layer 19, in step S113, as shown in fig. 5, may be formed.
In another example, the first material layer 101 may be a medium, and the second material layer 102 may be a polymer layer, at this time, in step S111, the first material layer 101 may be formed by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like, the first material layer 101 may include but is not limited to a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, or the like, in step S112, the second material layer 102 may be formed by a spin-coating process, and the second material layer 102 may include but is not limited to a polyimide layer or a polybenzoxazole layer, in step S113, the second material layer 102 may be directly exposed and developed based on a double exposure process or a light-shielding/light-transmitting alternating mask, so as to form the groove 103 in the second material layer 102.
In the above example, the recess 103 is formed and an interconnect hole (not shown) is formed in the support layer 10 and the passivation layer 12, and the interconnect hole exposes the integrated circuit region.
In yet another example, step S11 may include the steps of:
s111, forming a first material layer 101;
s112, performing exposure and development on the first material layer 101 to form an initial groove 104 in the first material layer 101, wherein the depth of the initial groove 104 is less than or equal to the thickness of the first material layer 101;
S113, forming a second material layer 102 on the upper surface of the first material layer 101, the side wall and the bottom of the initial groove 104, wherein the thickness of the second material layer 102 is smaller than the depth of the initial groove 104, as shown in FIG. 9 and FIG. 10, and the first material layer 101 and the second material layer 102 together form the supporting layer 10.
In one example, the first material layer 101 may be a polymer layer and the second material layer 102 may be a dielectric layer, in step S111, the first material layer 101 may be formed on the upper surface of the passivation layer 12 by using, but not limited to, a spin-coating process, the first material layer 101 may include, but not limited to, a polyimide layer or a polybenzoxazole layer, in step S112, the first material layer 101 may be directly subjected to exposure and development based on a dual exposure process or a light-shielding/light-transmitting alternating photomask to form an initial groove 104 in the first material layer 101, the depth of the initial groove 104 may be smaller than the thickness of the first material layer 101 (as shown in fig. 7) or may be equal to the thickness of the first material layer 101 (as shown in fig. 8), in step S113, the second material layer 102 may be formed by using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like, and the second material layer 102 may include, but not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.
In another example, the first material layer 101 may be a dielectric layer and the second material layer 102 may be a polymer layer, in step S111, the first material layer 101 may be formed by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like, the first material layer 101 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, or the like, in step S112, a patterned mask layer (not shown) may be formed on an upper surface of the first material layer 101, the patterned mask layer may include, but is not limited to, a patterned photoresist layer, then the first material layer 101 is etched based on the patterned mask layer, and finally the patterned mask layer is removed, in step S113, the second material layer 102 may be formed by a spin-on process, and the second material layer 102 may include, but is not limited to, a polyimide layer or a polybenzoxazole layer.
It should be noted that, in the above example, the initial recess 104 is formed and an interconnect hole (not shown) is formed in the support layer 10 and the passivation layer 12, and the interconnect hole exposes the integrated circuit region. After the second material layer 102 is formed, a recess 103 is formed in the support layer 10.
In one example, the shape of the groove 103 in each of the above examples may include, but is not limited to, a rectangular bar shape, a cross shape, or a star shape (a hexagram or a pentagram, etc.), and the like.
In one example, in step S12, as shown in fig. 11 to 13, the bonding pad 14 may be formed using, but not limited to, a plating process or the like, and the bonding pad 14 may include, but is not limited to, an aluminum bonding pad.
In an alternative example, the bonding pad 14 is formed in the bonding pad region of the supporting layer 10, and the rewiring layer 15 is formed on the supporting layer 10, where the rewiring layer 15 is connected to the bonding pad 14 and the integrated circuit. In particular, the re-wiring layer 15 may be formed using, but not limited to, an electroplating process, and the re-wiring layer 15 may include, but not limited to, an aluminum re-wiring layer.
In one example, referring to fig. 11 to 13, before forming the pad 14 and the redistribution layer 15, a step of forming a seed layer 13 on the upper surface of the support layer 10 and in the interconnection hole is further included, and the pad 14 and the redistribution layer 15 are formed on the upper surface of the seed layer 13. Specifically, the seed layer 13 may be formed using, but not limited to, a sputtering or electroplating process, and the seed layer 13 may include, but is not limited to, a titanium layer or a titanium nitride layer, or the like.
The step S12 further includes the following steps:
S13, forming a protective layer 16 on the upper surface of the supporting layer 10, wherein the protective layer 16 covers the bonding pads of the rewiring layers 15 and 14;
S14, forming an opening 161 in the protection layer 16, wherein the opening 161 exposes the bonding pad 14, as shown in FIGS. 14 to 19;
and S15, providing a bonding wire 17, and connecting one end of the bonding wire 17 with the bonding pad 14, as shown in fig. 20 to 25. In one example, the protective layer 16 may be a single layer structure as shown in fig. 14 to 16, and in other examples, the protective layer 16 may be a stacked structure including a bottom protective layer 163 and a top protective layer 164 as shown in fig. 17 to 19. Specifically, the protective layer 16 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like. It should be noted that, under the same etching conditions, the bottom protective layer 163 has a higher etching selectivity than the top protective layer 164.
In an alternative embodiment, the protective layer 16 at the lower part of the opening 161 formed in the step S14 has a notch 162 therein, the notch 162 extends from the lower part of the opening 161 into the protective layer 16 as shown in fig. 14 to 19, and by forming the notch 162 in the protective layer 16 at the lower part of the opening 161, a buffer space can be formed at the lower part of the opening 161, the notch 162 can accommodate the bonding wire 15 to press the bonding pad 14 of the outer row, preventing the protective layer 16 from being lifted or cracked upwards, preventing the bonding pad 14 from overflowing, thereby ensuring the quality of the product.
When the protective layer 16 is of a single-layer structure, the protective layer 16 can be directly etched by a dry etching process to form an opening 161 with a notch 162 at the bottom, and when the protective layer 16 is of a laminated structure including a bottom protective layer 163 and a top protective layer 164, an initial opening can be formed in the top protective layer 161 by a dry etching process, and then the bottom protective layer 163 can be etched by a wet etching process to form the opening 161 with the notch 162 at the bottom.
In one example, wire bonds 17 may include, but are not limited to, copper wire, aluminum wire, or gold wire, among others.
In an alternative example, when bonding wire 17 is bonded to pad 14, bonding wire 17 reacts with pad 14 to form alloy layer 18 at the joint cross-section of the two, as shown in fig. 20-25.
In one example, the bottom of bond wire 17 is spaced from the bottom of groove 103. The bottom of the bonding wire 17 and the bottom of the groove 103 have a space, so that the bonding pad 14 is reserved between the bonding wire 17 and the bottom of the groove 103, and in operation, current can flow through the bonding pad 14 in the groove 103 in addition to the bonding pad 14 on both sides of the bonding wire 17, thereby increasing the current amount in operation.
In another embodiment, referring to fig. 20 to 25 in conjunction with fig. 2 to 19, the present invention further provides a semiconductor structure, which includes a support layer 10, the support layer 10 includes a pad region (not shown), a plurality of grooves 103 in the pad region of the support layer 10, and a bonding pad 14, wherein the bonding pad 14 is located on the support layer 10 and at least in the pad region, and the bonding pad 14 is partially embedded in the grooves 103.
In the above semiconductor structure, the supporting layer 10 having the plurality of grooves 103 in the pad region is formed under the bonding pad 14, i.e. the supporting layer 10 having the grooves 103 in the pad region is formed first, and then the bonding pad 14 is formed in the pad region of the supporting layer 10, and even if the bonding pad 14 is flat and most of the bonding pad 14 is displaced under the bonding pressure during the bonding process, the supporting layer 10 having the grooves 103 is formed under the bonding pad 14, and part of the area of the bottom of the bonding wire is trapped in the grooves 103, so that the contact surface between the bonding wire and the bonding pad 14 is uneven, the adhesion between the bonding wire and the bonding pad 14 is increased, and the risk of falling off of the bonding wire is reduced.
In an alternative example, the support layer 10 may have a single layer structure, and as shown in fig. 23, the depth of the groove 103 may be equal to or less than the thickness of the support layer 10, and the support layer 10 may include a dielectric layer or a polymer layer.
In another example, the support layer 10 may have a laminated structure, and the support layer 10 may include a first material layer 101 and a second material layer 102, where the second material layer 102 is located on an upper surface of the first material layer 101, and a plurality of grooves 103 are formed in the second material layer 102, and as shown in fig. 24, the depth of the grooves 103 may be less than or equal to the thickness of the second material layer 102.
In yet another example, the support layer 10 is a laminated structure, and the support layer 10 includes a first material layer 101, in which an initial groove is formed in the first material layer 101, and the depth of the initial groove may be less than or equal to the thickness of the first material layer 101, a second material layer 102, in which the second material layer 102 is located on the upper surface of the first material layer 101, on the side wall of the initial groove, and on the bottom of the initial groove, and the thickness of the second material layer 102 is less than the depth of the initial groove, so as to form a groove 103 in the support layer 10, as shown in fig. 25.
In one example, the first material layer 101 may be a dielectric layer and the second material layer 102 may be a polymer layer, and in another example, the first material layer 101 may be a polymer layer and the second material layer 102 may be a dielectric layer.
In each of the above examples, the dielectric layer may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like, and the polymer layer may include, but is not limited to, a polyimide layer or a polybenzoxazole layer.
In one example, the depth of the groove 103 may be smaller than the thickness of the support layer 10, and the depth of the groove 103 may be set according to practical needs, for example, the depth of the groove 103 may be 1/3, 2/3, or 3/4 of the thickness of the support layer 10, or the like, and of course, in other examples, the depth of the groove 103 may be equal to the thickness of the support layer 10, that is, the groove 103 penetrates the support layer 10 in the thickness direction.
In one example, the shape of the groove 103 in each of the above examples may include, but is not limited to, a rectangular bar shape, a cross shape, or a star shape (a hexagram or a pentagram, etc.), and the like.
In one example, the bond pad 14 may include, but is not limited to, an aluminum bond pad.
In an alternative embodiment, the semiconductor structure further comprises a substrate 11, an integrated circuit (not shown) is formed in the substrate 11, a passivation layer 12, a supporting layer 10, a rewiring layer 15, a seed layer 13, a protective layer 16, an opening 161 and a bonding wire 17, wherein the passivation layer 12 is located on the upper surface of the substrate 11, the supporting layer 10 is located on the upper surface of the passivation layer 12, the rewiring layer 15 is located on the supporting layer 10 and connected with the integrated circuit and the bonding pad 14, the seed layer 13 is located between the supporting layer 10 and the bonding pad 14, the rewiring layer 15 and between the supporting layer 10 and the integrated circuit, the protective layer 16 is located on the upper surface of the supporting layer 10 and covers the rewiring layer 15 and the bonding pad 14, the opening 161 is formed in the protective layer 16, the bonding wire 17 is located in the opening 161, and one end of the bonding wire 17 is connected with the bonding pad 14.
In one example, the base 11 may include, but is not limited to, a silicon substrate.
In one example, the passivation layer 12 covers the upper surface of the substrate 11. The passivation layer 12 may include a single layer structure or a stacked structure including a plurality of material layers. Passivation layer 12 may include, but is not limited to, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
In one example, the rewiring layer 15 may include, but is not limited to, an aluminum rewiring layer.
In one example, seed layer 13 may include, but is not limited to, a titanium layer or a titanium nitride layer, or the like.
In one example, wire bonds 17 may include, but are not limited to, copper wire, aluminum wire, or gold wire, among others.
In an alternative example, when bonding wires 17 are wired to pads 14, alloy layer 18 is formed at the bonding cross section of bonding wires 17 to pads 14, as shown in fig. 20 to 25.
In one example, the bottom of bond wire 17 is spaced from the bottom of groove 103. The bottom of the bonding wire 17 and the bottom of the groove 103 have a space, so that the bonding pad 14 is reserved between the bonding wire 17 and the bottom of the groove 103, and in operation, current can flow through the bonding pad 14 in the groove 103 in addition to the bonding pad 14 on both sides of the bonding wire 17, thereby increasing the current amount in operation.
In one example, the protective layer 16 may be a single layer structure as shown in fig. 20 to 22, and in other examples, the protective layer 16 may be a stacked structure including a bottom protective layer 163 and a top protective layer 164 as shown in fig. 23 to 25. Specifically, the protective layer 16 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like. It should be noted that, under the same etching conditions, the bottom protective layer 163 has a higher etching selectivity than the top protective layer 164. It should be further noted that, when the protection layer 16 is a stacked structure including the bottom protection layer 163 and the top protection layer 164, the notch 162 is formed in the bottom protection layer 163.
In another example, the protective layer 16 at the lower part of the opening 161 is provided with a notch 162, the notch 162 extends from the lower part of the opening 161 into the protective layer 16 as shown in fig. 14 to 19, and by forming the notch 162 in the protective layer 16 at the lower part of the opening 161, a buffer space can be formed at the lower part of the opening 161, the notch 162 can accommodate the bonding wires 15 to press the bonding pads 14 of the outer row, the protective layer 16 is prevented from being lifted upwards or split, and the bonding pads 14 are prevented from overflowing, thereby ensuring the quality of products.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims (12)

1.A semiconductor structure, characterized in that,
Comprising the following steps:
The support layer comprises a pad area, wherein the support layer in the pad area is provided with a plurality of grooves;
A bonding pad positioned on the supporting layer and at least positioned in the bonding pad area, wherein the bonding pad is partially embedded in the groove;
the semiconductor structure further comprises a substrate, wherein the substrate is internally provided with an integrated circuit structure;
The support layer is positioned on the upper surface of the passivation layer;
the rewiring layer is positioned on the supporting layer and connected with the integrated circuit and the welding pad;
a seed layer located between the support layer and the bond pad, between the redistribution layer and the support layer, and between the redistribution layer and the integrated circuit structure;
The protective layer is positioned on the upper surface of the supporting layer and covers the rewiring layer and the welding pad, and an opening is formed in the protective layer and exposes the welding pad;
One end of the bonding wire is positioned in the opening and is connected with the bonding pad;
The protective layer at the lower part of the opening is provided with a notch so that the width of the lower part of the opening is larger than that of the upper part of the opening.
2. The semiconductor structure of claim 1, wherein,
The supporting layer is of a single-layer structure and comprises a dielectric layer or a polymer layer, and the depth of the groove is smaller than or equal to the thickness of the supporting layer.
3. The semiconductor structure of claim 1, wherein,
The supporting layer is a laminated structure, and the supporting layer comprises:
the first material layer is internally provided with an initial groove, and the depth of the initial groove is smaller than or equal to the thickness of the first material layer;
the second material layer is positioned on the upper surface of the first material layer, the side wall of the initial groove and the bottom of the initial groove, and the thickness of the second material layer is smaller than the depth of the initial groove.
4. The semiconductor structure of claim 1, wherein,
The supporting layer is a laminated structure, and the supporting layer comprises:
a first material layer;
The second material layer is positioned on the upper surface of the first material layer, a plurality of grooves are formed in the second material layer, and the depth of each groove is smaller than or equal to the thickness of the second material layer.
5. The semiconductor structure of claim 3 or 4, wherein,
The first material layer is a dielectric layer and the second material layer is a polymer layer, or the first material layer is a polymer layer and the second material layer is a dielectric layer.
6. The semiconductor structure of claim 1, wherein,
And the bottom of the bonding wire and the bottom of the groove are provided with a distance.
7. A method for preparing a semiconductor structure is characterized in that,
The method comprises the following steps:
forming a supporting layer, wherein the supporting layer comprises a bonding pad area, and a plurality of grooves are formed in the bonding pad area of the supporting layer;
forming a bonding pad at least in a bonding pad area of the supporting layer, wherein the bonding pad is partially embedded in the groove;
the support layer is formed by the following steps:
Providing a substrate, wherein an integrated circuit is formed in the substrate;
forming a passivation layer on the upper surface of the substrate, wherein the support layer is formed on the upper surface of the passivation layer;
Forming an interconnection hole in the supporting layer and the passivation layer before forming the welding pad in the groove, wherein the interconnection hole exposes the integrated circuit region;
forming a rewiring layer on the supporting layer while forming the welding pad in the welding pad area of the supporting layer, wherein the rewiring layer is connected with the welding pad and the integrated circuit;
The method further comprises the step of forming a seed layer on the upper surface of the supporting layer and in the interconnection hole before forming the welding pad and the rerouting layer, wherein the welding pad and the rerouting layer are formed on the upper surface of the seed layer;
The method further comprises the following steps after forming the bonding pad in the bonding pad area of the supporting layer:
Forming a protective layer on the upper surface of the supporting layer, wherein the protective layer covers the rewiring layer and the welding pad;
And forming an opening in the protection layer, wherein the opening exposes the welding pad, and a notch is arranged in the protection layer at the lower part of the opening, so that the width of the lower part of the opening is larger than that of the upper part of the opening.
8. The method of manufacturing a semiconductor structure as claimed in claim 7, wherein,
The forming of the support layer comprises the following steps:
Forming a dielectric layer;
and etching the dielectric layer to form the groove in the dielectric layer, wherein the depth of the groove is smaller than or equal to the thickness of the dielectric layer.
9. The method of manufacturing a semiconductor structure as claimed in claim 7, wherein,
The forming of the support layer comprises the following steps:
forming a polymer layer;
and exposing and developing the polymer layer to form the grooves in the polymer layer, wherein the depth of the grooves is smaller than or equal to the thickness of the polymer layer.
10. The method of manufacturing a semiconductor structure as claimed in claim 7, wherein,
The forming of the support layer comprises the following steps:
Forming a first material layer;
Forming a second material layer on the upper surface of the first material layer;
And forming the groove in the second material layer, wherein the depth of the groove is smaller than or equal to the thickness of the second material layer.
11. The method of manufacturing a semiconductor structure as claimed in claim 7, wherein,
The forming of the support layer comprises the following steps:
Forming a first material layer;
forming an initial groove in the first material layer, wherein the depth of the initial groove is smaller than or equal to the thickness of the first material layer;
and forming a second material layer on the upper surface of the first material layer, the side wall and the bottom of the initial groove.
12. The method for fabricating a semiconductor structure according to claim 10 or 11, wherein,
The first material layer is a dielectric layer and the second material layer is a polymer layer, or the first material layer is a polymer layer and the second material layer is a dielectric layer.
CN201911213085.0A 2019-12-02 2019-12-02 Semiconductor structure and method for manufacturing the same Active CN112992830B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911213085.0A CN112992830B (en) 2019-12-02 2019-12-02 Semiconductor structure and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911213085.0A CN112992830B (en) 2019-12-02 2019-12-02 Semiconductor structure and method for manufacturing the same

Publications (2)

Publication Number Publication Date
CN112992830A CN112992830A (en) 2021-06-18
CN112992830B true CN112992830B (en) 2025-05-16

Family

ID=76331013

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911213085.0A Active CN112992830B (en) 2019-12-02 2019-12-02 Semiconductor structure and method for manufacturing the same

Country Status (1)

Country Link
CN (1) CN112992830B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116453961A (en) * 2022-01-06 2023-07-18 长鑫存储技术有限公司 Semiconductor structure and preparation method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543921A (en) * 2010-12-23 2012-07-04 中芯国际集成电路制造(上海)有限公司 Welding pad structure and manufacturing method thereof
CN210575928U (en) * 2019-12-02 2020-05-19 长鑫存储技术有限公司 Semiconductor structure

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW453137B (en) * 1997-08-25 2001-09-01 Showa Denko Kk Electrode structure of silicon semiconductor device and the manufacturing method of silicon device using it
US9524945B2 (en) * 2010-05-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with L-shaped non-metal sidewall protection structure
US9818711B2 (en) * 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543921A (en) * 2010-12-23 2012-07-04 中芯国际集成电路制造(上海)有限公司 Welding pad structure and manufacturing method thereof
CN210575928U (en) * 2019-12-02 2020-05-19 长鑫存储技术有限公司 Semiconductor structure

Also Published As

Publication number Publication date
CN112992830A (en) 2021-06-18

Similar Documents

Publication Publication Date Title
US5707894A (en) Bonding pad structure and method thereof
US9362329B2 (en) Pad structure exposed in an opening through multiple dielectric layers in BSI image sensor chips
KR101952988B1 (en) Semiconductor device
US9449935B1 (en) Wafer level package and fabrication method thereof
JP6317475B2 (en) Dicing method for wafer level packaging and semiconductor chip having dicing structure adapted for wafer level packaging
US10573587B2 (en) Package structure and manufacturing method thereof
US20110285008A1 (en) Semiconductor apparatus and semiconductor apparatus unit
US11107758B2 (en) Fan-out package structure and method
KR20070096016A (en) Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
US9184207B2 (en) Pad structures formed in double openings in dielectric layers
KR20190021127A (en) A semiconductor device
JP5474534B2 (en) Passivation and contact surrounded by polyimide and method of manufacturing the same
TW201532223A (en) Chip package and method of manufacturing same
US8324731B2 (en) Integrated circuit device
CN112992830B (en) Semiconductor structure and method for manufacturing the same
JP6137454B2 (en) Semiconductor device and manufacturing method of semiconductor device
US7943529B2 (en) Passivation structure and fabricating method thereof
JP4506767B2 (en) Manufacturing method of semiconductor device
CN210575928U (en) Semiconductor structure
US20090020878A1 (en) Semiconductor packages and methods of fabricating the same
CN210575838U (en) Semiconductor structure
CN210575839U (en) Semiconductor structure
JP3603673B2 (en) Manufacturing method of bonding pad structure
CN112786466A (en) Semiconductor structure and preparation method thereof
KR101897653B1 (en) Methods of fabricating compliant bump

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant