CN102820256A - Method for preparing inter-metal dielectric layer - Google Patents
Method for preparing inter-metal dielectric layer Download PDFInfo
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- CN102820256A CN102820256A CN2011101517859A CN201110151785A CN102820256A CN 102820256 A CN102820256 A CN 102820256A CN 2011101517859 A CN2011101517859 A CN 2011101517859A CN 201110151785 A CN201110151785 A CN 201110151785A CN 102820256 A CN102820256 A CN 102820256A
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Abstract
The invention provides a method for preparing an inter-metal dielectric (IMD) layer, and belongs to the technical field of back-end preparation processes of semiconductor chips. The method mainly includes steps of (1) providing a back-end structure of a semiconductor with designed and formed interconnected wires; (2) growing a fluorine-doped silicate glass layer by chemical vapor deposition; and (3) growing an undoped silicate glass layer by chemical vapor deposition. The method has the advantages that cavities are prevented from being formed on the IMD layer, and cost is low.
Description
Technical field
The invention belongs to the fabricating technology field, rear end of semiconductor chip, relate to a kind of inter-metal medium (Inter-Metal Dielectric, IMD) preparation method of layer who avoids producing cavity (Void).
Background technology
Along with the continuous development of integrated circuit fabricating technology, the client improves constantly the requirement of the integrated level of chip, and the size of IC chip is also constantly reducing according to Moore's Law.Wherein, in the back end structure of IC chip, the live width of interconnection line (for example aluminum interconnecting) also constantly reduces, and simultaneously, the distance between the interconnection line also constantly reduces.Normally, the IMD layer in the back end structure of IC chip is to be used for filling gap between the interconnection line.Therefore, after the patterned etching of interconnection line forms,, when growth IMD layer, between interconnection line, form the cavity easily along with the spacing between the interconnection line reduces.
Fig. 1 is shown in the structural representation of growth formation IMD layer between the aluminum interconnecting.In Fig. 1; Partly show the back end structure of semiconductor chip, wherein, 11 is inter-level dielectric (Inter-Layer Dielectric; ILD) layer; In ILD layer 11, can form the through hole (for example tungsten plug) that connects the different layers aluminum interconnecting, aluminum interconnecting 121 and 122 compositions are formed on the ILD layer 11, and aluminum interconnecting 121 can be connected through the interconnection line with its last layer or following one deck such as through hole or embolism.Therefore can form the space that is similar to groove shape between the adjacent aluminum interconnecting 121 and 122.In the process of IMD film growth, as illustrating among Fig. 1 whether form the cavity in the IMD layer and mainly receive following parameter influence:
Depth-to-width ratio: the height h of interconnection line and the ratio (being h/w) between the spacing w between the adjacent interconnection line;
The sidewall step covers: the ratio (being b/a) on the interconnection line wall between thin film thickness b and the interconnection line top thin film thickness a;
Bottom stage covers: the ratio (being d/a) between the thickness d of the film between the interconnection line and the interconnection line top thin film thickness a;
Conformability: the ratio (being b/c) between the thick film thickness c on thin film thickness b and the interconnection line wall on the interconnection line wall;
Overhang: the ratio (i.e. (c-b)/b) on interconnection line wall upper film thickness difference (c-b) and the interconnection line wall between the thin film thickness b.
Wherein, Depth-to-width ratio is bigger, the sidewall step covers poor more (being that b/a is more little), bottom stage covers poor more (being that d/a is more little), conformability poor more (being that b/c is more little), when overhanging bigger (promptly (c-b)/b is big more), forms the cavity between the easier adjacent aluminum interconnecting in IMD.
Shown in Figure 2 is the structural representation that in the IMD layer, forms the cavity in the prior art.As shown in Figure 2, constantly depositing in the process of IMD film, the part 123 of overhanging shown in Figure 1 can constantly become big and closure along with growth for Thin Film, thereby forms cavity 90, and this cavity can have a strong impact on chip reliability.
Along with the spacing between the interconnection line reduces, in the IMD layer, produce the cavity more and more easily.In view of this, be necessary to propose a kind of preparation method of novel IMD layer.
Summary of the invention
The technical problem that the present invention will solve is, avoids forming the cavity in the IMD layer in the back end structure of IC chip.
For solving above technical problem, the present invention provides a kind of preparation method of intermetallic dielectric layer, and it may further comprise the steps:
(1) end structure behind the semiconductor chip that composition forms interconnection line is provided;
(2) chemical vapor deposition growth is mixed the silica glass layer of fluorine; And
(3) the unadulterated silica glass layer of chemical vapor deposition growth.
Preferably, the said silica glass layer of mixing fluorine forms through the high density plasma CVD growth.
In one embodiment, in step (2) before, also comprise step:
(1a) deposition interconnection line protective layer.
Preferably, said interconnection line protective layer is the silicon rich oxide thin layer.
Preferably, said unadulterated silica glass layer forms through the high density plasma CVD growth.
Preferably, the thickness range of said silicon rich oxide thin layer is the 200-1000 dust; The said thickness range of mixing the silica glass layer of fluorine is the 8000-15000 dust; The thickness range of said unadulterated silica glass layer is the 4000-6000 dust.
According to the preparation method of intermetallic dielectric layer provided by the invention, wherein, the scope of the depth-to-width ratio of the groove that forms between the adjacent said interconnection line can be 2-2.9.
Particularly, said interconnection line can be aluminum interconnecting.
Particularly, the preparation method of intermetallic dielectric layer also comprises step: (4) chemico-mechanical polishing forms said intermetallic dielectric layer.
Technique effect of the present invention is; Intermetallic dielectric layer is through the method formation of growth fsg layer, twice deposition of regrowth USG layer earlier; Utilize the filling capacity of fsg layer good, protected the problem that the good advantage of row property avoids forming hole; And the USG layer can stop that the fluorine in the fsg layer spreads in its adjacent layer, does not need other deposition to be used to stop the TEOS layer of the fluorine diffusion of fsg layer, thereby can reduce the preparation cost of IMD layer.
Description of drawings
From the following detailed description that combines accompanying drawing, will make above and other objects of the present invention and advantage clear more fully, wherein, same or analogous key element adopts identical label to represent.
Fig. 1 is the structural representation that growth forms the IMD layer between aluminum interconnecting.
Fig. 2 is the structural representation that in the IMD layer, forms the cavity in the prior art.
Fig. 3 is according to IMD preparation method embodiment schematic flow sheet provided by the invention.
Fig. 4 to Fig. 8 schematically illustrates the structural change sketch map for preparing the IMD layer according to method flow shown in Figure 3.
Embodiment
What introduce below is some among a plurality of possibility embodiment of the present invention, aims to provide basic understanding of the present invention.Be not intended to confirm key of the present invention or conclusive key element or limit claimed scope.Understand easily, according to technical scheme of the present invention, do not changing under the connotation of the present invention, but one of ordinary skill in the art can propose other implementation of mutual alternative.Therefore, following embodiment and accompanying drawing only are the exemplary illustrations to technical scheme of the present invention, and should not be regarded as qualification or the restriction to technical scheme of the present invention that all perhaps be regarded as of the present invention.
In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and zone, and, mellow and fullly wait signal in the accompanying drawings of shape facility because etching causes.
In the present invention, the IMD layer mainly the silex glass through mixing fluorine (Fluorinated Silicate Glass, FSG) (Undoped Silicate Glass USG) forms with unadulterated silex glass.
Shown in Figure 3 is according to IMD preparation method embodiment schematic flow sheet provided by the invention.In this embodiment, the IMD layer that forms between the aluminum interconnecting with preparation is that example describes.Wherein, Fig. 4 to Fig. 8 schematically illustrates the structural change sketch map for preparing the IMD layer according to method flow shown in Figure 3.Specify this example I MD layer preparation method below in conjunction with Fig. 3 to Fig. 8.
At first, step S31 provides end structure behind the semiconductor chip that composition forms aluminum interconnecting.
Consult Fig. 4, aluminum interconnecting 121 and 122 composition that is etched is formed on the ILD layer 11, and aluminum interconnecting residing number of metal in the end structure behind semiconductor chip is not restrictive.The IMD layer will be formed between the aluminum interconnecting, therefore, need fill the groove between the two adjacent aluminum interconnectings 121 and 122.The depth-to-width ratio of the groove between the aluminum interconnecting 121 and 122 is big more, forms the cavity more easily therein.In this embodiment, therefore the depth-to-width ratio of the groove between the aluminum interconnecting 121 and 122, need form IMD through following procedure and avoid in the groove scope, forming the cavity in the scope of 2-2.9.
Need to prove; Procedure shown in Figure 3 is not only applicable to the preparation of the IMD layer of aluminium interconnection back end structure; The situation of any interconnection line elder generation's composition formation interconnection line and then deposition IMD layer; All can use method shown in Figure 3 and prepare the IMD layer, thereby avoid the zone between the adjacent interconnection line to form the cavity.
Further, step S32, deposition silicon rich oxide (Silicon Rich Oxide, SRO) thin layer.
Consult Fig. 5; At first deposit the surface of one deck SRO thin layer 25 aluminium coating interconnection lines 121 and 122; SRO thin layer 25 can be used as HDPCVD (High-Density Plasma Chemical Vapor Deposition thereafter; High density plasma CVD) protective layer of growth course, thus can prevent in the HDPCVD growth course that plasma from causing damage to metal level (for example aluminum interconnecting 121 and 122).SRO thin layer 25 is because as the interconnection line protective layer, therefore, its thickness can be provided with thinner relatively, and for example, its thickness range can be 200 to 1000 dusts.Need to prove that the concrete film type that is used as the interconnection line protective layer is not limited by the embodiment of the invention, it can also be the film of other the concrete basic identical performance outside the SRO.
Further, step S33, the HDPCVD fsg layer of growing.
Consult Fig. 6, deposition fsg layer 26 on SRO thin layer 25, in this embodiment; Preferably adopt the HDPCVD growth pattern to deposit fsg layer; This is because HDPCVD is the mode of etching limit, limit growth, and filling capacity is stronger, in the fsg layer of trench region, is difficult for forming the cavity.The concrete technological parameter of HDPCVD is not restrictive, and those skilled in the art can be provided with according to different situations.The thickness of fsg layer 26 can be provided with in 8000 dust to 15000 dust scopes.
Need to prove; FSG and USD are the dielectric layer that often uses among the IMD, in this invention, utilize the filling capacity of FSG material when growth to be better than the filling capacity of USG material; Therefore; In the forming process of fsg layer 26, the conformability of fsg layer 26, overhang, parameter such as sidewall step covering is better relatively, is not easy to form the cavity.When using the HDPCVD deposition, overhanging of fsg layer 26 is littler relatively, be not easy to form the cavity, and the conformal spreadability is better relatively.But any fsg layer 26 that should be appreciated that of art technology can also take other thin film deposition mode to grow, for example PECVD except that employing HDPVD mode deposits.
Further, step S34, CVD (chemical vapour deposition (CVD)) growth USG layer.
Consult Fig. 7, deposition USG layer 27 on fsg layer 26, USG layer 27 are covered in top layer, therefore, can mainly pass through the groove between USG layer 27, the fsg layer 26 filling aluminum interconnection lines 121 and 122.Particularly, the growing method of USG layer can adopt CVD methods such as HDPCVD and PECVD, preferably, adopts the mode of HDPCVD to deposit, and this more helps reducing the possibility that forms the cavity.In this embodiment, the thickness range of USG layer 27 can be the 4000-6000 dust.
Need to prove that in the present invention, elder generation deposits formation fsg layer 26, the mode of deposition formation USG layer 27 forms the IMD layer again, can prevent that not only formation is empty in IMD, and can utilize USG layer 27 to stop that the fluorine in the fsg layer 26 spreads to its adjacent layer.Thereby, in this invention, can save the conventional step that on fsg layer, deposits one deck TEOS (Tetraethylorthosilicate, tetraethyl orthosilicate), reduce the preparation cost of IMD layer.
Further, step S35, CMP (Chemical Mechanical Polishing, chemico-mechanical polishing) forms the IMD layer.
Consult Fig. 8, remove the dielectric layer (comprising part USG layer and part fsg layer) on the aluminum interconnecting, realize planarization, thereby formed IMD layer as shown in Figure 8 through CMP.Normally, on this IMD layer, can form the ILD layer by the continued growth dielectric layer.
So far, the preparation process of IMD layer finishes basically.
Above example has mainly been explained the preparation method of IMD layer of the present invention.Although only some of them execution mode of the present invention is described, those of ordinary skills should understand, and the present invention can be in not departing from its purport and scope implements with many other forms.Therefore, example of being showed and execution mode are regarded as schematic and nonrestrictive, are not breaking away under the situation of liking defined spirit of the present invention of each claim and scope enclosed, and the present invention possibly contained various modifications and replacement.
Claims (9)
1. the preparation method of an intermetallic dielectric layer is characterized in that, may further comprise the steps:
(1) end structure behind the semiconductor chip that composition forms interconnection line is provided;
(2) chemical vapor deposition growth is mixed the silica glass layer of fluorine; And
(3) the unadulterated silica glass layer of chemical vapor deposition growth.
2. preparation method as claimed in claim 1 is characterized in that, the said silica glass layer of mixing fluorine forms through the high density plasma CVD growth.
3. preparation method as claimed in claim 2 is characterized in that, in step (2) before, also comprises step:
(1a) deposition interconnection line protective layer.
4. preparation method as claimed in claim 3 is characterized in that, said interconnection line protective layer is the silicon rich oxide thin layer.
5. according to claim 1 or claim 2 preparation method is characterized in that, said unadulterated silica glass layer forms through the high density plasma CVD growth.
6. preparation method as claimed in claim 4 is characterized in that, the thickness range of said silicon rich oxide thin layer is the 200-1000 dust; The said thickness range of mixing the silica glass layer of fluorine is the 8000-15000 dust; The thickness range of said unadulterated silica glass layer is the 4000-6000 dust.
7. preparation method as claimed in claim 1 is characterized in that, the scope of the depth-to-width ratio of the groove that forms between the adjacent said interconnection line is 2-2.9.
8. like claim 1 or 7 described preparation methods, it is characterized in that said interconnection line is an aluminum interconnecting.
9. preparation method as claimed in claim 1 is characterized in that, also comprises step:
(4) chemico-mechanical polishing forms said intermetallic dielectric layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2015165411A1 (en) * | 2014-04-29 | 2015-11-05 | 无锡华润上华半导体有限公司 | Silicon-on-insulator device and intermetallic dielectric layer structure thereof and manufacturing method |
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| US20020001876A1 (en) * | 1999-01-26 | 2002-01-03 | Mahjoub Ali Abdelgadir | Method of making an integrated circuit device having a planar interlevel dielectric layer |
| US20040213921A1 (en) * | 2003-04-23 | 2004-10-28 | Taiwan Semiconductor Manufacturing Co. | Solution for FSG induced metal corrosion & metal peeling defects with extra bias liner and smooth RF bias ramp up |
| US20060134900A1 (en) * | 2004-12-22 | 2006-06-22 | Dongbuanam Semiconductor Inc. | Method of forming a metal interconnection line in a semiconductor device using an FSG layer |
| CN101740473A (en) * | 2008-11-18 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Interlayer dielectric layer, interconnection structure and manufacturing method thereof |
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| US5876798A (en) * | 1997-12-29 | 1999-03-02 | Chartered Semiconductor Manufacturing, Ltd. | Method of fluorinated silicon oxide film deposition |
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| US20040213921A1 (en) * | 2003-04-23 | 2004-10-28 | Taiwan Semiconductor Manufacturing Co. | Solution for FSG induced metal corrosion & metal peeling defects with extra bias liner and smooth RF bias ramp up |
| US20060134900A1 (en) * | 2004-12-22 | 2006-06-22 | Dongbuanam Semiconductor Inc. | Method of forming a metal interconnection line in a semiconductor device using an FSG layer |
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| WO2015165411A1 (en) * | 2014-04-29 | 2015-11-05 | 无锡华润上华半导体有限公司 | Silicon-on-insulator device and intermetallic dielectric layer structure thereof and manufacturing method |
| CN105097776A (en) * | 2014-04-29 | 2015-11-25 | 无锡华润上华半导体有限公司 | Silicon-on-insulator device and intermetallic dielectric layer structure thereof and manufacturing method |
| US20170011957A1 (en) * | 2014-04-29 | 2017-01-12 | Csmc Technologies Fab1 Co., Ltd. | Silicon-on-insulator device and intermetallic dielectric layer structure thereof and manufacturing method |
| CN105097776B (en) * | 2014-04-29 | 2018-03-16 | 无锡华润上华科技有限公司 | SOI device and its inter-metal medium Rotating fields and manufacture method |
| US10276430B2 (en) * | 2014-04-29 | 2019-04-30 | Csmc Technologies Fab1 Co., Ltd. | Silicon-on-insulator device and intermetallic dielectric layer structure thereof and manufacturing method |
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