CN102593085B - Chip packaging structure and chip packaging process - Google Patents

Abstract

The invention relates to a chip packaging structure which comprises a silicon substrate, a sensing element, a metal circuit layer, a first insulating layer and a conductive metal layer. The silicon substrate is provided with a first surface and a second surface which are opposite. The sensing element is arranged on the first surface. The metal circuit layer is also arranged on the first surface and is electrically connected with the sensing element. The first insulating layer covers the second surface and is provided with a first through hole to expose part of the second surface. The conductive metal layer is disposed on the first insulating layer and includes a plurality of first leads and a second lead. The first lead is electrically connected to the metal circuit layer. The second leads are filled in the first through holes to be electrically connected with the silicon substrate and at least one of the first leads. In addition, the invention also provides a chip packaging process. The chip packaging structure and the chip packaging process can realize the electrical connection between the silicon substrate and the external element.

Description

Chip packaging structure and chip packaging process

technical field

The invention relates to a chip package, in particular to a chip package structure and a chip package process.

Background technique

With the rapid development of semiconductor technology, the performance of integrated circuits (ICs) is continuously enhanced, and the structure of integrated circuits is becoming more and more complex, which leads to the production of integrated circuits, especially the packaging of integrated circuits, which needs to be continuously developed and updated.

Chip Scale Package (CSP) is a high-density packaging technology that is widely used at present. FIG. 1 is a schematic cross-sectional view of a chip package structure of an existing optical integrated circuit. Please refer to FIG. 1 , the silicon substrate 110 of the conventional chip packaging structure 100 has a first surface 101 and a second surface 102 opposite to each other. The circuit layer 120 and the optical sensing chip element 130 electrically connected to the circuit layer 120 are disposed on the first surface 101 of the silicon substrate 110 and covered by the transparent protection layer 140 . The circuit layer 120 is electrically connected to external components through the guide pins 150 and the solder balls 160 . The second surface 102 of the silicon substrate 110 is usually covered by the encapsulant 170 .

However, in the existing chip packaging structure 100, the silicon substrate 110 is only used to configure the circuit layer 120 and the optical sensing chip element 130, etc., and cannot be electrically connected with external components (such as a printed circuit board). 110 cannot be grounded.

Contents of the invention

The invention provides a chip packaging structure, which can realize the electrical connection between the silicon substrate and the external components.

The present invention further provides a chip packaging process, which is used to manufacture a chip packaging structure, so as to realize the electrical connection between the silicon substrate of the chip packaging structure and external components.

In order to achieve at least one of the above advantages, the present invention provides a chip packaging structure, which includes a silicon substrate, a sensing element, a metal circuit layer, a first insulating layer, and a conductive metal layer. The silicon substrate has a first surface and a second surface opposite to the first surface. The sensing element is disposed on the first surface of the silicon substrate. The metal circuit layer is also disposed on the first surface of the silicon substrate and electrically connected to the sensing element. The first insulating layer covers the second surface of the silicon substrate and has a first through hole to expose part of the second surface of the silicon substrate. The conductive metal layer is disposed on the first insulating layer and includes a plurality of first leads and a second lead. The first lead is electrically connected to the metal circuit layer, and the second lead is filled in the first through hole to be electrically connected to the silicon substrate and at least one of the first lead.

In an embodiment of the present invention, the above-mentioned chip packaging structure further includes a protection layer to cover the metal circuit layer and the sensing element.

In an embodiment of the present invention, the above protective layer is made of epoxy resin.

In an embodiment of the present invention, the above-mentioned chip packaging structure further includes a protection substrate disposed on the protection layer.

In an embodiment of the present invention, the above-mentioned protective substrate is a transparent substrate.

In an embodiment of the present invention, the above-mentioned first lead electrically connected to the second lead is one of a ground lead and a power lead.

In an embodiment of the present invention, the above-mentioned chip packaging structure further includes a second insulating layer and a plurality of solder balls. Wherein, the second insulating layer covers the first lead pin and the second lead pin, and has a plurality of second through holes to expose parts of each first lead pin. A plurality of solder balls are correspondingly disposed in the second through holes to be electrically connected to the first pins.

In an embodiment of the present invention, the above-mentioned silicon substrate is provided with a plurality of through silicon vias (Through Silicon Via, TSV), so that the first pins are electrically connected to the metal circuit layer through the through silicon vias.

In an embodiment of the present invention, the above-mentioned conductive metal layer is composed of a plurality of sub-metal layers, and these sub-metal layers include stacked first sub-metal layers and second sub-metal layers. The first sub-metal layer is different from the second sub-metal layer, wherein the first sub-metal layer is located between the second sub-metal layer and the first insulating layer, and is used for being adhered to the second sub-metal layer and the first insulating layer respectively.

In order to achieve at least one of the above advantages, the present invention further provides a chip packaging process, which includes the following steps. First, a silicon wafer is provided, and the silicon wafer has a first surface and a second surface opposite to the first surface. The first surface is provided with a metal circuit layer and a plurality of sensing elements electrically connected to the metal circuit layer. Then, a plurality of cutting lines (Notches) are formed in the silicon wafer to separate a plurality of chip units and expose the metal circuit layer, wherein each chip unit includes a sensing element. Afterwards, a first insulating layer is formed on the second surface of the silicon wafer and filled into the dicing lines. Next, a plurality of openings respectively located in the dicing lines are formed in the first insulating layer, and a first through hole is formed in the first insulating layer of each chip unit to expose part of the second surface of the silicon wafer. Next, a conductive metal layer is formed on the first insulating layer. The conductive metal layer includes a plurality of first leads and a plurality of second leads, these first leads are electrically connected to the metal circuit layer, and these second leads are respectively filled in the first through holes for electrical connection on the silicon wafer, and electrically connected to at least one of the first leads. Afterwards, the silicon wafer is diced along these dicing lines to separate the individual chip units.

In an embodiment of the present invention, the above-mentioned chip packaging process further includes disposing a protective layer on the silicon wafer before forming the dicing lines to cover the metal circuit layer and the sensing element.

In an embodiment of the present invention, the above-mentioned chip packaging process further includes disposing a protective substrate on the protective layer.

In an embodiment of the present invention, the above-mentioned protective substrate is a transparent substrate.

In an embodiment of the present invention, the above-mentioned chip packaging process further includes performing a wafer thinning process after the protective substrate is provided. In the wafer thinning process, for example, the second surface of the silicon wafer is firstly ground to form a ground surface, and then the ground surface is planarized.

In an embodiment of the present invention, the above-mentioned method for forming a dicing line includes performing a photolithographic etching process.

In an embodiment of the present invention, the above-mentioned chip packaging process exposes the metal wiring layer when forming the opening, and fills the opening with the conductive metal layer when forming the conductive metal layer, so that the first conductive pin is electrically conductive. Connect to the metal wiring layer.

In an embodiment of the present invention, the above-mentioned conductive metal layer is composed of a plurality of sub-metal layers. The method of forming the conductive metal layer includes the following steps. Firstly, a first sub-metal layer is formed to cover the first insulating layer and fill in the opening and the first through hole. Then, the first sub-metal layer is etched to form a first lead and a second lead. Next, a second sub-metal layer is formed and stacked on the first lead and the second lead.

In an embodiment of the present invention, the above-mentioned conductive metal layer is composed of a plurality of sub-metal layers. The method of forming the conductive metal layer includes the following steps. Firstly, a first sub-metal layer is formed to cover the first insulating layer and fill in the opening and the first through hole. Then, a second sub-metal layer is formed to cover the first sub-metal layer. Next, the first sub-metal layer and the second sub-metal layer are etched to form a first lead and a second lead.

In an embodiment of the present invention, the material of the first sub-metal layer includes aluminum or copper, and the material of the second sub-metal layer includes nickel or gold.

In an embodiment of the present invention, the above-mentioned chip packaging process further includes the following steps. A second insulating layer is formed on the first insulating layer to cover the first lead and the second lead. A plurality of second through holes are formed in the second insulating layer to expose a portion of each first lead. A plurality of solder balls are correspondingly arranged in the second through holes, and are respectively electrically connected to the first pins.

In an embodiment of the present invention, the above-mentioned chip packaging process further includes forming a plurality of TSVs in the silicon wafer, so that the first leads are electrically connected to the metal circuit layer through the TSVs.

It can be seen from the above that in the chip packaging structure and the chip packaging process of the embodiment of the present invention, the silicon substrate can be connected with external components (such as printed circuit boards) through the second pins arranged in the first through holes of the first insulating layer. ) direct electrical connection. Therefore, the silicon substrate can be directly grounded, which is beneficial for signal testing of the silicon substrate and for maintaining the lowest potential of the silicon substrate.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a chip package structure of an existing optical integrated circuit.

FIG. 2 is a schematic cross-sectional view of a chip package structure according to an embodiment of the present invention.

FIG. 3 is a schematic top view of a first lead and a second lead of a chip package structure according to an embodiment of the present invention.

4A to 4M are schematic flowcharts of a chip packaging process according to an embodiment of the present invention.

[Description of main component symbols]

30: Patterned photoresist layer

100: Existing chip package structure

110: silicon substrate

101: First Surface

102: second surface

120: line layer

130: Optical sensing chip components

140: transparent protective layer

150: guide foot

160: solder ball

170: encapsulation colloid

200: chip package structure

210: Silicon substrate

210’, 210”: silicon wafer

212, 212': first surface

214, 214', 214": second surface

216: Cutting Road

218: chip unit

220: sensing element

230, 230': metal circuit layer

240, 240': first insulating layer

241: opening

242: First through hole

250, 250': conductive metal layer

252, 252': the first guide pin

253, 253': the first sub-metal layer

254, 254': the second guide pin

255, 255': the second sub-metal layer

260, 260': protective layer

270, 270': Protective substrate

280, 280': second insulating layer

282: Second through hole

290: solder ball

Detailed ways

In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the specific implementation methods, methods, and steps of the chip packaging structure and chip packaging process proposed according to the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. , structure, feature and effect, detailed description is as follows.

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the drawings. Through the description of the specific implementation, one can have a deeper and more specific understanding of the technical means and effects of the present invention to achieve the intended purpose. However, the attached drawings are only for reference and description, and are not used to limit the present invention. .

FIG. 2 is a schematic cross-sectional view of a chip package structure according to an embodiment of the present invention, and FIG. 3 is a schematic top view of the first lead and the second lead of the chip package structure according to an embodiment of the present invention. Please refer to FIG. 2 first. The chip packaging structure 200 of this embodiment includes a silicon substrate 210 , a sensing element 220 , a metal wiring layer 230 , a first insulating layer 240 and a conductive metal layer 250 . The silicon substrate 210 has a first surface 212 and a second surface 214 opposite to the first surface 212 . The sensing element 220 and the metal wiring layer 230 are disposed on the first surface 212 of the silicon substrate 210 . The sensing element 220 is, for example, an optical sensing element, but is not limited thereto. The metal circuit layer 230 is electrically connected to the sensing element 220 . The first insulating layer 240 covers the second surface 214 of the silicon substrate 210 and has a first through hole 242 to expose part of the second surface 214 of the silicon substrate 210 . The first insulating layer 240 is, for example, a solder mask, but not limited thereto.

Please refer to FIG. 2 and FIG. 3 , the conductive metal layer 250 is disposed on the first insulating layer 240 . The conductive metal layer 250 includes a plurality of first leads 252 and a second lead 254 . In this embodiment, the first lead 252 is electrically connected to the metal circuit layer 230 . In addition, the second lead 254 is filled into the first through hole 242 of the first insulating layer 240 to be electrically connected to the silicon substrate 210 . In addition, the second lead 242 is also electrically connected to at least one of the first lead 252 . The first pin 252 electrically connected to the second pin 254 is, for example, a ground pin or a power pin. In this way, the silicon substrate 210 can be realized through the first pin 252 electrically connected to the second pin 254. Ground or electrical connection to an external power source. In addition, since the silicon substrate 210 can be directly grounded, it is beneficial to perform a signal test on the silicon substrate 210 and to maintain the lowest potential of the silicon substrate 210 .

In this embodiment, the conductive metal layer 250 may be composed of multiple sub-metal layers. For example, the conductive metal layer 250 is composed of stacked first sub-metal layers 253 and second sub-metal layers 255 . The aforementioned first sub-metal layer 253 is different from the second sub-metal layer 255 . The material of the first sub-metal layer 253 includes, for example, aluminum or copper, and the material of the second sub-metal layer 255 includes, for example, nickel or gold, but is not limited thereto. The first sub-metal layer 253 is, for example, between the second sub-metal layer 255 and the first insulating layer 240 , and is adhered to the second sub-metal layer 255 and the first insulating layer 240 respectively.

The chip packaging structure 200 of this embodiment further includes, for example, a second insulating layer 280 and a plurality of solder balls 290 . The second insulating layer 280 is located on the first insulating layer 240 and covers the conductive metal layer 250 . The second insulating layer 280 is, for example, a solder resist layer, but is not limited thereto. The second insulating layer 280 has a plurality of second through holes 282 to expose a portion of each first lead 252 . The solder balls 290 are correspondingly disposed in the second through holes 282 to be electrically connected to the corresponding first pins 252 .

In addition, the chip package structure 200 further includes, for example, a protective layer 260 to cover the sensing element 220 and the metal circuit layer 230 . The protection layer 260 is made of epoxy resin, but not limited thereto. In addition, the chip package structure 200 may further include a protection substrate 270 disposed on the protection layer 260 . In this embodiment, the sensing element 220 is, for example, an optical sensing element, so the protective substrate 270 may be a transparent substrate (such as a glass substrate).

It should be noted that the first lead 252 and the metal circuit layer 230 may also be electrically connected in other ways. For example, in another embodiment, the metal circuit layer 230 may be electrically connected to the first pin 252 through a TSV disposed in the silicon substrate 210 .

The chip packaging process suitable for manufacturing the above chip packaging structure 200 will be described in detail below.

4A to 4M are schematic flowcharts of a chip packaging process according to an embodiment of the present invention. Please refer to FIG. 4A first. In the chip packaging process of this embodiment, for example, a silicon wafer 210' is firstly provided. The silicon wafer 210' has two opposite surfaces (ie, a first surface 212' and a second surface 214'). The first surface 212' of the silicon wafer 210' is provided with a metal circuit layer 230' and a plurality of sensing elements 220 electrically connected to the metal circuit layer 230'. In addition, in one embodiment, a protection layer 260' may be provided on one side of the first surface 212' of the silicon wafer 210' to cover and protect the metal circuit layer 230' and the sensing element 220. The protective layer 260' can be a transparent material layer, and the material of the protective layer 260' includes epoxy resin and the like, for example. Moreover, a protective substrate 270' may also be provided on the protective layer 260'. The protective substrate 270' can be a transparent substrate (such as a glass substrate).

After the protective substrate 270' is set, a wafer thinning process can be optionally performed to shrink the silicon wafer 210' to an appropriate thickness. Please refer to FIG. 4A and FIG. 4B together. The wafer thinning process is, for example, first grinding the second surface 214' of the silicon wafer 210' in FIG. 4A to reduce the thickness of the silicon wafer 210'. In FIG. Reference numeral 210" denotes the silicon wafer after thickness reduction. Then, the second surface 214" of the silicon wafer 210" is etched to planarize the second surface 214" and release the stress of the second surface 214".

Then, referring to FIG. 4C to FIG. 4E , a plurality of dicing lines 216 are formed in the silicon wafer 210 ″ to separate a plurality of chip units 218 and expose part of the metal circuit layer 230 ′. Between two adjacent dicing lines 216 There is a chip unit 218 in between, and each chip unit 218 includes a sensing element 220. Specifically, the step of forming the dicing line 216 is firstly formed on the second surface 214" of the silicon wafer 210" as shown in FIG. 4C Patterning the photoresist layer 30. The portion of the second surface 214″ not covered by the patterned photoresist layer 30 is the area where the dicing lines are intended to be formed. Next, as shown in FIG. 4D , an etching process is performed using the patterned photoresist layer 30 as a mask to remove part of the silicon substrate 210 ″ to form a dicing line 216 penetrating through the first surface 212 ′ and the second surface 214 ″, so that Part of the metal wiring layer 230 ′ is exposed by the scribe lines 216 . After that, as shown in FIG. 4E , the patterned photoresist layer 30 in FIG. 4D is removed.

It should be noted that the method for forming the dicing lines 216 is not limited to the lithographic etching process of this embodiment, and other suitable methods such as mechanical cutting and laser cutting can also be used to form the dicing lines 216 .

Afterwards, referring to FIG. 4F , a first insulating layer 240' is formed on the second surface 214" of the silicon wafer 210", and filled into the scribe line 216. The first insulating layer 240' is, for example, a solder resist layer, but is not limited thereto.

Next, referring to FIGS. 4G and 4H , a plurality of openings 241 and a plurality of first via holes 242 are formed in the first insulating layer 240'. The opening 241 and the first through hole 242 can be formed by etching, machining or laser machining. Specifically, the step of forming the first through holes 242 and the opening 241 is, for example, as shown in FIG. 4G , prior to forming a plurality of first through holes 242 in the first insulating layer 240'. Wherein, a first through hole 242 is formed in the first insulating layer 240' corresponding to each chip unit 218 to expose part of the second surface 214" of the silicon wafer 210". The shape of the first through hole 242 can be circular or square, but not limited thereto. After that, as shown in FIG. 4H , a plurality of openings 241 are formed in the first insulating layer 240 ′, and the openings 241 are respectively located on the cutting lines 216 and correspond to the cutting lines 216 one by one. It should be noted that in this embodiment, the opening 241 formed in the first insulating layer 240' needs to expose the metal circuit layer 230', so as to electrically connect the metal circuit layer 230' to the outside. In addition, when forming the opening 241, part of the metal circuit layer 230', the protection layer 260' and the protection substrate 270' may be removed, so that the opening 241 extends downward to the protection substrate 270'.

Next, referring to FIG. 4I to FIG. 4J , a conductive metal layer 250' is formed on the first insulating layer 240'. In this embodiment, the conductive metal layer 250' is composed of multiple sub-metal layers (such as the first sub-metal layer 253' and the second sub-metal layer 255'). In more detail, the method of forming the conductive metal layer 250' includes the following steps. First, referring to FIG. 4I , a first sub-metal layer 253' is formed, covering the first insulating layer 240', and filling the opening 241 and the first through hole 242. Then, the first sub-metal layer 253' is etched to form a plurality of first leads 252' and a plurality of second leads 254'. Next, referring to FIG. 4J , a second sub-metal layer 255' is formed, stacked on the first lead 252' and the second lead 254'. The first guide pin 252 in FIG. 2 is composed of a first guide pin 252' and a second sub-metal layer 255' stacked on the first guide pin 252', while the second guide pin 254 in FIG. The lead pin 254' is formed by the second sub-metal layer 255' stacked on the second lead pin 254'. In this embodiment, the conductive metal layer 250' includes a plurality of first leads 252 and a plurality of second leads 254. The first lead 252 is filled into the opening 241 and electrically connected to the metal circuit layer 230'. The second leads 254 are respectively filled into the first through holes 242 to be electrically connected to the silicon wafer 210 ″.

In another embodiment, the method for forming the conductive metal layer 250' may also include the following steps. Firstly, the first sub-metal layer 253' is formed to cover the first insulating layer 240 and fill the opening 241 and the first through hole 242. Then, a second sub-metal layer 255' is formed to cover the first sub-metal layer 253'. Next, the first sub-metal layer 253' and the second sub-metal layer 255' are etched to form a plurality of first leads 252 and a plurality of second leads 254.

Please refer to FIG. 3 again, each chip unit 218 includes a plurality of first leads 252 and a second lead 254 . In the process of forming the first lead 252 and the second lead 254 by etching, the second lead 254 can also be electrically connected to at least one of the first lead 252, so that the second lead 254 can be The electrical connection with the outside is realized through the first pin 252 . In this embodiment, the second lead 254 is electrically connected to a first lead 252 . The first pin 252 electrically connected to the second pin 254 is, for example, a ground pin or a power pin.

Please refer to FIG. 4K, after forming the first lead 252 and the second lead 254, a second insulating layer 280' can be optionally formed on the first insulating layer 240'. The second insulating layer 280' fills the opening 241 and the first through hole 242, and covers the conductive metal layer 250'. Then, a plurality of second via holes 282 are formed in the second insulating layer 280' to expose parts of the first pins 252. Next, as shown in FIG. 4L , a plurality of solder balls 290 are correspondingly disposed in the second through holes 282 , and are respectively electrically connected to the first pins 252 . In this way, the second insulating layer 280 can protect the conductive metal layer 250', and the conductive metal layer 250' can be electrically connected to external components through the solder balls 290.

Next, please refer to FIG. 4M , the silicon wafer 210 ″ is cut along the dicing line 216 to separate each chip unit 218 , wherein each chip unit 218 is the chip package structure 200 shown in FIG. 2 .

It should be noted that, in this embodiment, the above-mentioned chip packaging process is to fill the first lead 252 into the opening 241 so as to be electrically connected to the metal circuit layer 230 . However, the manner in which the metal circuit layer 230 is electrically connected to the first lead 252 is not limited thereto, therefore, the steps of the chip packaging process will be different accordingly. For example, in another embodiment, when the TSV disposed in the silicon substrate is used to electrically connect to the first lead, the chip packaging process needs to form a plurality of TSVs in the silicon wafer, so that the first The leads are electrically connected to the metal circuit layer through the TSVs.

To sum up, in the chip packaging structure and chip packaging process of the present invention, the silicon substrate can be connected with external components (such as printed circuit boards) through the second pins arranged in the first through holes of the first insulating layer. direct electrical connection. Therefore, the silicon substrate can be directly grounded, which is beneficial for signal testing of the silicon substrate and for maintaining the lowest potential of the silicon substrate.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the technical content disclosed above to make some changes or modify them into equivalent embodiments with equivalent changes, but as long as they do not depart from the technical solution of the present invention, the Technical Essence Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention.

Claims (21)

1. A chip packaging structure, comprising: A silicon substrate having a first surface and a second surface opposite to the first surface; a sensing element, disposed on the first surface of the silicon substrate; a metal circuit layer disposed on the first surface of the silicon substrate and electrically connected to the sensing element; a first insulating layer covering the second surface of the silicon substrate, the first insulating layer having a first through hole to expose part of the second surface of the silicon substrate; and A conductive metal layer is disposed on the first insulating layer, and the conductive metal layer includes: a plurality of first leads electrically connected to the metal circuit layer; and A second pin is filled in the first through hole to be electrically connected to the silicon substrate and electrically connected to at least one of the plurality of first pins. 2 . The chip package structure according to claim 1 , wherein the chip package structure further comprises a protection layer to cover the metal wiring layer and the sensing element. 3 . 3. The chip packaging structure according to claim 2, wherein the protection layer is made of epoxy resin. 4. The chip packaging structure according to claim 2, characterized in that: the chip packaging structure further comprises a protective substrate disposed on the protective layer. 5. The chip packaging structure according to claim 4, wherein the protective substrate is a transparent substrate. 6. The chip package structure according to claim 1, wherein the first lead electrically connected to the second lead is one of a ground lead and a power lead. 7. The chip packaging structure according to claim 1, characterized in that: the chip packaging structure further comprises: A second insulating layer covering the plurality of first leads and the second leads, wherein the second insulating layer has a plurality of second through holes to expose parts of each of the first leads ;as well as A plurality of solder balls are correspondingly disposed in the plurality of second through holes to be electrically connected to the plurality of first leads. 8. The chip packaging structure according to claim 1, characterized in that: the silicon substrate is provided with a plurality of TSVs, so that the plurality of first leads are electrically connected to the TSVs through the plurality of TSVs. The above metal circuit layer. 9. The chip packaging structure according to claim 1, wherein the conductive metal layer is composed of a plurality of sub-metal layers, including a stacked first sub-metal layer and a second sub-metal layer, and the The first sub-metal layer is different from the second sub-metal layer, wherein the first sub-metal layer is interposed between the second sub-metal layer and the first insulating layer for respectively adhering to the The second sub-metal layer is connected with the first insulating layer. 10. A chip packaging process, comprising: A silicon wafer is provided, the silicon wafer has a first surface and a second surface opposite to the first surface, the first surface is provided with a metal circuit layer and is electrically connected to the metal circuit layer multiple sensing elements; forming a plurality of dicing lines in the silicon wafer to separate a plurality of chip units and expose the metal wiring layer, wherein each chip unit includes one of the plurality of sensing elements; forming a first insulating layer on the second surface of the silicon wafer, and filling the plurality of dicing lines; forming a plurality of openings respectively located in the plurality of dicing lines in the first insulating layer, and forming a first through hole in the first insulating layer of each chip unit to expose the silicon crystal a circular portion of said second surface; A conductive metal layer is formed on the first insulating layer, the conductive metal layer includes a plurality of first leads and a plurality of second leads, and the plurality of first leads are electrically connected to the metal circuit layer, the plurality of second pins are respectively filled in the plurality of first through holes to be electrically connected to the silicon wafer, and electrically connected to at least one of the plurality of first through holes. guide pins; and The silicon wafer is diced along the plurality of dicing lines to separate the plurality of chip units. 11. The chip packaging process according to claim 10, characterized in that: before forming the plurality of dicing lines, further comprising disposing a protection layer on the silicon wafer to cover the metal wiring layer and the Multiple sensing elements. 12 . The chip packaging process according to claim 11 , wherein the chip packaging process further comprises disposing a protective substrate on the protective layer. 13 . 13. The chip packaging process according to claim 12, wherein the protective substrate is a transparent substrate. 14. The chip packaging process according to claim 12, characterized in that: after setting the protective substrate, it also includes performing a wafer thinning process, and the wafer thinning process includes: grinding the second surface of the silicon wafer to form a ground surface; and Planarize the abrasive surface. 15. The chip packaging process according to claim 10, wherein the method for forming the plurality of dicing lines comprises performing a lithographic etching process. 16. The chip packaging process according to claim 10, characterized in that: when forming the plurality of openings, the metal circuit layer is exposed, and when the conductive metal layer is formed, the conductive metal layer is filling the plurality of openings so that the plurality of first leads are electrically connected to the metal circuit layer. 17. The chip packaging process according to claim 16, wherein the conductive metal layer is composed of a plurality of sub-metal layers, and the method for forming the conductive metal layer comprises: forming a first sub-metal layer, covering the first insulating layer, and filling the plurality of openings and the plurality of first through holes; etching the first sub-metal layer to form the plurality of first leads and the plurality of second leads; and A second sub-metal layer is formed and stacked on the plurality of first leads and the plurality of second leads. 18. The chip packaging process according to claim 16, wherein the conductive metal layer is composed of a plurality of sub-metal layers, and the method for forming the conductive metal layer comprises: forming a first sub-metal layer, covering the first insulating layer, and filling the plurality of openings and the plurality of first through holes; forming a second sub-metal layer covering the first sub-metal layer; and The first sub-metal layer and the second sub-metal layer are etched to form the plurality of first leads and the plurality of second leads. 19. The chip packaging process according to claim 18, wherein the material of the first sub-metal layer includes aluminum or copper, and the material of the second sub-metal layer includes nickel or gold. 20. The chip packaging process according to claim 16, characterized in that: the chip packaging process further comprises: forming a second insulating layer on the first insulating layer to cover the plurality of first leads and the second leads; forming a plurality of second via holes in the second insulating layer to expose a portion of each of the first leads; and A plurality of solder balls are correspondingly arranged in the plurality of second through holes, and are respectively electrically connected to the plurality of first lead pins. 21. The chip packaging process according to claim 10, characterized in that: the chip packaging process further comprises: A plurality of through-silicon vias are formed in the silicon wafer, so that the plurality of first leads are electrically connected to the metal circuit layer through the plurality of through-silicon vias.