CN100336169C - Manufacturing method and structure of inductance element - Google Patents

Abstract

A method for manufacturing an inductance element is provided, wherein the inductance element is constructed on a substrate, and a flattened dielectric layer is arranged on the substrate. The inductance element structure comprises a first inductance graph, a second inductance graph and a third inductance graph, wherein the first inductance graph is configured on the dielectric layer. In addition, the second inductance graph is configured on the first inductance graph, and the second inductance graph is electrically connected with the first inductance graph. In addition, the third inductance pattern is configured on the second inductance pattern and is electrically connected with the second inductance pattern, wherein the first inductance pattern, the second inductance pattern and the third inductance pattern have similar patterns. Since the thickness of the inductance element is increased by the multilayer inductance pattern, the impedance of the inductance element can be reduced.

Description

Manufacturing method and structure of inductance element

technical field

The present invention relates to a manufacturing method and structure of a semiconductor element, and in particular to a manufacturing method and structure of an inductance element.

Background technique

In an integrated circuit, an inductance element is an important element, and the style of these inductance elements is generally a circular or square helical metal coil, and the application range of these inductance elements can be said to be quite wide. For the application field of high frequency, it has higher requirements on the quality of the inductance element, which means that the inductance element used in this field has a higher Q value. For example, in the application of wireless communication, the Q value of the inductance element must reach about 60. The definition of the above Q value is as follows:

Q＝ _ω0 L/R (1)

Where ω ₀ is the resonant angular frequency of the inductance element, R is the resistance of the inductance element, and L is the value of the inductance element of the metal coil.

It can be seen from the formula (1) that when L is fixed, the Q value will increase with the increase of the resonance angular frequency and/or the decrease of the resistance, and the resistance is proportional to the square of the current density, so one of the methods to increase the Q value is One is to increase the cross-sectional area of the metal coil to reduce the current density of the metal coil, thereby reducing the resistance of the metal coil and achieving the purpose of increasing the Q value.

Therefore, in the semiconductor process, if the cross-sectional area of the metal wire is to be increased to manufacture a high-Q inductance element, it can be done by increasing the width of the metal wire. However, if the width of the metal wire is too large, the charge tends to be concentrated and distributed at the corner of the metal wire, so that the increased cross-sectional area of the metal wire cannot achieve the effect of reducing the current density of the metal wire, and it is impossible to increase the current density of the metal wire. The Q value of the composed inductive element. Therefore, generally, the Q value of the inductance element that can be manufactured by the semiconductor process can only reach about 10 at most.

Moreover, most of the inductance components are arranged under the protective layer of the chip, so the inductance components are very close to the silicon substrate (less than 10 μm), therefore, the silicon substrate will become a conductor at high frequencies using high-frequency components , and consume a large amount of energy, which reduces the quality of the inductive element.

Moreover, although the known technology proposes to form a three-dimensional inductance element composed of metal wires/vias/metal wires through the metal interconnection process, however, the inductance element also has the problem of being too close to the silicon substrate. The layer window layer is limited by the process and cannot be made into a pattern similar to the metal wire layer, but only a large number of plugs can be formed to connect the upper and lower metal wire layers, so the Q value of the inductance element cannot be further improved. Therefore, how to solve the above-mentioned problems and improve the quality and Q value of the inductance element is a concern of the current process.

Contents of the invention

In view of this, the object of the present invention is to provide a method for manufacturing an inductance element, which can reduce the impedance of the inductance element and improve the Q value of the inductance element without adding additional process steps.

Another object of the present invention is to provide an inductance element structure, which can make the inductance element structure far away from the silicon substrate, so as to reduce the magnetic interference caused by the silicon substrate to the inductance element, so as to improve the performance of the chip.

Another object of the present invention is to provide an inductance element structure, the inductance element has a multi-layer structure and the entire inductance element has a uniform thickness, so that the Q value of the inductance element can be increased.

The present invention proposes a method for manufacturing an inductance element. The method is constructed on a substrate, and at least a first dielectric layer is formed on the substrate. The method for manufacturing the inductance element is first to simultaneously form the first dielectric layer A patterned first metal layer and a first inductor pattern. After that, a patterned second dielectric layer is formed on the first dielectric layer to cover the first metal layer, the first inductor pattern and the first dielectric layer, and the second dielectric layer has a plurality of first openings and several second openings, wherein the first openings expose the first metal layer, and the second openings expose the first inductor pattern. Then, filling the first opening and the second opening with metal to simultaneously form a second metal layer in the first opening, and form a second inductor pattern in the second opening, wherein the second metal layer and the first metal layer electrically connected, and the second inductance pattern is electrically connected to the first inductance pattern. Next, a patterned third metal layer is formed on the second metal layer, and a third inductance pattern is formed on the second inductance pattern at the same time, wherein the third metal layer is electrically connected to the second metal layer, and the third inductance pattern is connected to the second metal layer The second inductance pattern is electrically connected, and the first inductance pattern, the second inductance pattern and the third inductance pattern have similar patterns.

Therefore, it can be known from the above process that the present invention utilizes multilayer inductance patterns to increase the thickness of the metal wire of the inductance element, so that the resistance value of the inductance element can be reduced, and its Q value can be increased. In addition, in the process of the present invention, no additional The process of the inductance element can be completed by adding process steps, so the method of the present invention can be said to be quite simple.

The invention proposes an inductance element constructed on a substrate, and at least a planarized dielectric layer is disposed on the substrate. The inductance element structure includes a first inductance pattern, a second inductance pattern and a third inductance pattern, wherein the first inductance pattern is arranged on the dielectric layer. In addition, the second inductance pattern is configured on the first inductance pattern, and the second inductance pattern is electrically connected to the first inductance pattern. In addition, the third inductance pattern is disposed on the second inductance pattern, and the third inductance pattern is electrically connected to the second inductance pattern, wherein the first inductance pattern, the second inductance pattern and the third inductance pattern have similar patterns.

In the manufacturing method and structure of the inductance element, the first inductance pattern, the second inductance pattern and the third inductance pattern are formed simultaneously with the uppermost metal layer, metal plug and metal pad of the multilayer metal interconnection structure respectively.

In the manufacturing method and structure of the above-mentioned inductance element, the first inductance pattern, the second inductance pattern and the third inductance pattern form a three-dimensional inductance structure. For a symmetrical inductance structure, the inductance element will have a cross-overlapping area , and in order to avoid a short circuit of the inductance element, the first inductance pattern and the third inductance pattern are not connected by the second inductance pattern at the overlapping area of the inductance pattern.

The present invention proposes another method for manufacturing an inductance element. The inductance element is constructed on a substrate, and at least a first dielectric layer is formed on the substrate. The method is to simultaneously form a patterned a first metal layer and a second inductance pattern, then forming a patterned second dielectric layer on the first dielectric layer to cover the first metal layer, the first inductance pattern and the first dielectric layer, and The second dielectric layer has a plurality of first openings and a plurality of second openings, wherein the first openings expose the first metal layer, and the second openings expose the first inductor pattern, and then the filling is formed on the second dielectric layer. A second metal layer that fills the first opening, and at the same time forms a second inductor pattern that fills the second opening on the second dielectric layer, wherein the second metal layer is electrically connected to the first metal layer, and the second inductor The pattern is electrically connected with the first inductance pattern.

In the manufacturing method of the inductance element above, the first inductance pattern, the second inductance pattern and the third inductance pattern are formed simultaneously with the uppermost metal layer, the metal plug, and the metal pad of the multilayer metal interconnection structure, and Metal plugs and metal pads (the second inductor pattern and the third inductor pattern) are formed in the same deposition and lithographic etching steps.

In the manufacturing method of the above-mentioned inductance element, the first inductance pattern and the second inductance pattern form a three-dimensional inductance structure. For a symmetrical inductance structure, the inductance element will have a cross overlapping area, and in order to avoid the inductance element The short circuit, at the overlapping area of the inductance pattern, is such that the first inductance pattern is not connected to the second inductance pattern.

Therefore, it can be seen from the manufacturing method and structure of the above-mentioned inductive element that the present invention utilizes a multilayer inductive pattern to increase the thickness of the metal wire of the inductive element, so that the resistance value of the inductive element can be reduced, and its Q value can be increased, thereby improving the inductive element. quality.

Moreover, since each layer of the multilayer inductance element of the present invention has a similar pattern, the entire inductance element has a uniform thickness, thereby further effectively increasing its Q value.

Moreover, the inductance element can be manufactured together with the process of the metal pad, so the formed inductance element is farther away from the substrate than conventionally known, so the magnetic interference caused by the substrate to the inductance element can be reduced to improve chip performance.

In addition, because the inductor pattern corresponding to the metal plug and the metal pad can be completed in the same deposition and photolithographic etching steps of the present invention, the process is simplified.

Furthermore, since the inductance patterns corresponding to the metal plug and the metal pad are made of the same material, the contact resistance caused by the contact of different materials can be reduced, thereby increasing the Q value of the inductance element.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, several preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

FIG. 1 is a schematic top view of an inductor element according to a first embodiment of the present invention.

2A to 2C are schematic cross-sectional views of the manufacturing process along I to I' in FIG. 1 .

3A to 3C are schematic cross-sectional views of the manufacturing process along II to II' in FIG. 1 .

4A to 4C are schematic top views of the inductor pattern in FIG. 1 , wherein FIG. 4A is the inductor pattern 104 a , FIG. 4B is the inductor pattern 110 b , and FIG. 4C is the inductor pattern 112 b.

FIG. 5 is a schematic top view of the structure of an inductance element according to the second embodiment of the present invention.

6A to 6C are schematic cross-sectional views of the manufacturing process along III to III' in FIG. 5 .

7A to 7C are schematic top views of the inductor pattern in FIG. 5 , wherein FIG. 7A is the inductor pattern 204 a , FIG. 7B is the inductor pattern 210 b , and FIG. 7C is the inductor pattern 214 b.

Explanation of reference numbers

100, 200: Substrate

101, 103, 105: area

102, 106, 202, 206: dielectric layer

104a, 110a, 112a, 204a, 210a, 212a, 214a: metal layers

104b, 110b, 112b, 204b, 210b, 212b, 214b: inductance pattern

108a, 108b, 208a, 208b: openings

Detailed ways

first embodiment

Fig. 1 is a schematic top view showing a structure for forming an inductance element according to the first embodiment of the present invention; Fig. 2A to Fig. 2C are schematic cross-sectional views showing the production process from I-I' in Fig. 1; Fig. 3A to Fig. 3C are representational diagrams 1, the schematic cross-sectional view of the manufacturing process from II-II', wherein the areas marked 101, 103, and 105 in Figure 1 correspond to Figures 2A to 2C and Figures 3A to 3C, and the area 105 is a representative area 101 overlaps with region 103 . And in this embodiment, it discloses a symmetrical circular spiral inductance element, and the inductance element has a cross overlapping area.

Referring to Fig. 1, Fig. 2A and Fig. 3A at the same time, the manufacture of the inductance element is first to provide a substrate 100, and at least a dielectric layer 102 is formed on the substrate 100, and its material is, for example, silicon oxide, silicon nitride, low dielectric constant Generally known dielectric materials such as materials are formed by, for example, first depositing the dielectric layer 102 on the substrate 100 by chemical vapor deposition, and then performing a planarization step by chemical mechanical polishing. It is well known by those skilled in the art that the dielectric layer 102 may have a multi-layer structure, and a plurality of elements and metal interconnections may be formed on the substrate 100 and in the dielectric layer 102 .

Then, a patterned metal layer 104a and an inductance pattern 104b are simultaneously formed in the dielectric layer 102, wherein a top view of the inductance pattern 104b is shown in FIG. The uppermost metal layer of the structure, that is, during the metal interconnection process, can form the inductor pattern 104b in the same process.

In addition, the material of the metal layer 104a and the inductor pattern 104b is, for example, copper. The forming method is, for example, a generally well-known damascene process. Firstly, a patterned opening (not shown) is formed in the dielectric layer 102, and then the metal The material is filled into the opening to form the patterned metal layer 104a and the inductor pattern 104b.

Next, referring to FIG. 1 , FIG. 2B and FIG. 3B , a patterned dielectric layer 106 is formed on the dielectric layer 102 to cover the metal layer 104 a , the inductor pattern 104 b and the dielectric layer 102 . In addition, the dielectric layer 106 further has several openings 108a, 108b, wherein the opening 108a exposes the metal layer 104a, and the opening 108b exposes the inductor pattern 104b.

In addition, the method of forming the dielectric layer 106 is, for example, to form a dielectric layer (not shown) on the dielectric layer 102 to cover the metal layer 104 a, the inductor pattern 104 b and the dielectric layer 102 . Chemical mechanical polishing is then performed to completely planarize the dielectric layer. Then, the dielectric layer is patterned using a lithographic etching process known in the art to define the dielectric layer 106 with a plurality of openings 108a, 108b.

In addition, it is worth mentioning that, in order to avoid the short circuit of the inductance element in the design, when the above-mentioned dielectric layer is patterned to form the opening 108b, the opening 108b is not formed in the region 101 and the region 103, which means that the opening 108b formed in the subsequent process The inductance pattern (not shown) of the uppermost layer will not connect the inductance pattern 104b in the region 101 and the region 103 through the inductance pattern (not shown) of the middle layer, and except the region 101 and the region 103, the pattern track of the opening 108b is and The pattern of the inductor pattern 104b is similar.

Afterwards, continue to refer to FIG. 1 , FIG. 2B and FIG. 3B at the same time, filling metal in several openings 108a, 108b to simultaneously form the metal layer 110a in the opening 108a, and form the inductor pattern 110b in the opening 108b. Wherein, the formed metal layer 110a is, for example, used as a metal plug, and is electrically connected to the metal layer 104a.

In addition, the way to form the inductor pattern 110b and the metal layer 110a is, for example, to form a metal layer (not shown) in the openings 108a, 108b and on the dielectric layer 106, wherein the metal material is, for example, tungsten, and the forming method is, for example, low voltage chemical vapor deposition or sputtering. Afterwards, a planarization step is performed to remove the metal material outside the openings 108a, 108b to form the metal layer 110a and the inductor pattern 110b. Therefore, the inductor pattern 110b is formed simultaneously with the metal layer 110a (eg, metal plug) in the same step.

Moreover, the top view of the formed inductance pattern 110b is as shown in FIG. 4B, which is electrically connected to the inductance pattern 104b, and, in addition to avoiding short circuit of the inductance element in design, near the overlapping area of the metal wires (regions 101, 103, 105) Except that the inductor pattern 110b is not formed, the inductor pattern 110b is similar to the inductor pattern 104b.

Next, referring to FIG. 1, FIG. 2C and FIG. 3C, a patterned metal layer 112a is formed on the metal layer 110a, and an inductor pattern 112b is formed on the inductor pattern 110b at the same time, wherein the metal layer 112a is, for example, used as a metal pad For use, it is electrically connected to the metal layer 110a.

In addition, the material of the metal layer 112a and the inductor pattern 112b is, for example, aluminum, and the formation method thereof is, for example, forming a comprehensive metal layer (not shown) on the dielectric layer 106, and the formation method is, for example, physical vapor deposition. Then, the metal layer is patterned to form the metal layer 112a and the inductor pattern 112b by using known lithographic etching techniques. Therefore, the inductor pattern 112b is formed in the same step as the metal layer 112a (eg, the metal pad).

Moreover, the top view of the formed inductance pattern 112b is shown in FIG. 4C, which is electrically connected to the inductance pattern 110b, and, in addition to avoiding the short circuit of the inductance element in design, the inductance pattern 112b is only formed at the region 105 and the region 103. Additionally, the inductor pattern 112b has a similar pattern to the inductor patterns 110b, 104b.

It is worth mentioning that the above-mentioned multi-layer inductor patterns 104b, 110b and 112b constitute a three-dimensional inductor structure, the top view of which is shown in FIG. 104b, the dielectric layer 106 and the inductance pattern 112b, and the inductance pattern 104b and the inductance pattern 112b in this area 105 are not connected by the inductance pattern 110b. When flowing along the three-dimensional inductance structure, the current will only flow along the first inductance pattern when the current flows through the cross-overlapping region for the first time, and only flow along the third inductance pattern when the current flows through the cross-overlapping region for the second time, Therefore, it is possible to avoid the short circuit of the inductor pattern in the overlapping area.

In addition, the present invention is not limited to the above-mentioned process steps, and the above-mentioned metal layers 110a, 112a, and the inductor patterns 110b, 112b formed at the same time can be completed by a known dual damascene process.

Therefore know by above-mentioned operation, the present invention utilizes the inductance pattern of multilayer to increase the thickness of the metal wire of inductance element, can reduce the resistance value of inductance element like this, and increase its Q value, in addition, in operation of the present invention, do not need The process of the inductance element can be completed by adding additional process steps, so the method of the present invention can be said to be quite simple.

Moreover, in the process of the present invention, the opening 108b for forming the inductor pattern 110b can be formed together with the opening 108a of the plug for forming the metal pad, because the openings 108a, 108b are located in the metal interconnection structure. The uppermost layer, so there are few process restrictions, so that the opening 108b can have a similar pattern to the inductor pattern 104b.

The structure of the inductance element produced by the above process is described below, continue to refer to Fig. 1, Fig. 2C and Fig. 3C at the same time, wherein Fig. 1 is a schematic top view of the inductance element of the present invention, and Fig. 2C is a schematic diagram of Fig. 1 along I To the schematic cross-sectional view of I', Fig. 3C is a schematic cross-sectional view along II to II' of Fig. 1, wherein the areas marked 101, 103, 105 in Fig. 1 correspond to Fig. 2C and Fig. 3C, and the area 105 is the portion where the region 101 and the region 103 overlap.

The structure of the inductance element of the present invention is built on the substrate 100, and the dielectric layer 102 is disposed on the substrate 100 at least. The inductor element structure includes three layers of inductor patterns 104b, 110b, 112b.

Wherein, the inductance pattern 104b is arranged on the dielectric layer 102. The top view of the inductance pattern 104b is shown in FIG. The metal layer 104a is, for example, the uppermost metal layer of the multilayer metal interconnection structure on the substrate 100, and the material of the metal layer 104a and the inductor pattern 104b is, for example, copper. It is worth mentioning that, in the region 103 , except the region 105 overlapping with the region 101 is configured with the inductor pattern 104 b , the rest of the region 103 is not configured with the inductor pattern 104 b.

In addition, the inductance pattern 110b is disposed on the inductance pattern 104b. The top view of the inductance pattern 110b is shown in FIG. 104b is electrically connected. In addition, a metal layer 110a is further disposed on the metal layer 104a, that is, the metal layer 110a and the inductor pattern 110b are disposed on the same film layer, the metal layer 110a is, for example, a metal plug, and the metal layer 110a and the inductor pattern 110b The material is, for example, tungsten. It is worth mentioning that in the area 103 and the area 101 (including the overlapping area 105 ), there is no configuration of the inductor pattern 110b.

In addition, the inductance pattern 112b is disposed on the inductance pattern 110b. The top view of the inductance pattern 112b is shown in FIG. The inductor pattern 110b is electrically connected. In addition, a metal layer 112a is further disposed on the metal layer 110a, that is, the metal layer 112a and the inductor pattern 112b are disposed on the same film layer, and the metal layer 112a is, for example, the metal pad 114 . It is worth mentioning that, in the region 101 , except the region 105 overlapping with the region 103 is configured with the inductor pattern 112 b , the rest of the region 101 is not configured with the inductor pattern 112 b.

In addition, the three-layer inductance patterns 104b, 110b, and 112b above constitute a three-dimensional inductance structure. 106 and the inductance pattern 112b, and the inductance pattern 104b and the inductance pattern 112b in the area 105 are not connected by the inductance pattern 110b, so that the inductance pattern will not be short-circuited in the overlapping area.

second embodiment

5 is a schematic top view showing the structure of an inductance element according to the second embodiment of the present invention; FIGS. 6A to 6C are schematic cross-sectional views showing the manufacturing process from III-III' in FIG. 5 . And in this embodiment, it is disclosed as a concentric spiral inductance element.

Referring to Fig. 5 and Fig. 6A at the same time, the manufacture of the inductance element is first to provide the substrate 200, then at least a dielectric layer 202 is formed on the substrate 200, wherein the material is, for example, silicon oxide, silicon nitride, low dielectric constant material Generally known dielectric materials are formed by, for example, first depositing the dielectric layer 202 on the substrate 200 by chemical vapor deposition, and then performing a planarization step by chemical mechanical polishing. It is well known to those skilled in the art that the dielectric layer 202 may have a multi-layer structure, and a plurality of elements and metal interconnections may be formed on the substrate 200 and in the dielectric layer 202 .

Then, a patterned metal layer 204a and an inductor pattern 204b are simultaneously formed in the dielectric layer 202, wherein a top view of the inductor pattern 204b is shown in FIG. 7A, and the metal layer 204a is, for example, a multilayer metal interconnection on the substrate 200 The uppermost metal layer of the structure, that is, during the metal interconnection process, can form the inductor pattern 204b in the same process.

In addition, the material of the metal layer 204a and the inductor pattern 204b is, for example, copper, and the formation method is, for example, a generally well-known damascene process, first forming a patterned opening (not shown) in the dielectric layer, and then adding the metal material The opening is filled to form a patterned metal layer 204a and an inductor pattern 204b.

Next, referring to FIG. 5 and FIG. 6B simultaneously, a patterned dielectric layer 206 is formed on the dielectric layer 202 to cover the metal layer 204 a , the inductor pattern 204 b and the dielectric layer 202 . In addition, there are several openings 208a, 208b in the dielectric layer 206, wherein the opening 208a exposes the metal layer 204a, and the opening 208b exposes the inductor pattern 204b, and the trace of the pattern of the opening 208b is similar to that of the inductor pattern 204b, That is, a spiral opening 208b is formed along the inductor pattern 204b.

In addition, the method of forming the dielectric layer 206 is, for example, to form a dielectric layer (not shown) on the dielectric layer 202 to cover the metal layer, the inductor pattern 204 and the dielectric layer 202 . Chemical mechanical polishing is then performed to completely planarize the dielectric layer. The dielectric layer is then patterned using a lithographic etching process known in the art to define a dielectric layer 206 having a plurality of openings 208a, 208b.

Afterwards, referring to FIG. 5 and FIG. 6C at the same time, a metal layer 210a and an inductor pattern 210b filling the openings 208a and 208b are formed on the dielectric layer 206, wherein the metal layer 210a is electrically connected to the metal layer 204a, and can be regarded as formed by The metal layer 212a in the opening and the metal layer 214a on the dielectric layer 206 are formed, and the metal layer 212a in the opening 208a can be used as a metal plug, and the metal layer 214a on the dielectric layer 206 can be used as a plug, for example. For metal pads.

The inductor pattern 210b can be regarded as a single inductor pattern, or it can be regarded as composed of the inductor pattern 212b in the opening 208b and the inductor pattern 214b on the dielectric layer 206 as in the first embodiment. Moreover, since the opening 208b has a shape similar to the inductor pattern 204b, the formed inductor patterns 212b, 214b can also have a similar shape to the inductor pattern 204b.

In addition, the way to form the inductor pattern 210b and the metal layer 210a is, for example, to form a metal layer (not shown) in the openings 208a, 208b and on the dielectric layer 206, wherein the metal material is, for example, aluminum, and the forming method is, for example, physical vapor deposition method. Afterwards, the metal layer is patterned to form the metal layer 210 a ( 212 a , 214 a ) and the inductor pattern 210 b ( 212 b , 214 b ) by using known lithographic etching techniques. Therefore, the inductor pattern 210b is formed simultaneously with the metal layer 210a in the same step.

Equally, because the present invention is to utilize multi-layer inductance pattern to increase the thickness of the metal wire of inductance element, therefore can reduce the resistance value of inductance element, and increase its Q value, in addition, in the process of the present invention, do not need additional The process of the inductance element can be completed by adding process steps, so the method of the present invention can be said to be quite simple.

Moreover, in the process of the present invention, the opening 208b for forming the inductor pattern 210b can be formed together with the opening 208a of the plug for forming the metal pad, because the openings 208a, 208b are located in the metal interconnection structure. The uppermost layer, so there are few process restrictions, so that the opening 208b can have a similar pattern to the inductor pattern 204b.

Furthermore, in this embodiment, since the metal layers 212a, 214a and the inductor patterns 212b, 214b formed at the same time can be completed in the same deposition and lithographic etching steps, compared with the first embodiment, the process can be simplified. , for the inductance patterns 212b and 214b, since they are made of the same material, the contact resistance caused by the contact of different materials can be reduced and the Q value thereof can be increased. Furthermore, for the inductor pattern 212b, since aluminum can be used, compared with the use of tungsten in the first embodiment, the contact resistance can be reduced and the Q value thereof can be increased.

The following is a description of the structure of the inductance element produced by the above process. Continue to refer to FIG. 5 and FIG. 6C at the same time, wherein FIG. 5 is a schematic top view of the inductance element of the present invention, and FIG. ’Schematic cross-section.

The structure of the inductance element of the present invention is built on the substrate 200, and the dielectric layer 202 is disposed on the substrate 200 at least. The inductor element structure includes inductor patterns 204b, 210b.

Wherein, the inductance pattern 204b is disposed on the dielectric layer 202. The top view of the inductance pattern 204b is shown in FIG. On the same film layer, the metal layer 204 a is, for example, the uppermost metal layer of the multilayer metal interconnection structure on the substrate 200 , and the material of the metal layer 204 a and the inductor pattern 204 b is, for example, copper.

The inductor pattern 210b is disposed on the inductor pattern 204b. A top view of the inductor pattern 210b is shown in FIG. 7C , and the inductor pattern 210b is electrically connected to the inductor pattern 204b. In addition, a metal layer 210a is further disposed on the metal layer 204a, and the metal layer 210a is disposed on the same film layer as the inductor pattern 210b. In this embodiment, the inductor pattern 210b can be regarded as composed of the inductor pattern 212b and the inductor pattern 214b. From this point of view, the top view of the inductor pattern 212b is as shown in FIG. 7B, and the top view of the inductor pattern 212b is as shown in FIG. 7C. Similarly, the metal layer 210a can be regarded as composed of a metal layer 212a and a metal layer 214a, wherein the metal layer 212a is, for example, a metal plug, the metal layer 214a is, for example, a metal pad, and the materials of the metal layer 210a and the inductor pattern 210b For example aluminum.

Of course, the form of the above-mentioned inductance element is not limited to the symmetrical circular spiral pattern shown in Figure 1 or the concentric circular spiral pattern shown in Figure 5, other such as symmetrical square spiral pattern or concentric square spiral pattern can also use the present invention to complete.

Moreover, in the symmetrical circular spiral inductance element of the first embodiment, the first inductance pattern, the second inductance pattern, and the third inductance pattern (the uppermost metal layer, the metal plug, and the metal welding pad) are made of different The deposition process is formed, but the present invention is not limited thereto. The inductance element of the first embodiment can also be the same as the second embodiment, so that the second inductance pattern and the third inductance pattern (metal plugs, metal pads) are on the same The steps of deposition and lithographic etching are completed. Furthermore, any form of inductance element can be formed through the processes disclosed in the first embodiment or the second embodiment.

In summary, it can be seen from the above structure that the present invention uses multi-layer inductance patterns to increase the thickness of the metal wire of the inductance element, so that the resistance value of the inductance element can be reduced, the Q value can be increased, and the quality of the inductance element can be improved. .

Moreover, since each layer of the multilayer inductive element of the present invention has a similar pattern, the entire inductive element structure has a uniform thickness, thereby further effectively increasing its Q value.

Moreover, since the inductance element can be manufactured together with the process of forming metal pads, the formed structure is farther away from the substrate than conventionally known, so the magnetic interference caused by the substrate to the inductance element can be reduced to improve chip performance.

In addition, because the inductor pattern corresponding to the metal plug and the metal pad can be completed in the same deposition and photolithographic etching steps of the present invention, the process is simplified.

Furthermore, since the inductance pattern corresponding to the metal plug or the metal pad is made of the same material, the contact resistance caused by the contact of different materials can be reduced, thereby increasing the Q value of the inductance element.

Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can certainly make some changes and modifications without departing from the spirit and scope of the present invention. , so the protection scope of the present invention should be regarded as defined by the claims of the patent application.

Claims (17)

1. the manufacture method of an inductance element, this inductance element framework is formed with one first dielectric layer at least on this substrate on a substrate, and this method comprises:

In this first dielectric layer, form a patterned the first metal layer and one first inductive graph simultaneously;

On this first dielectric layer, form patterned one second dielectric layer, to cover this first metal layer, this first inductive graph and this first dielectric layer, and this second dielectric layer has most first openings and most second openings, wherein these first openings expose this first metal layer, and these second openings expose this first inductive graph;

In these first openings and these second openings, insert a metal, in these first openings, to form one second metal level simultaneously, and in these second openings, form one second inductive graph, wherein this second metal level is electrically connected with this first metal layer, and this second inductive graph is electrically connected with this first inductive graph; And

On this second metal level, form patterned one the 3rd metal level, and on this second inductive graph, form one the 3rd inductive graph simultaneously, wherein the 3rd metal level is electrically connected with this second metal level, and the 3rd inductive graph is electrically connected with this second inductive graph.

Wherein first inductive graph, second inductive graph have similar figure to the 3rd inductive graph.

2. the manufacture method of inductance element as claimed in claim 1, it is characterized in that: this first metal layer comprises the topmost metal layer of the multiple layer metal internal connection-wire structure on this substrate.

3. the manufacture method of inductance element as claimed in claim 1, it is characterized in that: this second metal level comprises metal plug.

4. the manufacture method of inductance element as claimed in claim 1, it is characterized in that: the 3rd metal level comprises metal pad.

5. the manufacture method of inductance element as claimed in claim 1, it is characterized in that: this inductance element comprises symmetrical round screw thread formula inductance element or circular concentric screw type inductive element.

6. the manufacture method of inductance element as claimed in claim 1, it is characterized in that: this first inductive graph, this second inductive graph and the 3rd inductive graph constitute a three-dimensional induction structure, and should have a juxtaposition zone by the solid induction structure, and in this juxtaposition zone, this first inductive graph is not connected by this second inductive graph with the 3rd inductive graph, so that electric current is when this solid induction structure flows, when flowing through for the first time this juxtaposition zone, only flow, and when flowing through for the second time this juxtaposition zone, only flow along the 3rd inductive graph along this first inductive graph.

7. inductance element, this inductance element framework disposes a dielectric layer at least on this substrate on a substrate, and this structure comprises:

One is disposed at first inductive graph in this dielectric layer;

One is disposed at second inductive graph on this first inductive graph, and this second inductive graph is electrically connected with this first inductive graph; And

One is disposed at the 3rd inductive graph on this second inductive graph, and the 3rd inductive graph is electrically connected with this second inductive graph,

Wherein first inductive graph, second inductive graph have similar figure to the 3rd inductive graph,

This first inductive graph, this second inductive graph and the 3rd inductive graph constitute a three-dimensional induction structure, and should have a juxtaposition zone by the solid induction structure, in described juxtaposition location, this first inductive graph is not connected by this second inductive graph with the 3rd inductive graph, so that electric current is when this solid induction structure flows, when flowing through for the first time this juxtaposition zone, only flow, and when flowing through for the second time this juxtaposition zone, only flow along the 3rd inductive graph along this first inductive graph.

8. inductance element as claimed in claim 7 is characterized in that: the patterned the first metal layer on this first inductive graph and this substrate is same one deck, and this first metal layer comprises the topmost metal layer of the multiple layer metal internal connection-wire structure on this substrate.

9. inductance element as claimed in claim 7 is characterized in that: patterned one second metal level on this second inductive graph and this substrate is same one deck, and this second metal level comprises metal plug.

10. inductance element as claimed in claim 7 is characterized in that: patterned one the 3rd metal level on the 3rd inductive graph and this substrate is same one deck, and the 3rd metal level comprises metal pad.

11. inductance element as claimed in claim 7 is characterized in that: this inductance element comprises symmetrical round screw thread formula inductance element or circular concentric screw type inductive element.

12. the manufacture method of an inductance element, this inductance element framework are formed with one first dielectric layer at least on this substrate on a substrate, this method comprises:

In this first dielectric layer, form a patterned the first metal layer and one first inductive graph simultaneously;

On this first dielectric layer, form patterned one second dielectric layer, to cover this first metal layer, this first inductive graph and this first dielectric layer, and this second dielectric layer has most first openings and most second openings, wherein these first openings expose this first metal layer, and these second openings expose this first inductive graph; And

On this second dielectric layer, form one second metal level that fills up these first openings, and one second inductive graph that these second openings are filled up in formation on this second dielectric layer simultaneously, wherein this second metal level is electrically connected with this first metal layer, and this second inductive graph is electrically connected with this first inductive graph.

13. the manufacture method of inductance element as claimed in claim 12 is characterized in that: this first metal layer comprises the topmost metal layer of the multiple layer metal internal connection-wire structure on this substrate.

14. the manufacture method of inductance element as claimed in claim 12 is characterized in that: this second metal level comprises metal plug and metal pad.

15. the manufacture method of inductance element as claimed in claim 14 is characterized in that: the material of this second metal level and this second inductive graph comprises aluminium.

16. the manufacture method of inductance element as claimed in claim 12 is characterized in that: this inductance element comprises symmetrical round screw thread formula inductance element or circular concentric screw type inductive element.

17. the manufacture method of inductance element as claimed in claim 12, it is characterized in that: this first inductive graph and this second inductive graph constitute a three-dimensional induction structure, and should have a juxtaposition zone by the solid induction structure, and in this juxtaposition zone, this first inductive graph is not connected with this second inductive graph, so that electric current is when this solid induction structure flows, when flowing through for the first time this juxtaposition zone, only flow, and when flowing through for the second time this juxtaposition zone, only flow along this second inductive graph along this first inductive graph.

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