Sandeep Shukla

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Papers by Sandeep Shukla

Optimizing System Models for Simulation Efficiency

Abstract This chapter describes algorithmic ways to transform a multi-threaded SystemC model into... more Abstract This chapter describes algorithmic ways to transform a multi-threaded SystemC model into a non-threaded model for simulation efficiency. Such a transformation must be correctness preserving, and the transformed model must simulate the original model. We show simulation results to establish the efficiency enhancement by the systematic transformation. Keywords: SystemC Threads, Methods, Simulation Efficiency. Transformation. Optimization

A Compositional Behavioral Modeling Framework for Embedded System Design and Conformance Checking

We propose a framework based on a synchronous multi-clocked model of computation to support the i... more We propose a framework based on a synchronous multi-clocked model of computation to support the inductive and compositional construction of scalable behavioral models of embedded systems engineered with de facto standard design and programming languages. Behavioral modeling is seen under the paradigm of type inference. The aim of the proposed type system is to capture the behavior of a system under design and to re-factor it by performing global optimizing and architecture-sensitive transformations on it. It allows to modularly express a wide spectrum of static and dynamic behavioral properties and automatically or manually scale the desired degree of abstraction of these properties for efficient verification. The type system is presented using a generic and language-independent static single assignment intermediate representation.

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Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications

Abstract: Specification of a concurrent system using CAOS (Concurrent Action Oriented Specificati... more Abstract: Specification of a concurrent system using CAOS (Concurrent Action Oriented Specifications)(CAOS) as illustrated by Bluespec Inc.&amp;amp;amp;amp;amp;amp;amp;amp;#x27;s Bluespec System Verilog provides a high abstraction level, effective concurrency management through atomicity, and powerful compilation to efficient RTL hardware. In this paper, we present two algorithms that make CAOS to RTL synthesis power-aware and produce RTL that can be synthesized into hardware competitive in terms of power/area/slack trade-off against the well-known ...

Verifying Compiler Based Refinement of Bluespec TM Specifications Using the SPIN Model Checker

The underlying model of computation for PROMELA is based on interacting processes with asynchrono... more The underlying model of computation for PROMELA is based on interacting processes with asynchronous communication, and hence SPIN has been mainly used as a verification engine for concurrent software systems. On the other hand, hardware verification has mostly focused on clock synchronous register-transfer level (RTL) models. As a result, verification tools such as SMV which are based on synchronous state machine models have been used more frequently for hardware verification. However, as levels of abstractions are being raised in hardware design and as high-level synthesis is being promoted for synthesizing RTL, hardware design verification problems are changing in nature. In this paper, we consider a specific high-level hardware description langauge, namely, Bluespec System Verilog (BSV). The programming model of BSV is based on concurrent guarded actions, which we also call as Concurrent Action Oriented Specification (CAOS). High-level synthesis from BSV models has been shown to produce efficient RTL designs. Given the industry traction of BSV-based high-level synthesis and associated design flow, we consider the following formal verification problems: (i) Given a BSV specification S of a hardware design, does it satisfy certain temporal properties? (ii) Given a BSV specification S, and an implementation R synthesized from S using a BSV-based synthesis tool, does R conform to the behaviors specified by S; that is, is R a refinement of S? (iii) Given a different implementation R synthesized from S using some other BSVbased synthesis tool, is R a refinement of R as well? In this paper, we show how SPIN Model Checker can be used to solve these three problems related to the verification of BSV-based designs. Using a sample design, we illustrate how our approach can be used for verifying whether the designer intent in the BSV specification is accurately matched by its synthesized hardware implementation.

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A Formally Verified Peak-Power Reduction Technique for Hardware Synthesis from Concurrent Action-Oriented Specifications

Abstract: High-level Concurrent Action-Oriented Specifications (CAOS) of hardware designs based o... more Abstract: High-level Concurrent Action-Oriented Specifications (CAOS) of hardware designs based on concurrent atomic actions can be synthesized into efficient hardware implementations as exemplified by the Bluespec Compiler. However, peak-power aware synthesis has not been available for such compilers. In this paper, we propose a technique for peak-power reduction (without unduly compromising latency) during high-level synthesis from CAOS. We demonstrate the efficacy of our technique through experimental results on ...

Programming Models for Multi-Core Embedded Software

Introduction of multi-core processors is one of the most significant changes in the semiconductor... more Introduction of multi-core processors is one of the most significant changes in the semiconductor industry in recent years. The shift to multi-core technology was preceded by a brief stint with the use of multiple virtual processors on top of a uniprocessor machine. Virtual processor techniques like the Intel Hyper-Threading technology [5] depended heavily on the distribution of computation between virtual processes. Improvement in performance due to the new techniques notwithstanding, the software which runs on these machines has ...

Power Aware High Level Synthesis of Hardware Coprocessors

Abstract: Power reduction techniques such as clock-gating are used in almost all the ASIC designs... more Abstract: Power reduction techniques such as clock-gating are used in almost all the ASIC designs. This technique helps in achieving quite a lot of power savings. Logic synthesis tools provide a good support for the implementation of clock-gating. However, above RTL there are not many existing techniques/tools. This paper presents detailed analysis of enabling clock-gating around high-level synthesis. We propose a novel system-level design methodology, which utilizes a&amp;#x27;relative power reduction model&amp;#x27;that can help in predicting ...

A Framework for Analyzing Load-Carrying-Capacity of Plug-In Electric Vehicles and Impact on Solar Generators

In this study, we have: �� Proposed an efficient and practical algorithm for optimizing the V2G ... more In this study, we have: �� Proposed an efficient and practical algorithm for optimizing the V2G operations. �� Developed a flexible multi-phase simulation framework to estimate and quantify the impact of PEVs on the grid. �� Leveraged the framework and actual hourly load data from New York City to compute the effective load carrying capacity (ELCC) contributed by PEVs. �� Utilized actual hourly time-synchronized solar radiation data in the framework to compute solar generator ELCC with and without PEVs. �� Used capacity auction market data to quantify the ...

Networking technologies for wide-area measurement applications

A wide-area measurement system (WAMS) consists of advanced measurement technology, the latest com... more A wide-area measurement system (WAMS) consists of advanced measurement technology, the latest communication network infrastructure, and integrated operational framework. The supervisory control and data acquisition (SCADA) infrastructure for energy-management system (EMS) has been widely used in power systems for a long time. Some of the functionalities of an EMS are system state monitoring, tie-line bias control, and economic dispatch . However, in recent years, various deficiencies of the existing SCADA-based EMS (such as quasi-steady-state calculation, non-synchronized data acquisition, and relatively low data transmission rate) have been pointed out. These defects make it impossible to sample the global state of a power system in real time. As more and more wide-area blackouts are reported, it is clear that acquiring real-time or wide-area state information would be needed in the future. The state information in terms of phasors of voltages and currents from a distributed wide area in real time is therefore critical for avoiding large-area disturbances by effecting wide-area control based on wide-area measurements.

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A hierarchically distributed non-intrusive agent aided distance relaying protection scheme to supervise Zone 3

A FRAMEWORK FOR ANALYZING COMBINED LOAD-CARRYING-CAPACITY OF PLUG-IN ELECTRIC VEHICLES AND SOLAR GENERATORS

Processing and characterization of nanometer sized copper sulfide particles

Journal of Vacuum Science & Technology A, 1999

ABSTRACT

Model Checking Bluespec Specified Hardware Designs

2007 Eighth International Workshop on Microprocessor Test and Verification, 2007

Abstract Using RTL (Register Transfer Level) models for the verification of complex hardware desi... more Abstract Using RTL (Register Transfer Level) models for the verification of complex hardware designs involves reducing the state space of designs using various abstraction techniques. In this paper, we propose faster and earlier verification of hardware designs at a level of abstraction above RTL. We consider a high-level (above RTL) hardware model that uses atomic rules to describe the behavior of a design, which can then be synthesized to RTL code. Bluespec System Verilog (BSV) is an example of such a high-level ...

Resource availability through rainwater harvesting influenced vegetation diversity and herbage yield in hillslope of Aravalli in India

Frontiers of Agriculture in China, 2010

Recent decline in biological diversity has stimulated the research on the effects of resource con... more Recent decline in biological diversity has stimulated the research on the effects of resource conservation on biodiversity and vice versa. We examined soil water and nutrients influenced by rainwater harvesting (RWH) in hillslope and its effects on herbage diversity and productivity at up (USP), middle (MSP) and lower position (LSP) in 75 plots, each of 700-m2 area laid in 20%

Agent Based Supervision of Zone 3 Relays to Prevent Hidden Failure Based Tripping

2010 First IEEE International Conference on Smart Grid Communications, 2010

In this paper, we propose a distributed agent based supervisory scheme to make Zone 3 relays robu... more In this paper, we propose a distributed agent based supervisory scheme to make Zone 3 relays robust to hidden failure induced tripping, facilitated by the communication network --soon to become an integral parts of the smart grid. Possible elimination of Zone 3 relays (remote backup protection) has been studied in the recent past and these remote backup relays have been adjudged to be essential for power system protection [23]. Even though Zone 3 relays are often overly sensitive to remote line overloading, and are known to cause unwarranted trips during cascading failure scenarios, they are prescribed as acceptable means for remote backup. Therefore, providing robustness to Zone 3 relays to minimize the risk of erroneous trips, especially when hidden failures [10, 1] make them vulnerable to over reaction, is an important problem. In our scheme, a synchronous grid is populated with agents at each relay, and an agent hierarchy is maintained in master/slave relationship. The communication established between relay agents decreases the probability of erroneous Zone 3 trips thereby preventing them from aggravating cascading failure scenarios, and reducing the probability of cascading blackouts. Unlike other agent based relay proposals, ours is a nonintrusive approach.

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Power system and communication network co-simulation for smart grid applications

ISGT 2011, 2011

The vision of a smart grid is predicated upon pervasive use of modern digital communication techn... more The vision of a smart grid is predicated upon pervasive use of modern digital communication techniques to today's power system. As wide area measurements and control techniques are being developed and deployed for a more resilient power system, the role of communication network is becoming prominent. Power system dynamics gets influenced by the communication delays in the network. Therefore, extensive integration of power system and its communication infrastructure mandates that the two systems are studied as a single distributed cyber-physical system. This paper proposes a power/network co-simulation framework which integrates power system dynamic simulator and network simulator together using an accurate synchronization mechanism. The accuracy is tunable based on the time-scale requirements of the phenomena being studied. This co-simulation can improve the practical investigation of smart grid and evaluate wide area measurement and control schemes. As a case study an agent-based remote backup relay system is simulated and validated on this cosimulation framework.

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GaN Growth by Plasma Assisted Reactive Evaporation

Complexity Analysis of Scheduling in CAOS-Based Synthesis

Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications, 2010

PARTICIPATORY RESEARCH: WILL THE KOEL HATCH THE CROW'S EGGS?

This paper describes an experiment in participatory research for sustainable development. The exp... more This paper describes an experiment in participatory research for sustainable development. The experiment relies upon certain crucial underlying assumptions. The traditional models of on-station development of technology and its transmission to farmers are no longer feasible, since high ecological variability demands niche-specific solutions. Local solutions developed by farmers themselves need to be identified and their scientific bases understood. The value-added

Polychrony for formal refinement-checking in a system-level design methodology

Third International Conference on Application of Concurrency to System Design, 2003. Proceedings., 2003

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