Robert Hundt

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Papers by Robert Hundt

Scalable high performance cross-module inlining

by Robert Hundt, Xinliang Li, and Shin-ming Liu

Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004., 2004

Performing inlining of routines across file boundaries is known to yield significant run-time per... more Performing inlining of routines across file boundaries is known to yield significant run-time performance improvements. In this paper, we present a scalable cross-module inlining framework that reduces the compiler&#x27;s memory footprint, file thrashing, and overall compile-time. Instead of using ...

Dynamic Instrumentation of C++ Applications on IA-64

ABSTRACT

Optimizing Google's warehouse scale computers: The NUMA experience

by Robert Hundt and R. Hagmann

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 2013

Abstract Due to the complexity and the massive scale of modern warehouse scale computers (WSCs), ... more Abstract Due to the complexity and the massive scale of modern warehouse scale computers (WSCs), it is challenging to quantify the performance impact of individual microarchitectural properties and the potential optimization benefits in the production environment. As a result of these challenges, there is currently a lack of understanding of the microarchitecture-workload interaction, leaving potentially significant performance on the table. This paper argues for a two-phase performance analysis methodology for ...

JSWhiz: Static analysis for JavaScript memory leaks

Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2013

ABSTRACT JavaScript is the dominant language for implementing dynamic web pages in browsers. Even... more ABSTRACT JavaScript is the dominant language for implementing dynamic web pages in browsers. Even though it is standardized, many browsers implement language and browser bindings in different and incompatible ways. As a result, a plethora of web development frameworks were developed to hide cross-browser issues and to ease development of large web applications. An unwelcome side-effect of these frameworks is that they can introduce memory leaks, despite the fact that JavaScript is garbage collected. Memory bloat is a major issue for web applications, as it affects user perceived latency and may even prevent large web applications from running on devices with limited resources. In this paper we present JSWhiz, an extension to the open-source Closure JavaScript compiler. Based on experiences analyzing memory leaks in Gmail, JSWhiz detects five identified common problem patterns. JSWhiz found a total of 89 memory leaks across Google&#39;s Gmail, Docs, Spread-sheets, Books, and Closure itself. It contributed significantly in a recent effort to reduce Gmail memory footprint, which resulted in bloat reduction of 75% at the 99th percentile, and by roughly 50% at the median.

Contention aware execution

Proceedings of the 8th annual IEEE/ ACM international symposium on Code generation and optimization - CGO '10, 2010

Cross-core application interference due to contention for shared on-chip and off-chip resources p... more Cross-core application interference due to contention for shared on-chip and off-chip resources pose a significant challenge to providing application level quality of service (QoS) guarantees on commodity multicore micro-architectures. Unexpected cross-core interference is especially problematic when considering latencysensitive applications that are present in the web service data center application domains, such as web-search. The commonly used solution is to simply disallow the co-location of latency-sensitive applications and throughput-oriented batch applications on a single chip, leaving much of the processing capabilities of multicore micro-architectures underutilized. In this work we present a Contention Aware Execution Runtime (CAER) environment that provides a lightweight runtime solution that minimizes crosscore interference due to contention, while maximizing utilization. CAER leverages the ubiquitous performance monitoring capabilities present in current multicore processors to infer and respond to contention and requires no added hardware support. We present the design and implementation of the CAER environment, two separate contention detection heuristics, and approaches to respond to contention online. We evaluate our solution using the SPEC2006 benchmark suite. Our experiments show that when allowing colocation with CAER, as opposed to disallowing co-location, we are able to increase the utilization of the multicore CPU by 58% on average. Meanwhile CAER brings the overhead due to allowing co-location from 17% down to just 4% on average.

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Scenario Based Optimization: A Framework for Statically Enabling Online Optimizations

2009 International Symposium on Code Generation and Optimization, 2009

AbstractOnline optimization allows the continuous re-structuring and adaptation of an executing ... more

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MAO — An extensible micro-architectural optimizer

International Symposium on Code Generation and Optimization (CGO 2011), 2011

Performance matters, and so does repeatability and predictability. Today's processors' micro-arch... more Performance matters, and so does repeatability and predictability. Today's processors' micro-architectures have become so complex as to now contain many undocumented, not understood, and even puzzling performance cliffs. Small changes in the instruction stream, such as the insertion of a single NOP instruction, can lead to significant performance deltas, with the effect of exposing compiler and performance optimization efforts to perceived unwanted randomness. This paper presents MAO, an extensible micro-architectural assembly to assembly optimizer, which seeks to address this problem for x86/64 processors. In essence, MAO is a thin wrapper around a common open source assembler infrastructure. It offers basic operations, such as creation or modification of instructions, simple data-flow analysis, and advanced infra-structure, such as loop recognition, and a repeated relaxation algorithm to compute instruction addresses and lengths. This infrastructure enables a plethora of passes for pattern matching, alignment specific optimizations, peep-holes, experiments (such as random insertion of NOPs), and fast prototyping of more sophisticated optimizations. MAO can be integrated into any compiler that emits assembly code, or can be used standalone. MAO can be used to discover micro-architectural details semi-automatically. Initial performance results are encouraging.

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Lightweight feedback-directed cross-module optimization

by Robert Hundt and Raksit Ashok

Proceedings of the 8th annual IEEE/ ACM international symposium on Code generation and optimization - CGO '10, 2010

Page 1. Lightweight Feedback-Directed Cross-Module Optimization Xinliang DavidLi, Raksit Ashok, R... more

Heterogeneity in “Homogeneous” Warehouse-Scale Computers: A Performance Opportunity

IEEE Computer Architecture Letters, 2011

The class of modern datacenters recently coined as "warehouse scale computers" (WSCs) has traditi... more The class of modern datacenters recently coined as "warehouse scale computers" (WSCs) has traditionally been embraced as homogeneous computing platforms. However, due to frequent machine replacements and upgrades, modern WSCs are in fact composed of diverse commodity microarchitectures and machine configurations. Yet, current WSCs are designed with an assumption of homogeneity, leaving a potentially significant performance opportunity unexplored. In this paper, we investigate the key factors impacting the available heterogeneity in modern WSCs, and the benefit of exploiting this heterogeneity to maximize overall performance. We also introduce a new metric, opportunity factor, which can be used to quantify an application's sensitivity to the heterogeneity in a given WSC. For applications that are sensitive to heterogeneity, we observe a performance improvement of up to 70% when employing our approach. In a WSC composed of state-of-the-art machines, we can improve the overall performance of the entire datacenter by 16% over the status quo.

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Structure Layout Optimization for Multithreaded Programs

International Symposium on Code Generation and Optimization (CGO'07), 2007

Structure layout optimizations seek to improve runtime performance by improving data locality and... more Structure layout optimizations seek to improve runtime performance by improving data locality and reuse. The structure layout heuristics for single-threaded benchmarks differ from those for multi-threaded applications running on multiprocessor machines, where the effects of false sharing need to be taken into account. In this paper we propose a technique for structure layout transformations for multithreaded applications that optimizes both

Whole-program optimization of global variable layout

Proceedings of the 15th international conference on Parallel architectures and compilation techniques - PACT '06, 2006

On machines with high-performance processors, the memory system continues to be a performance bot... more On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve locality, but increasingly seek to modify an application's data layout to reduce cache miss and page fault penalties. In this paper we discuss Global Variable Layout (GVL), an optimization of the placement of entire static global data objects in the binary. We describe two practical methods for GVL in the HP-UX Integrity optimizing compiler for the Itanium c architecture. The first layout strategy relies on profile feedback, collaboratively employing the compiler, the linker and a pre-link tool to facilitate reordering. The second strategy uses whole-program analysis to drive data layout decisions, and does not require the use of a dynamic profile. We give a detailed description of our implementation and evaluate its performance for the SPEC integer benchmark programs, as well as for a large commercial database application.

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SYZYGY - A Framework for Scalable Cross-Module IPO

by Xinliang Li, Robert Hundt, U. Srinivasan, and Shin-ming Liu

International Symposium on Code Generation and Optimization, 2004. CGO 2004., 2004

Performing analysis across module boundaries for an entire program is important for exploiting se... more Performing analysis across module boundaries for an entire program is important for exploiting several runtime performance opportunities. However, due to scalability problems in existing full-program analysis frameworks, such performance opportunities are only realized by paying tremendous compile-time costs. Alternative solutions, such as partial compilations or user assertions, are complicated or unsafe and as a result, not many commercial applications are compiled today with cross-module optimizations.

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Bubble-Up

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11, 2011

As much of the world's computing continues to move into the cloud, the overprovisioning of comput... more As much of the world's computing continues to move into the cloud, the overprovisioning of computing resources to ensure the performance isolation of latency-sensitive tasks, such as web search, in modern datacenters is a major contributor to low machine utilization. Being unable to accurately predict performance degradation due to contention for shared resources on multicore systems has led to the heavy handed approach of simply disallowing the co-location of high-priority, latency-sensitive tasks with other tasks. Performing this precise prediction has been a challenging and unsolved problem.

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Practical Structure Layout Optimization and Advice

Symposium on Code Generation and Optimization, 2006

With the delta between processor clock frequency and memory latency ever increasing and with the ... more With the delta between processor clock frequency and memory latency ever increasing and with the standard locality improving transformations maturing, compilers increasingly seek to modify an application's data layout to improve spatial and temporal locality and to reduce cache miss and page fault penalties. In this paper, we describe a practical implementation of the data layout optimizations structure splitting, structure

Taming Hardware Event Samples for Precise and Versatile Feedback Directed Optimizations

by Robert Hundt, Stephane Eranian, and Xinliang Li

IEEE Transactions on Computers, 2000

Abstract Feedback-directed optimization (FDO) is effective in improving application performance, ... more Abstract Feedback-directed optimization (FDO) is effective in improving application performance, but has not been widely adopted due to the tedious dual-compilation model, the difficulties in generating representative training data sets, and the high runtime overhead of profile collection. The use of hardware-event sampling to generate estimated execution profiles overcomes these drawbacks. Yet, hardware event samples are typically not precise at the instruction or basic-block granularity. These inaccuracies lead to missed ...

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Increasing Utilization in Modern Warehouse-Scale Computers Using Bubble-Up

IEEE Micro, 2000

Precisely predicting performance degradation due to colocating multiple executing applications on... more Precisely predicting performance degradation due to colocating multiple executing applications on a single machine is critical for improving utilization in modern warehouse-scale computers (WSCs). Bubble-Up is the first mechanism for such precise prediction. As opposed to over-provisioning machines, Bubble-Up enables the safe colocation of multiple workloads on a single machine for Web service applications that have quality of service constraints,

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Google-Wide Profiling: A Continuous Profiling Infrastructure for Data Centers

by Robert Hundt and Yixin Shi

IEEE Micro, 2000

Google-Wide Profiling (GWP), a continuous profiling infrastructure for data centers, provides per... more Google-Wide Profiling (GWP), a continuous profiling infrastructure for data centers, provides performance insights for cloud applications. With negligible overhead, GWP provides stable, accurate profiles and a datacenter-scale tool for traditional performance analyses. Furthermore, GWP introduces novel applications of its profiles, such as application-platform affinity measurements and identification of platform-specific, microarchitectural peculiarities.

Feedback-directed optimizations with estimated edge profiles from hardware event sampling

Traditional feedback-directed optimization (FDO) uses static instrumentation to collect profiles.... more Traditional feedback-directed optimization (FDO) uses static instrumentation to collect profiles. This method has shown good application performance gains, but is not commonly used in practice due to the high runtime overhead of profile collection, the tedious dual-compile usage model, and difficulties in generating representative training data sets. In this paper, we show that edge frequency estimates can be successfully constructed with heuristics using profile data collected by sampling of hardware events, incurring low runtime overhead (e.g., less then 2%), and requiring no instrumentation, yet achieving competetive performance gains. Our initial results show a 3-4% performance gain on the SPEC C benchmarks.

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RACEZ: a lightweight and non-invasive race detection tool for production applications

by Robert Hundt and Stephane Eranian

Concurrency bugs, particularly data races, are notoriously difficult to debug and are a significa... more Concurrency bugs, particularly data races, are notoriously difficult to debug and are a significant source of unreliability in multithreaded applications. Many tools to catch data races rely on program instrumentation to obtain memory instruction traces. Unfortunately, this instrumentation introduces significant runtime overhead, is extremely invasive, or has a limited domain of applicability making these tools unsuitable for many production systems. Consequently, these tools are typically used during application testing where many data ...

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The impact of memory subsystem resource sharing on datacenter applications

In this paper we study the impact of sharing memory resources on five Google datacenter applicati... more In this paper we study the impact of sharing memory resources on five Google datacenter applications: a web search engine, bigtable, content analyzer, image stitching, and protocol buffer. While prior work has found neither positive nor negative effects from cache sharing across the PARSEC benchmark suite, we find that across these datacenter applications, there is both a sizable benefit and

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