Navab Singh

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Papers by Navab Singh

Etch-hole design in encapsulation for better robustness

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC), 2014

This paper reports various etch-hole schemes based on the location and quantities of etch holes t... more This paper reports various etch-hole schemes based on the location and quantities of etch holes to improve robustness of the Thin Film Encapsulation (TFE). In order to achieve robust TFE, different etch hole mapping is performed on the cap layer and robustness of TFE was evaluated by measuring the height of the TFE using optical profiler measurement after sealing. For demonstrating the TFE, amorphous Si and AlN (or SiO2) were used as a sacrificial layer and the cap layer, respectively. Etching of a-Si sacrificial layer was performed with help of XeF2. Experimental result shows that the quantity of etch holes and their location on the cap layer influence the downward deformation of the TFE after sealing process. A uniformly distributed etch holes scheme is effective in controlling the stress of encapsulation which results in low downward deformation..

Robust Pop-Up Shape Encapsulation Using Dual-Sealing

by Srinivas Merugu and Navab Singh

Journal of Microelectromechanical Systems, 2014

ABSTRACT This letter presents pop-up-shaped (having a spherical top shape) thin film encapsulatio... more ABSTRACT This letter presents pop-up-shaped (having a spherical top shape) thin film encapsulation (TFE) using two-step sealing method. The first sealing step seals the etch holes in the cap layer, whereas the second step provides the shape. A pop-up shape with 2.4- (mu ) m upward deformation is demonstrated using a negative pressure difference between the two sealing layers—0.5- (mu ) m SiN at 1100 mTorr followed by 3- (mu ) mSiO2 at 390 mTorr on an aluminum nitride cap encapsulating 800- (mu ) m (times 800) - (mu ) m size cavities. Besides a deeper cavity, the pop-up shape has smaller downward deformation of the cap layer due to its sturdy design. The increase in the robustness of TFE with pop-up radius is verified through finite element method simulations and theoretical calculation. [2013-0341]

Cavity-enhanced sacrificial layer micromachining for faster release of thin film encapsulated MEMS

by Srinivas Merugu and Navab Singh

Journal of Micromechanics and Microengineering, 2015

ABSTRACT This paper reports a method for fast-release and safe-sealing of thin film encapsulation... more ABSTRACT This paper reports a method for fast-release and safe-sealing of thin film encapsulation (TFE) for packaging of piezoelectric MEMS devices fabricated on cavity-SOI wafers. For fast releasing of the TFE, MEMS device trenches and the cavity below them were utilized and this combination acted as etch channels. Etchant can attack the sacrificial layer from the bottom of the MEMS device as well as side-located channels. A side-located etch channel scheme was chosen to ensure safe-sealing without mass-loading. 120 µm × 120 µm sized encapsulation on top of the MEMS device with eight isolation trenches connected to the cavity was released in 25 min. This is twice as fast as the TFE fabricated on bulk wafer using a similar encapsulation scheme. This reduction in release time is a consequence of a prefabricated cavity underneath the device which allows the etchant to attack the sacrificial layer at multiple locations as etchant can pass from one isolation trench to another.

Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration

by Navab Singh and W. Kuzmicz

This paper introduces a new device architecture, which can be shared by a variety of different ty... more This paper introduces a new device architecture, which can be shared by a variety of different types of transistors including a new 3D junctionless N-channel and P-channel vertical slit FET (VeSFET). VeSFETs have two symmetrical independent gates that provide many new circuit level opportunities e.g. in energy conservation domain, unavailable otherwise. The key feature of the new architecture is its

Trap Layer Engineered Gate-All-Around Vertically Stacked Twin Si -Nanowire Nonvolatile Memory

2007 IEEE International Electron Devices Meeting, 2007

Trap layer engineered gate-all-around (GAA) silicon nanowire SONOS memory showing excellent devic... more Trap layer engineered gate-all-around (GAA) silicon nanowire SONOS memory showing excellent device performance is demonstrated for the first time. Nitride and silicon nanocrystal (Si-NC) has have been incorporated as the engineered charge trapping layer. Fast transient memory characteristic is shown owing to the nanowire channel structure. The device with embedded Si-NC achieves even faster higher memory speed and increased window, up to 3.2 V ΔV th shift for 1 μs and 6.25 V memory window. The nanowire based non-volatile SONOS memory is promising for the future high speed and low power NAND-type flash memory application.

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Microelectromechanically tunable multiband metamaterial with preserved isotropy

by Navab Singh and Lokesh Dhakar

Scientific Reports, 2015

We experimentally demonstrate a micromachined reconfigurable metamaterial with polarization indep... more We experimentally demonstrate a micromachined reconfigurable metamaterial with polarization independent characteristics for multiple resonances in terahertz spectral region. The metamaterial unit cell consists of eight out-of-plane deformable microcantilevers placed at each corner of an octagon ring. The octagon shaped unit cell geometry provides the desired rotational symmetry, while the out-of-plane movable cantilevers preserves the symmetry at different configurations of the metamaterial. The metamaterial is shown to provide polarization independent response for both electrical inductive-capacitive (eLC) resonance and dipolar resonance at all states of actuation. The proposed metamaterial has a switching range of 0.16 THz and 0.37 THz and a transmission intensity change of more than 0.2 and 0.7 for the eLC and dipolar resonances, respectively for both TE and TM modes. Further optimization of the metal layer thickness, provides an improvement of up to 80% modulation at 0.57 THz. The simultaneously tunable dual band isotropic metamaterial will enable the realization of high performance electro-optic devices that would facilitate numerous terahertz applications such as compressive terahertz imaging, miniaturized terahertz spectroscopy and next generation high speed wireless communication possible in the near future.

Novel low aspect-ratio Si nano-hemisphere array surface texture application to ultrathin film solar cells

2011 37th IEEE Photovoltaic Specialists Conference, 2011

Low aspect-ratio Si nano-hemisphere array surface texturing compatible to thin film based solar c... more Low aspect-ratio Si nano-hemisphere array surface texturing compatible to thin film based solar cells is studied systematically for performance improvement. The light reflection can be significantly suppressed through varying the nano-hemisphere dimensions due to the spatial effective refractive index modulation. Owing to the excellent light trapping and also the nature of low aspect ratio (critical for conformal deposition of electrodes and achieving low surface defects), a short circuit current density (J sc ) of 37.4 mA/cm 2 is realized, in distinct comparison with the J sc of 20.4 mA/cm 2 measured from the reference flat solar cells.

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Si Nanowire CMOS Transistors and Circuits by Top-Down Technology Approach

ECS Transactions, 2008

ABSTRACT

Impact of scaling on the performance and reliability degradation of metal-contacts in NEMS devices

2011 International Reliability Physics Symposium, 2011

Impact of Scaling on the Performance and Reliability ... Degradation of Metal-Contacts in NEMS De... more

CMOS compatible Ge/Si core/shell nanowire gate-all-around pMOSFET integrated with HfO<inf>2</inf>/TaN gate stack

2009 IEEE International Electron Devices Meeting (IEDM), 2009

Ge/Si core/shell gate-all-round nanowire pMOSFET integrated with HfO2/TaN gate stack is demonstra... more Ge/Si core/shell gate-all-round nanowire pMOSFET integrated with HfO2/TaN gate stack is demonstrated using fully CMOS compatible process. Devices with 100 nm gate length achieved high ION of ~946 ¿A/¿m at VG - VT = -0.7 V and VDS = -1 V and on/off ratio of 104 with decent subthreshold behavior. Significant improvement in hole mobility and ballistic efficiency is demonstrated

A new method to achieve RF linearity in SOI nanowire MOSFETs

by Ali Razavieh and Navab Singh

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, 2011

Our experiments show that linearity can be achieved if transistors are designed to operate in the... more Our experiments show that linearity can be achieved if transistors are designed to operate in the onedimensional ballistic transport regime in the quantum capacitance limit. We report third order intercept points (IIP3) of around -13dBm at maximum transconductance under these particular transport and device operation conditions, meeting the requirements for state-of-the-art mobile communication systems. The advantage of our approach becomes most apparent when normalizing the IIP3 values with power at maximum transconductance. Although, our results do not yet show an improvement over devices operating in the velocity saturation regime due to the presence of scattering, they provide compelling evidence for the potential of our approach. Our findings make our approach an excellent candidate for low power applications in the early stages of RF receivers when linearity is critical.

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Dopant-Segregated Ni-Silicide Schottky-Source/Drain CMOS on Strained-Si/SiGe Multiple Quantum-Well Channel on Bulk-Si

2006 European Solid-State Device Research Conference, 2006

The authors report for the first time a high performance Schottky-barrier S/D transistor with str... more The authors report for the first time a high performance Schottky-barrier S/D transistor with strained-Si/SiGe multiple-quantum-well channel (MQW-SBT). Through dopant-segregation at Ni-silicide/Si interface and utilizing the smaller bandgap of channel materials, Schottky-barrier height was modulated resulting in Phib (to electron) ~0.13eV in n-MOS and Phib (hole) ~0.086 eV in p-MOS. This enhanced modulation in MQW helps to achieve high IDs

P-i-n junction in silicon nanowires

2008 2nd IEEE International Nanoelectronics Conference, 2008

P-i-n junctions were fabricated along silicon nanowires of about 8 nm in cross-sectional dimensio... more P-i-n junctions were fabricated along silicon nanowires of about 8 nm in cross-sectional dimension via the conventional top-down approach. Rectifying electrical characteristics have been observed and the ideality factor is estimated to be 3.8, attributed to trapped charges in the encapsulating silicon dioxide layer. Dopants diffusion along the nanowires reduces the effective length of the intrinsic region. The reverse bias

A FinFET and Tri-gate MOSFET's channel structure patterning and its influence on the device performance

Thin Solid Films, 2004

A simple and manufacturing worthy method to pattern a very thin channel body of the FinFET/Tri-ga... more A simple and manufacturing worthy method to pattern a very thin channel body of the FinFET/Tri-gate MOSFET is presented. A channel body as thin as 40 nm using the phase-shift mask (PSM) technique with deep UV 248 nm lithography on UV 210 Shipley resist has been achieved, while having an inherently wider Source/Drain (S/D) extension region. The width of extension region was optimized using the Prolitho.3D lithography simulator for the exposure dose and reticle bias conditions. The device simulation of the wider S/D extension region performed using three-dimensional (3-D) Davinci device simulator shows the significant reduction in the S/D parasitic resistance. Furthermore, these patterns on photoresists like UV 210 provides the basis for the easy integration to the mainstream CMOS technology, hence the potential for manufacturability with higher device performance. D

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Magnetic antidot nanostructures: effect of lattice geometry

Nanotechnology, 2006

We investigate the effect of lattice geometry on the magnetic anisotropy and transport properties... more We investigate the effect of lattice geometry on the magnetic anisotropy and transport properties of Ni 80 Fe 20 antidot nanostructures. The structures were fabricated using deep ultra-violet lithography at 248 nm exposure wavelength. For an antidot array with a square lattice, a fourfold magnetic anisotropy with alternating hard axis and easy axis every 45 • was observed. The honeycomb and rhomboid antidot lattice, however, both show a sixfold anisotropy, conforming well to the symmetry of their respective lattices. The magnetic hysteresis and micromagnetic simulation of the spin states at remanence show that the magnetization reversal process is very sensitive to the lattice arrangement of the holes. From the magnetotransport measurements, both the current density distribution and the magnetoresistance behaviour are markedly dependent on the antidot lattice geometry, in agreement with our transport simulations.

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Fabrication of large area nanomagnets

Nanotechnology, 2004

ABSTRACT We have developed a large area technique for fabricating magnetic nanostructures. This t... more ABSTRACT We have developed a large area technique for fabricating magnetic nanostructures. This technique is based on deep ultraviolet lithography followed by a lift-off process. A phase shift mask is used to create nanoscale patterns of very high density. By varying the focus and exposure doses we have synthesized multiple patterns using the same mask. Arrays of Ni80Fe20 nanostructures of different shapes and sizes were fabricated using this technique. Scanning electron microscopy was used to verify the lateral dimensions and uniformity of the structures. We have used a vibrating sample magnetometer to characterize the magnetic properties of the fabricated structures. We observed a marked increase in both the coercivity and the switching field of the patterned nanomagnets compared with the reference film due to the magnetic shape anisotropy.

DNA Sensing by Silicon Nanowire: Charge Layer Distance Dependence

by Navab Singh and E. Wong

Nano Letters, 2008

To provide a comprehensive understanding of the field effect in silicon nanowire (SiNW) sensors, ... more To provide a comprehensive understanding of the field effect in silicon nanowire (SiNW) sensors, we take a systematic approach to fine tune the distance of a charge layer by controlling the hybridization sites of DNA to the SiNW preimmobilized with peptide nucleic acid (PNA) capture probes. Six target DNAs of the same length, but differentiated successively by three bases in the complementary segment, are hybridized to the PNA. Fluorescent images show that the hybridization occurs exclusively on the SiNW surface between the target DNAs and the PNA. However, the field-effect response of the SiNW sensor decreases as the DNA (charge layer) moves away from the SiNW surface. Theoretical analysis shows that the field effect of the SiNW sensor relies primarily on the location of the charge layer. A maximum of 102% change in resistance is estimated based on the shortest distance of the DNA charge layer (4.7 A) to the SiNW surface.

Utilizing the Unique Properties of Nanowire MOSFETs for RF Applications

Nano Letters, 2013

Nanostructures have attracted a great deal of attention because of their potential usefulness for... more Nanostructures have attracted a great deal of attention because of their potential usefulness for high density applications. More importantly, they offer excellent avenues for improved scaling beyond conventional approaches. Less attention has been paid to their intrinsic potential for distinct circuit applications. Here we discuss how a combination of 1-D transport, operation in the quantum capacitance limit, and ballistic transport can be utilized for certain RF applications. In particular this work explores how the above transport properties can provide a high degree of transconductance linearity at the device level. The article also discusses how device characteristics can be interpreted and analyzed in terms of device linearity if the above conditions are not ideally fulfilled. Using aggressively scaled silicon nanowire field-effect transistors as an example device in this work provides new insights toward the proper choice of channel material to improve linearity through the above-mentioned transport conditions. According to this study, a high degree of linearity occurs feasible while operating at low supply voltages making low-dimensional systems, and here in particular nanowires, an interesting candidate for portable RF applications. I n recent years, the rapid transition of the communication systems toward wireless technologies resulted in operation of numerous standards within a small frequency window. More traffic, in adjacent frequency ranges, requires complex circuit and system level linearization techniques to prevent intermodulation and harmonic distortion. 1−5 These constraints turn more focus toward the improvement of linearity at the device level. 6−12 If high transconductance can be achieved in a fieldeffect transistor, which offers high linearity at the same time, simpler circuit design solutions and lower power consumption are achievable at the same performance specs. This is in line with goals for future generations of wireless and mobile communication systems in which high linearity performance and low power consumption are the key requirements. Recently we discussed the possibility of employing nanostructures to achieve improved linearity in devices with small transconductance variations in the on-state. 13 If three criteria: (i) operation in the quantum capacitance limit (QCL), (ii) onedimensional (1-D) transport, and (iii) operation in the ballistic transport regime are met, a FET will exhibit ideal linear I d −V ds characteristics with a constant transconductance which is independent of the actual choice of channel material when operated under high enough drain voltage conditions. These three conditions ensure that: (i) both the conduction and valence band in the gated region of the device follow the applied gate voltage one-to-one (1:1) even in the on-state of the device. Different from a conventional metal−oxide− semiconductor field-effect transistor (MOSFET) where the entire voltage drop is assumed to occur across the gate oxide above threshold, operation in the QCL implies that the gate

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Effect of dipolar interaction on the magnetization state of chains of rectangular particles located either head-to-tail or side-by-side

by Navab Singh and D. Bisero

Journal of Nanoparticle Research, 2011

Magnetostatic coupling in arrays of closely spaced magnetic elements is becoming an important iss... more Magnetostatic coupling in arrays of closely spaced magnetic elements is becoming an important issue in the path to the fabrication of spintronic devices. Dense chains of rounded-corners rectangular particles (dots) of lateral size 1025 9 450 nm 2 , with interdot spacing variable in the range between 55 and 700 nm, have been patterned by deep UV lithography, followed by the lift-off of two permalloy films of thickness 20 and 40 nm. Magneto-optical Kerr effect (MOKE) and magnetic force microscopy (MFM) experiments, together with micromagnetic simulations, were performed to study the dependence of the magnetization configuration on the dipolar coupling. Both MOKE measurements and MFM images clearly show that, at remanence, the magnetic state of isolated particles of thickness 20 nm takes the form of a distorted single domain (C-state or S-State configurations). Instead, when the particle thickness is double (40 nm), closure states characterized by one, two or three vortices occur at remanence. However, when the 40 nm thick dots are placed in chains along the easy axis (head to tail), as the separation is progressively reduced, the single domain state is stabilized at remanence. On the other hand, when the 40 nm thick particles are placed side by side in chains the effect of dipolar interactions is to favour the nucleation of vortex states. For small inter-element separation, there is only one vortex per particle and it has the same chirality in adjacent particles, due to the dipolar interaction. Different from this, for the 20 nm thick samples and sub-100 nm separation, adjacent particles are single-domain but with antiparallel magnetization in neighbour elements, like in an artificial antiferromagnet.

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Propagating volume and localized spin wave modes on a lattice of circular magnetic antidots

Journal of Applied Physics, 2008

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