Communication — The Role of the Metal-Semiconductor Junction in Pt-Assisted Photochemical Etching of Silicon Carbide
Porous 4H-SiC layers were fabricated by photochemical etching of n-type 4H-SiC samples with varyi... more Porous 4H-SiC layers were fabricated by photochemical etching of n-type 4H-SiC samples with varying resistivity. An etching solution of Na2S2O8 and HF was used while Pt deposited at the 4H-SiC surface served as catalyst for the reduction of Na2S2O8. The contact resistance at the Pt/4H-SiC junction was decreased by annealing and surface near phosphorous doping. This enabled the porosification of 4H-SiC with photochemical etching
Photoelectrochemical porosification of silicon carbide for MEMS
In dieser Arbeit wurden Metall-unterstütztes photochemisches Ätzen (engl. metal assisted photoche... more In dieser Arbeit wurden Metall-unterstütztes photochemisches Ätzen (engl. metal assisted photochemical etching – MAPCE) und photoelektrochemisches Ätzen (engl. photoelectrochemical etching – PECE) von Siliciumcarbid (SiC) mit Hinblick auf mögliche Anwendungen in Mikrosystemen (engl. microelectromechanical system - MEMS) untersucht. Es stellte sich heraus, dass MAPCE sich gut eignet, um poröse Dünnfilme mit Schichtdicken bis zu 2 μm herzustellen, während mit PECE bis zu 30 μm dicke poröse Schichten realisiert werden konnten. Weiters war es möglich mit MAPCE poröse Anti-Reflexions-Beschichtungen und homogen poröse Schichten auf 4H-SiC Substraten zu erzeugen, die Reflexionseigenschaften wie Dünnfilme zeigen. Erstere könnten in LEDs oder UV-Sensoren eingesetzt werden, wobei letztere eine mögliche Anwendung in optischen Sensoren haben, die auf einer Änderung der Reflexion beruhen, wenn die Poren mit z.B. gasförmigem oder flüssigem Medium befüllt werden. Ladungs-kontrolliertes PECE erlaub...
Nanoporous materials represent a versatile solution for a number of applications ranging from sen... more Nanoporous materials represent a versatile solution for a number of applications ranging from sensing, energy applications, catalysis, drug delivery, and many others. The synergy between the outstanding properties of graphene with a three-dimensional porous structure, circumventing the limits of its 2D nature, constitutes therefore a breakthrough for many fields. We report the first three-dimensional growth of epitaxial graphene on a porousified crystalline 4H-SiC(0001). The wafer porosification is performed via a sequence of metal-assisted photochemical and photoelectrochemical etching in hydrofluoric acid based electrolytes. Pore dimensions of the matrix have been evaluated by electron tomography resulting in an average diameter of 180 nm. Graphene growth is performed in an ultra high vacuum environment at a base pressure of 10 −11 mbar. The graphene growth inside the pores is uniform as confirmed by Transmission Electron Microscopy (TEM) analysis. Raman spectroscopy confirms the high quality of the graphene with a 2D/G ratio > 1 and an average graphene crystal size of ≈ 100 nm. Furthermore, it demonstrates a uniform coverage of graphene across the whole sample area. The surface-to-volume ratio of this novel material, its properties, the tunability of the pore size and the scalability of the surface porosification process offer a game changing perspective for a large number of applications.
Communication—Current Oscillations in Photoelectrochemical Etching of Monocrystalline 4H Silicon Carbide
ECS Journal of Solid State Science and Technology, 2021
Photoelectrochemical etching of monocrystalline 4H silicon carbide was performed under constant v... more Photoelectrochemical etching of monocrystalline 4H silicon carbide was performed under constant voltage condition. For the first time current oscillations were observed that caused a periodic modulation of the resulting pore diameter in etching direction. The period length of the pore diameter variation could be estimated to be about 20 nm. Additionally, it was observed that the assembly of the pores in a top down view is a Turing pattern.
Procédé et système de réalisation d'un objet en forme de plaque, contenant en particulier une pluralité d'éléments de circuit imprimé
L'invention concerne un procede et un systeme de realisation d'un objet en forme de plaqu... more L'invention concerne un procede et un systeme de realisation d'un objet en forme de plaque (6), contenant ou recevant en particulier une pluralite d'elements de circuit imprime (1, 2, 3, 4), dans lesquels un element de circuit imprime (1, 2, 3, 4) est insere dans un evidement (1', 2', 3', 4') correspondant. Dans le cadre dudit procede, il est prevu de mesurer au moins une zone partielle du profil de l'element de circuit imprime (1, 2, 3, 4) a inserer ou du profil de l'evidement (1', 2', 3', 4') menage dans l'objet en forme de plaque (6), de realiser le profil de l'autre element de circuit imprime (1, 2, 3, 4) a inserer ou de l'evidement (1', 2', 3', 4') de l'objet en forme de plaque (6) en l'adaptant au profil deja mesure de l'autre element de circuit imprime (1, 2, 3, 4) a inserer ou de l'evidement (1', 2', 3', 4') de l'objet en forme de plaque (6) et de monter l'...
Verfahren zum herstellen, insbesondere bearbeiten oder bestücken, eines leiterplattenelements sowie träger zur verwendung in einem derartigen verfahren
Bei einem Verfahren zum Herstellen, insbesondere Bearbeiten oder Bestucken eines Leiterplattenele... more Bei einem Verfahren zum Herstellen, insbesondere Bearbeiten oder Bestucken eines Leiterplattenelements, sind die folgenden Schritte vorgesehen: - Bereitstellen eines im wesentlichen vollflachigen Tragers (1) mit einer haftenden Oberflache (6), - Anordnen und Festlegen eines Ausgangsmaterials des herzustellenden, insbesondere zu bearbeitenden oder zu bestuckenden Leiterplattenelements (2, 3, 4, 5) auf der haftenden Oberflache (6) des Tragers (1), - Herstellen, insbesondere Bearbeiten oder Bestucken, des auf dem Trager festgelegten Leiterplattenelements (2, 3, 4, 5) in auf dem Trager (1) festgelegter Lage, und - Entfernen des hergestellten, insbesondere bearbeiteten oder bestuckten Leiterplattenelements (2, 3, 4, 5) von dem Trager (1). Daruber hinaus wird ein Trager (1) zur Verwendung in einem derartigen Verfahren zur Verfugung gestellt, wobei insbesondere auf aufwendige Trenn- bzw. Vereinzelungsschritte von Leiterplattenelementen (2, 3, 4, 5) verzichtet werden kann und unter Schonung...
Procédé de fabrication de carte à circuits imprimés multicouche, matériau anti-adhésion, carte à circuits imprimés multicouche, et utilisation d'un tel procédé
La presente invention concerne un procede de fabrication d'une carte a circuits imprimes cons... more La presente invention concerne un procede de fabrication d'une carte a circuits imprimes constituee d'une pluralite de couches ou d'epaisseurs, conductrices ou electroconductrices, ainsi que non-conductrices ou isolantes, pressees les unes contre les autres. En l'occurrence, apres etablissement de liaison entre des couches au moins partiellement planes, on retire au moins une partie delimitee (11) de ces couches, et pour empecher l'adherence de la partie delimitee a enlever (11), on applique sur une couche (9) jouxtant la partie delimitee a enlever un materiau anti-adhesion (8) correspondant a ladite partie delimitee a enlever (11). A cet effet, le materiau anti-adhesion (8) utilise est un melange d'agent demoulant, de liant, et de solvant, l'agent demoulant etant constitue d'au moins un savon metallique, de preference des sels d'acides gras de Al, Mg, Ca, Na et Zn. L'invention permet ainsi, apres les etapes de traitement concernees d'une ...
Embedding known-good component in known-good cavity of known-good component carrier material with pre-formed electric connection structure
A method of manufacturing a component carrier (100), wherein the method comprises providing a kno... more A method of manufacturing a component carrier (100), wherein the method comprises providing a known-good layer stack (102) comprising an already formed electrically conductive connection structure (104) and a known-good cavity (106), and mounting a known-good component (108) on the already formed electrically conductive connection structure (104) in the cavity (106).
Matière inhibitrice d'adhérence, procédé pour enlever une portion d'une couche de matière plane, structure multicouche et leur utilisation
L'invention concerne une matiere inhibitrice d'adherence mise en oeuvre pour l'enleve... more L'invention concerne une matiere inhibitrice d'adherence mise en oeuvre pour l'enlevement d'une portion (11) d'une couche de matiere pratiquement plane (2) qui est reliee lors d'un processus d'assemblage a au moins une autre couche de matiere pratiquement plane (9). Selon l'invention, la matiere inhibitrice d'adherence (8) presente une difference de polarite par rapport aux couches de matiere pratiquement planes adjacentes (2, 9). L'invention concerne egalement un procede servant a enlever une portion (11) d'une couche de matiere pratiquement plane (2) qui est reliee lors d'un processus d'assemblage a au moins une autre couche de matiere pratiquement plane (9), une structure multicouche constituee d'au moins deux couches de matiere pratiquement planes (2, 9) a relier entre elles, ainsi que leur utilisation notamment en liaison avec la production d'une carte imprimee multicouche.
Verfahren zur integration eines elektronischen bauteils in eine leiterplatte sowie leiterplatte mit einem darin integrierten elektronischen bauteil
Bei einem Verfahren zur Integration eines Bauteils (3) in eine Leiterplatte sind folgende Schritt... more Bei einem Verfahren zur Integration eines Bauteils (3) in eine Leiterplatte sind folgende Schritte vorgesehen: - Bereitstellen von zwei fertig gestellten, und insbesondere aus einer Mehrzahl von miteinander verbundenen Lagen bzw. Schichten (6, 7, 8) bestehenden Leiterplattenelementen (1, 4), wobei wenigstens ein Leiterplattenelement (4) eine Ausnehmung bzw. Vertiefung (10) aufweist, - Anordnen des zu integrierenden Bauteils (3) auf einem der Leiterplattenelemente (1) oder in der Ausnehmung des wenigstens einen Leiterplattenelements, und - Verbinden der Leiterplattenelemente (1, 4) unter Aufnahme des Bauteils (3) in der Ausnehmung (10), wodurch eine sichere und zuverlassige Aufnahme eines Bauteils bzw. Sensors (3) in einer Leiterplatte erzielbar ist. Daruber hinaus wird eine derartige Leiterplatte mit einem darin integrierten elektronischen Bauteil (3) zur Verfugung gestellt.
In this paper the pore formation process during metal assisted photochemical etching (MAPCE) of 4... more In this paper the pore formation process during metal assisted photochemical etching (MAPCE) of 4H silicon carbide (SiC) is investigated. By utilizing cellular automaton simulations, it was found, that MAPCE can be described by time-stochastic effects as long as the etching rate is constant. When this is not the case, other effects such as the growth of already existing pores dominate, and the probability of new pore formation decreases. These findings implied that porous SiC generated with MAPCE can most beneficially be used as anti-reflective coating or as integrated filter element in optical sensor applications.
In preliminary studies it could be shown that single crystalline silicon carbide wafers can be po... more In preliminary studies it could be shown that single crystalline silicon carbide wafers can be porosified with metal assisted photochemical etching. Furthermore, the generation of porous areas which are locally defined is possible with this method. By adjusting the etching parameters, a highly porous layer (degree of porosity of 90%) can be formed which is under-etched by a line of breakage. By depositing a compressively stressed amorphous SiC:H thin film on top of a porous region, the a-SiC:H film can be locally separated from the substrate, resulting in a buckled membrane configuration. Such membranes might open up potential applications in MEMS design concepts.
The presented work shows a study of the boundary condition between metal and silicon, in metal as... more The presented work shows a study of the boundary condition between metal and silicon, in metal assisted chemical etching. This is achieved by varying silicon doping type and concentration as well as metal type and oxidation agent concentration. First, the etch rate dependence of silver particles, on n-and on p-doped samples is investigated revealing different etch rates depending on doping concentration. Additional experiments using an etch solution containing no oxidation agent show an impact of the metal-semiconductor combination on the etch process. In this case the higher work function of Pt particles compared to Ag leads to an etching independent of silicon doping.
Metal assisted photochemical etching (MAPCE) of 4H–silicon carbide (SiC) in Na2S2O8/HF and H2O2/H... more Metal assisted photochemical etching (MAPCE) of 4H–silicon carbide (SiC) in Na2S2O8/HF and H2O2/HF aqueous solutions is investigated with platinum as metallic cathode. The formation process of the resulting porous layer is studied with respect to etching time, concentration and type of oxidizing agent. From the experiments it is concluded that the porous layer formation is due to electron hole pairs generated in the semiconductor, which stem from UV light irradiation. The generated holes are consumed during the oxidation of 4H–SiC and the formed oxide is dissolved by HF. To maintain charge balance, the oxidizing agent has to take up electrons at the Pt/etching solution interface. Total dissolution of the porous layers is achieved when the oxidizing agent concentration decreases during MAPCE. In combination with standard photolithography, the definition of porous regions is possible. Furthermore chemical micromachining of 4 H–SiC at room temperature is possible.
Metal assisted photochemical etching (MAPCE) of 4H Silicon Carbide (SiC) was utilized to generate... more Metal assisted photochemical etching (MAPCE) of 4H Silicon Carbide (SiC) was utilized to generate locally defined porous areas on single crystalline substrates. Therefore, Platinum (Pt) was sputter deposited on 4H-SiC substrates and patterned with photolithography and lift off. Etching was performed by immersing the Pt coated samples into an etching solution containing sodium persulphate and hydrofluoric acid. UV light irradiation was necessary for charge carrier generation while the Pt served as local cathode. The generated porous areas can be used for the generation of integrated cavities in the single crystalline SiC substrates when covered with a chemical vapor deposited thin film of poly-crystalline SiC.
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