Jim Jeffers

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Papers by Jim Jeffers

System and Method for Dynamically Configured, Asymmetric Endpoint Video Exchange

Image Insertion in Video Streams Using a Combination of Physical Sensors and Pattern Recognition

System and method for real time insertion into video with occlusion on areas containing multiple colors

High Performance Parallelism Pearls

インテルXeon Phiコプロセッサーハイパフォーマンス・プログラミング

High Performance Parallelism Pearls Volume Two: Multicore and Many-core Programming Approaches

High Performance Parallelism Pearls Volume 2 offers another set of examples that demonstrate how ... more High Performance Parallelism Pearls Volume 2 offers another set of examples that demonstrate how to leverage parallelism. Similar to Volume 1, the techniques included here explain how to use processors and coprocessors with the same programming illustrating the most effective ways to combine Xeon Phi coprocessors with Xeon and other multicore processors. The book includes examples of successful programming efforts, drawn from across industries and domains such as biomed, genetics, finance, manufacturing, imaging, and more. Each chapter in this edited work includes detailed explanations of the programming techniques used, while showing high performance results on both Intel Xeon Phi coprocessors and multicore processors. Learn from dozens of new examples and case studies illustrating "success stories" demonstrating not just the features of Xeon-powered systems, but also how to leverage parallelism across these heterogeneous systems. Promotes write-once, run-anywhere coding,...

Optimizing classical molecular dynamics in LAMMPS

Intel Xeon Phi Processor High Performance Programming, 2016

LAMMPS results on Knights Landing are discussed. Significant performance improvements on Intel Xe... more LAMMPS results on Knights Landing are discussed. Significant performance improvements on Intel Xeon processors and Knights Landing many-core processors are discussed. The simulations on single-socket Knights Landing processors were up to 1.96 × faster than dual socket Intel Xeon processors in configurations with a significantly lower processor TDP.

Intel Omni-Path Fabric

Intel Xeon Phi Processor High Performance Programming, 2016

Details on the next generation fabric with heritage from the Intel® TrueScale product line and th... more

Tasks and threads

Intel Xeon Phi Processor High Performance Programming, 2016

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Μarch Optimization Advice

Intel Xeon Phi Processor High Performance Programming, 2016

Tuning advice that is specific to the Knights Landing design, which is known as the microarchitec... more Tuning advice that is specific to the Knights Landing design, which is known as the microarchitecture and is abbreviated as μarch. Focuses on tuning advice arising specifically from the Knights Landing μarch design when compared with the Knights Corner μarch (found in the first-generation Intel Xeon Phi products) or the μarch of a recent Intel® Xeon® processor.

Coprocessor System Software