Papers by Isabel Teixeira
This contribution describes the work carried out by the INESC team, in collaboration with LIP, in... more This contribution describes the work carried out by the INESC team, in collaboration with LIP, in order to increase testability features on the CMS ECAL upperlevel readout and trigger system. To accomplish this purpose, (1) extension of boundary scan test of electronic boards to system level, (2) introduction of self test in ASICs, (3) defect-oriented test effectiveness evaluation and ( ) system-level modeling and simulation have been addressed and are reported. This work is consistent with the one carried out by Politecnico di Torino and CAEN in collaboration with CERN, in order to improve testability and reliability of the upper-level readout and trigger system.
Foi analisada a performance de Zabrotes subfasciatus em temperaturas baixas, com ou sem alimento.... more Foi analisada a performance de Zabrotes subfasciatus em temperaturas baixas, com ou sem alimento. Usaram-se insetos recem-emergidos colocados em temperatura constante de 15oC (9 repeticoes). Notou-se que a longevidade foi bem maior em baixa temperatura do que nas consideradas ideais (26-29oC), porem a fecundidade foi bem menor (1,1 ovo/femea). Possivelmente, a baixa fecundidade esta relacionada a reabsorcao dos ovocitos permitindo maior longevidade aos adultos e a ingestao de carboidratos.
The work developed consists in a power or performance optimization methodology, for long-term ope... more The work developed consists in a power or performance optimization methodology, for long-term operation, using global and local aging aware performance sensors. Methodology allows circuits to be dynamically optimized, during their life-time, according with one of two possible needs: (1) restrict power consumption, by reducing power-supply voltage to the minimum value that prevents errors from happening; or (2) optimize performance, by increasing operating frequency to the maximum limit that prevents errors' occurrence. The dynamic optimization is achieved by using a cooperative work of global and local sensors. Moreover, new global sensor architecture, controller and a DCO (Digital Control Oscillator) are presented, to demonstrate frequency automatic optimization, according with sensors' outputs. Extensive spice simulations in a 65nm CMOS technology demonstrate the results.
Journal of Instrumentation, 2007
Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001
Product development economics and specs drive the need for on chip embedded test functionality. H... more Product development economics and specs drive the need for on chip embedded test functionality. However, optimal partitioning of test functionality between a tester and a SOC is a non-trivial task, which must be solved during the system analysis phase. Hence, at system level, a trade-off analysis must be performed, in order to evaluate the costs and benefits of different partitioning schemes. The purpose of this contribution is to present a methodology and tools, using the Object Oriented (OO) Paradigm and UML, and a set of architectural Quality Metrics (QMs), to analyze the impact of different TRP schemes on system's architecture. A 4-core SOC case study is presented to guide the discussion.
Design of Circuits and Integrated Systems, 2014
The work developed consists in an aging-aware dynamic voltage or frequency scaling methodology, t... more The work developed consists in an aging-aware dynamic voltage or frequency scaling methodology, to be used in long-term operation, using global and local performance sensors. Methodology allows circuits to be dynamically optimized, during their life-time, according with one of two possible needs: (1) restrict power consumption, by reducing power-supply voltage to the minimum value that prevents errors from happening; or (2) optimize performance, by increasing operating frequency to the maximum limit that prevents errors' occurrence. The dynamic optimization is achieved by using a cooperative work of global and local sensors. Moreover, a new local sensor is presented, to obtain an enhanced solution with additional tolerance to delayfaults, allowing to achieve higher improvement in power or frequency optimization, or to achieve a higher safety and control margin. Spice simulations in a 65nm CMOS technology demonstrate the results for an example of a dynamic frequency scaling strategy.
2003 Design, Automation and Test in Europe Conference and Exhibition
High quality Built-In Self Test (BIST) needs to efficiently tackle the coverage of random-pattern... more High quality Built-In Self Test (BIST) needs to efficiently tackle the coverage of random-pattern-resistant (r.p.r) defects. Several techniques have been proposed to cover r.p.r faults at logic level, namely, weighted pseudo-random and mixed-mode. In mixed-mode test pattern generation (TPG) techniques, deterministic tests are added to pseudorandom vectors to detect r.p.r. faults. Recently, a RTL mixed-mode TPG technique has been proposed to cover r.p.r defects, the mask-based BIST technique. The purpose of this paper is to present mask-based BIST TPG improvements, namely in two areas: RTL estimation of the test length to be used for each mask, in order to reach high Defects Coverage (DC), and the identification of an optimum mask for each set of nested RTL conditions. Results are used to predict the number of customized vectors for each mask of one ITC'99 benchmark module.
EFTA 2003. 2003 IEEE Conference on Emerging Technologies and Factory Automation. Proceedings (Cat. No.03TH8696)
Factory automation requires smart solutions, especially when a set of equipment, from different v... more Factory automation requires smart solutions, especially when a set of equipment, from different vendors, has to be interfaced to enable fast and flexible production. In this paper, a hardware /software (hw/sw) modeling approach and its implementation, in the electronic system, Fill, for the automation and real-time control of a wine bottling production line, is presented. Fill is a sub-system of an intelligent production line. Object Oriented concept is used for system modeling and development. The key novelty of the implementation approach is the use of the bottle, as an active object, for synchronizing the production line. A prototype of Fill has been implemented in an industrial environment, in the northern part of Portugal, boosting productivity. If the market makes it cost-effective, the hw/sw solution can be easily integrated and installed in other production lines and companies.
Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, 2007
As IC technology scales down, power supply instability may dramatically contribute to signal inte... more As IC technology scales down, power supply instability may dramatically contribute to signal integrity loss. In this paper, we propose a new methodology to enhance circuit tolerance to powersupply voltage (V DD ) local variations, without degrading its performance. The underlying idea is to add additional tolerance to the edge trigger of the clock signal driving specific memory cells. The clock duty-cycle (CDC) is thus dynamically modulated according to V DD . Two architectures are presented, and one of them is shown to be effective. The key module is a Clock Stretching Logic (CSL) block, used to increase CDC according to V DD -V SS variations. Moreover, when clock frequency reduction is inevitable, circuit tolerance when disturbances start to occur is enhanced, allowing the clock generator to react and reduce its frequency. Experimental results based on SPICE simulations for simple combinational, pipeline and finite-state machine (FSM) circuits are used to demonstrate the usefulness of the proposed methodology.
Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, 2010
Characterization of the clear-PEM breast imaging scanner performance
IEEE Nuclear Science Symposium Conference Record, 2009
We present results on the characterization of the Clear-PEM breast imaging scanner. Clear-PEM is ... more We present results on the characterization of the Clear-PEM breast imaging scanner. Clear-PEM is a dual-head Positron Emission Mammography scanner using APD-based detector modules that are capable of measuring depth-of-interaction (DOI) with a resolution of 2 mm in LYSO:Ce crystals. The full system comprises 192 detector modules in a total of 6144 LYSO:Ce crystals and 384 32-pixel APD arrays readout
Implementation of an ATCA/AXIe board for fast control and data acquisition systems of nuclear fusion devices
2012 18th IEEE-NPSS Real Time Conference, 2012
ABSTRACT The implementation of an ATCA/AXIe board, developed for fast control and data acquisitio... more ABSTRACT The implementation of an ATCA/AXIe board, developed for fast control and data acquisition systems of nuclear fusion devices, is presented. The implemented board was designed for systems requiring high levels of reliability and availability, such as those of long duration discharges or steady-state operation nuclear fusion experiments. Following ITER instrumentation guidelines for rear signals interfaces, the board comprises a passive rear transition module allowing analogue IO cabling connectivity and cable-less hop-swap maintenance of the front board. Onboard ADC modules have differential input, galvanic isolation and an ADC chopper circuit which assures offset compensation over time for integrators used on magnetic diagnostics. Classical clock and trigger synchronism as well as IEEE-1588/IRIG timing are supported. Full ATCA redundancy and management are also provided.
Design and evaluation of the clear-PEM detector for positron emission mammography
IEEE Symposium Conference Record Nuclear Science 2004.
The design and evaluation of the imaging system Clear-PEM for positron emission mammography, unde... more The design and evaluation of the imaging system Clear-PEM for positron emission mammography, under development by the PEM Consortium within the framework of the Crystal Clear Collaboration at CERN, is presented. The proposed apparatus is based on fast, segmented, high atomic number radiation sensors with depth-of-interaction measurement capabilities and state-of-the-art data acquisition techniques. The camera consists of two compact and
Proceedings IEEE European Test Workshop
Sensors and Actuators A: Physical, 2011
Environment protection is one of the most discussed topics today. Accordingly there is an increas... more Environment protection is one of the most discussed topics today. Accordingly there is an increase in research and production of sensormaterials, which could detect leakages, monitor air quality and also could be used in industry for process control. Sensormaterial described above need to be at least sensitive to organic solvent vapour exposure limits determined by NIOSHA or OSHA. In the same time sensormaterial have to maintain response repeatability. Our scientific group have produced PNCC with 4 mass parts of carbon black and tested it to toluene vapour concentration 754mg/m 3 (toluene TWA level). The composite electric resistance increased immediately with exposure to vapour. As reported previously the composite electric resistance increase is due to tunneling current existence in thin layers of matrix between carbon black nanoparticles aggregates. Composite samples have been prepared by solution mixing of polyisoprene and carbon black particles, which were prior to dispersed into chloroform by sonification. After that a definite number of mixed solution layers (6, 8 or 10) were coated onto substrate (epoxy resin) with embedded brass wires. In this paper we will describe how variation of the composite carbon black content (4, 5 and 6 mass parts) near the percolation threshold influence organic solvent vapour sensitivity and repeatability. [1] M. Knite, K. Ozols, G. Sakale, V. Teteris. Polyisoprene and high structure carbon nanoparticle composite for sensing organic solvent vapours. Sensors and Actuators B 126 (2007) 209-213.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996
Fusion Engineering and Design, 2013
This paper describes the implementation and test of a control and data acquisition board designed... more This paper describes the implementation and test of a control and data acquisition board designed to be integrated on systems demanding high availability and reliability, foreseen for future experiments like ITER or other long operation fusion devices. The Advanced Telecommunications Computing Architecture (ATCA) standard (PICMG 3.0 and 3.4) was selected for board implementation, which has support for the desired system robustness and performance. Some board features such as rear Input/Output (IO) signals connectivity (passive, copper tracks only), cable-less hot-swap maintenance, Intelligent Platform Management Controller (IPMC) and redundancy on timing signals, communications links and power supplies are significant board improvements, relatively to previous control and data acquisition boards, allowing the development of more reliable system architectures. Moreover, the developed board is also compatible with the emerging ATCA eXtensions for Instrumentation (AXIe) specifications, which provides additional timing and synchronization signals on the backplane. ATCA full-mesh, multi-gigabit, full-duplex, pointto-point communication links between Field Programmable Gate Arrays (FPGA), of peer boards inside the shelf, allow the implementation of distributed algorithms and development of Multi-Input Multi-Output (MIMO) systems. Up to 48 analog input channels, simultaneously digitized (2 MSPS @ 18-bits), are filtered/decimated by the board FPGA and sent to the ATCA/AXIe host through Peripheral Component Interconnect express (PCIe) using Direct Memory Access (DMA). In real-time, the host can update up to 48 analog output channels (1 MSPS @ 18-bits), per board, through PCIe. Further board characteristics comprise analog IO channels with galvanic isolation and an optional signal chopper mode, for offset compensation over time on digital integration of magnetic signals. Board time synchronization is attained by means of the Inter-Range Instrumentation Group (IRIG) time-code.
The European Physical Journal C, 2006
The amplitude of the signal collected from the PbWO 4 crystals of the CMS electromagnetic calorim... more The amplitude of the signal collected from the PbWO 4 crystals of the CMS electromagnetic calorimeter is reconstructed by a digital filtering technique. The amplitude reconstruction has been studied with test beam data recorded from a fully equipped barrel supermodule. Issues specific to data taken in the test beam are investigated, and the implementation of the method for CMS data taking is discussed.
As IC technology scales down, interconnect issues are becoming one of the major concerns of gigah... more As IC technology scales down, interconnect issues are becoming one of the major concerns of gigahertz Systemon-Chip (SoC) design. Voltage distortion (power supply noise) and delay violations (signal and clock skews) dramatically contribute to signal integrity loss. As a consequence, performance degradation, reliability problems and ultimately, functional error occur. In this paper, we propose a new methodology to enhance SoC signal integrity with respect to power/ground voltage transients, without degrading its performance. The underlying principle of the proposed methodology is to dynamically adapt the clock duty-cycle (CDC) according to the signal propagation delay through the logic whose power supply voltage is being disturbed. The methodology is based on architecture with a built-in power supply voltage sensor (BIPS), which monitors abnormal power grid activity, and a clock stretching logic (CSL) block, used to increase clock duty-cycle accordingly. Moreover, a model to accurately quantify CDC stretching as a function of V DD and/or Ground fluctuations is proposed. It is shown that the proposed methodology makes, for a set of valuable applications, the digital circuit more robust to power line fluctuations while maintaining at-speed clock rate. Moreover, when clock frequency reduction is inevitable, it enhances circuit tolerance when the disturbances start to occur, allowing the clock generator to react and reduce its frequency. This improves signal integrity when fast V DD disturbances occur. Practical experiments based on FPGA implementation for a simple benchmark circuit were performed to demonstrate the assertions.
As IC technology scales down, interconnect issues are becoming one of the major concerns of gigah... more As IC technology scales down, interconnect issues are becoming one of the major concerns of gigahertz System-on-Chip (SoC) design. Voltage distortion (power supply noise) and delay violations (signal and clock skews) dramatically contribute to signal integrity loss. Temperature variations and gradients along the die, due to (variable) power consumption, also have a negative impact on SoC behavior. As a consequence, performance degradation, reliability problems and, ultimately, functional error occur. Detection of physical defects in emerging nanometer semiconductor technologies requires the detection of dynamic faults, namely delay test. In addition, process variations must be taken into account, leading to the specification of acceptability windows and time slacks. In previous works, it has been demonstrated that parametric tests using variable power supply voltage (multi-V DD test) and temperature (multi-T test) can be rewardingly applied to production and lifetime test. In this paper, a simple analytical model to define those dynamic parametric tests and the resulting test strategy are presented. Faults are unrestrictedly defined to describe the impact of physical defects, system operation, process variations, un-modeled layoutdependent parasitics, etc. on the timing response of the Core Under Test (CUT) and modeled as variations of the load capacitances of logic gates with respect to their nominal values. Simulation results allow the capabilities of the proposed approach to be demonstrated.
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Papers by Isabel Teixeira