Papers by Dragomir Milojevic
Design-Process-Technology Co-optimization XV, 2021
Advanced CMOS SoCs with more cores and more complex memory hierarchies are hitting the memory wal... more Advanced CMOS SoCs with more cores and more complex memory hierarchies are hitting the memory wall, especially in intermediate cache levels (L2, L3). Managing the memory wall thus represent major challenge in the design of future systems and should include memory tech tuning, macro design & Logic-to-Memory interconnect optimization using multi-die packages & different 3D structures. To understand the benefits of 3D interconnects on Memory-on-Logic partitioning we analyze four different partitioning options of intermediate (L2) cache assuming high density CuCu hybrid bonding. We observe that the partitioning of the complete subsystem (memory macros & controller logic) is less beneficial with respect to reference 2D integration when compared to memory macro only partitioning schemes. Further, more memory macros are moved from the logic die, better the gains are (up to 40% total wirelength reduction). Such gains come at the expense of higher 3D pin count, motivating finer 3D pitches. Finally, we demonstrate design enablement of 3D aware IR-drop analysis for micro-and nano-TSVs with Buried Power Rail for Back Side power delivery.
Computing Research Repository, 2007
In this paper, we address the power-aware scheduling of sporadic constrained-deadline hard real-t... more In this paper, we address the power-aware scheduling of sporadic constrained-deadline hard real-time tasks using dynamic,voltage scaling upon,multiprocessor,platforms. We propose two distinct algorithms. Our first algorithm is an off-line speed determination mechanism which provides,an identical speed,for each,processor. That speed,guarantees,that all deadlines,are met if the jobs are scheduled,using EDF. The second,algorithm is an on-line and adaptive,speed adjustment,mechanism,which reduces,the energy,consumption,while the
On the Design of an Optimal Multiprocessor Real-Time Scheduling Algorithm under Practical Considerations (Extended Version)
Computing Research Repository, 2010
This research addresses the multiprocessor scheduling problem of hard real-time systems, and it e... more This research addresses the multiprocessor scheduling problem of hard real-time systems, and it especially focuses on optimal and global schedulers when practical constraints are taken into account. First, we propose an improvement of the optimal algorithm BF. We formally prove that our adaptation is (i) optimal, i.e., it always generates a feasible schedule as long as such a schedule exists,
Lecture Notes in Computer Science, 2008
Nowadays, most of the energy-aware real-time scheduling algorithms belong to the DVFS (Dynamic Vo... more Nowadays, most of the energy-aware real-time scheduling algorithms belong to the DVFS (Dynamic Voltage and Frequency Scaling) framework. These DVFS algorithms are usually efficient but, in addition to often consider unrealistic assumptions: they do not take into account the current evolution of the processor energy consumption profiles. In this paper, we propose an alternative to the DVFS framework which preserves energy, while considering the emerging technologies. We introduce a dual CPU type multiprocessor platform model (compatible with any general-purpose processor) and a non-DVFS associated methodology which considerably simplifies the energy-aware real-time scheduling problem, while providing significant energy savings.
Power dissipation of the network-on-chip in a system-on-chip for MPEG-4 video encoding
2007 IEEE Asian Solid-State Circuits Conference, 2007
In this paper we present a multi-processor system-on-chip (MPSoC) platform with six computational... more In this paper we present a multi-processor system-on-chip (MPSoC) platform with six computational and four memory nodes interconnected with Arteris network-on-chip (NoC). The platform is dedicated for real-time video encoding applications for high resolution images (HDTV) and frame rates of up to 30 fps. Extensive experiments established the power dissipation models of all individual NoC components, i.e. network interfaces, routers and wires. Based on these power models and the NoC topology we built the power model of the complete NoC. Finally we derive the power dissipation of the NoC for MPEG4 simple profile encoder. The results show that depending on the image resolution the power dissipation of the communication infrastructure vary between 15 and 22 mW, which is comparable with the state of the art dedicated low-power implementations.
We have developed a multi-objective performance exploration tool to help SoC designers to take de... more We have developed a multi-objective performance exploration tool to help SoC designers to take decisions at the early stages of a flow. We demonstrate it on a real time video decoding application.
Physics of Fluids B: Plasma Physics, 1991
(Received 5 February 1991; accepted 29 May 1991) A nonequilibrium model is developed for the pred... more (Received 5 February 1991; accepted 29 May 1991) A nonequilibrium model is developed for the prediction of two-dimensional flow, electron and heavy particle temperatures, and number density distributions in cascaded arcs of monatomic gases. The system of strongly coupled elliptic partial differential equations describing plasma flow is solved by a numerical method based on a control volume with a nonstaggered
ACM SIGBED Review, 2011
EKG is a multiprocessor scheduling algorithm which is optimal for the schedule of real-time perio... more EKG is a multiprocessor scheduling algorithm which is optimal for the schedule of real-time periodic tasks with implicit deadlines. It adheres to the deadline partitioning fair (DP-Fair) approach. However, it was shown in recent studies that the systematic execution of some tasks inherent in such approaches, significantly reduce the usability of this algorithm. Hence, we propose a swapping algorithm with the aim of reducing the number of preemptions and migrations incurred by EKG. This algorithm should enhance the practicality of EKG while keeping its optimality.
On the use of Multi-Criteria Decision Aid tools for the efficient design of 3D-Stacked Integrated Circuits: A preliminary study
2010 IEEE International Conference on Industrial Engineering and Engineering Management, 2010
ABSTRACT In past decades, the electronic industry has been following the Moore's law to i... more ABSTRACT In past decades, the electronic industry has been following the Moore's law to improve the performance of CMOS integrated circuits (IC). However, it will probably be impossible to follow this law in the future due to physical limitations appearing with the miniaturization of the transistors below a certain threshold. In order to overcome this problem, new technologies have emerged, and among them the 3D-Stacked Integrated Circuits (3D-SIC) have been proposed to keep the Moore's momentum alive. 3D-SICs can bring numerous advantages in the design of future ICs but at the cost of additional design complexity due to their highly combinatorial nature, and requiring the optimization of several conflicting criteria. In this paper, we present a preliminary study of tools that can help the design of 3D-SICs, using multi-criteria analysis. Our study has targeted one of the main issues in the design of 3D-SICs: the floorplanning. This work has shown that the use of Multi-Criteria Decision Aid (MCDA) tools can provide relevant and objective analysis of the problem that may not be feasible with the current design methods. We believe that these promising results will allow designers to overcome the complexity of designing 3D-SICs.
Pathfinding: A design methodology for fast exploration and optimisation of 3D-stacked integrated circuits
2009 International Symposium on System-on-Chip, 2009
... 978-1-4244-4467 -0/09/$25.00 ©2009 IEEE 118 C. Roger Carpenter, D. Pol Marchal Javelin DA, Su... more ... 978-1-4244-4467 -0/09/$25.00 ©2009 IEEE 118 C. Roger Carpenter, D. Pol Marchal Javelin DA, Suite 118-IMEC 21028 Bank Mill Road-Kapeldreef 75, Saratoga, CA 95070-B-300l Leuven USA-Belgium vs. a new die; 2. Selection of process technology per tier; DRAM vs. ...
DRAM-on-logic Stack – Calibrated thermal and mechanical models integrated into PathFinding flow
2011 IEEE Custom Integrated Circuits Conference (CICC), 2011
ABSTRACT In this paper, we present thermal and mechanical characterization of a DRAM-on-logic sta... more ABSTRACT In this paper, we present thermal and mechanical characterization of a DRAM-on-logic stack. Our experimental data indicates that a holistic optimization of design and technology is needed to achieve working 3D stacks. Particularly, the stack organization and TSV/μbump layout must be fine-tuned together with the 3D technology for managing mechanical and thermal challenges. In order to support system designers, we propose hereto a dedicated thermal and mechanical model, integrated into the design flow. We also indicate the data required from foundries and OSATs to achieve good fidelity with measurement results.
EUROCON 2005 - The International Conference on "Computer as a Tool", 2005
We propose a new algorithm to analyze cell migration. Sequences of frames are automatically recor... more We propose a new algorithm to analyze cell migration. Sequences of frames are automatically recorded from standard (unmarked) cell cultures by means of phasecontrast microscopes equiped with video acquisition systems. This algorithm is able to automatically follow the locations in the reverse time of many cells during sequences covering relatively long periods of time such as 1 to 3 days. We then recombine the obtained cell tracks to detect mitoses and build a "mitotic tree". Several features are extract to characterize cell population motility and proliferation. As illustration the method is tested on U373 astrocytoma cell line.
Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study
2009 IEEE International Conference on 3D System Integration, 2009
Page 1. 1 Automated PathFinding Tool Chain for 3D-Stacked Integrated Circuits: Practical Case Stu... more Page 1. 1 Automated PathFinding Tool Chain for 3D-Stacked Integrated Circuits: Practical Case Study Dragomir Milojevic, Trevor E. Carlson, Kris Croes, Riko Radojcic, Diana F. Ragett, Dirk Seynhaeve, Federico Angiolini, Geert Van der Plas, and Pol Marchal ...
Computers and 3D Image Synthesis as Tools for Archaeology
Journal of Crystal Growth, 2005
Computing power at low cost, highly accurate 2D, 3D data acquisition systems, advanced methods of... more Computing power at low cost, highly accurate 2D, 3D data acquisition systems, advanced methods of 2D, 3D signal processing, images synthesis, artificial intelligence and huge data base management utilities are the basic tools that can be used for development of dedicated systems that can help the work of art historians and archaeologists. In this paper we describe the application of
MCDA-based methodology for efficient 3D-design space exploration and decision
2010 International Symposium on System on Chip, 2010
... Appliquées CoDE-SMG - Faculté des Sciences Appliquées Université Libre de Bruxelles, Av. FD... more ... Appliquées CoDE-SMG - Faculté des Sciences Appliquées Université Libre de Bruxelles, Av. FD Roosevelt 50, 1050 Brussels, Belgium Email: {nguyen.anh.vu.doan, frederic.robert, yves.de.smet, dragomir.milojevic}@ulb.ac.be ...
Quantitative Comparison of Switching Strategies for Networks on Chip
2007 3rd Southern Conference on Programmable Logic, 2007
To ensure low power consumption while maintaining flexibility and performance, future systems-on-... more To ensure low power consumption while maintaining flexibility and performance, future systems-on-chip (SoC) will integrate many processor nodes and memory units. To interconnect these IP nodes, networks-on-chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. One major problem consists in being able to compare choices and strategies in NoC design. To tackle this problem, we
2008 IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing (sutc 2008), 2008
In this paper, we address the power-aware scheduling of sporadic constrained-deadline hard real-t... more In this paper, we address the power-aware scheduling of sporadic constrained-deadline hard real-time tasks using dynamic voltage scaling upon multiprocessor platforms. We propose two distinct algorithms. Our first algorithm is an off-line speed determination mechanism which provides an identical speed for each processor. That speed guarantees that all deadlines are met if the jobs are scheduled using EDF. The second algorithm is an on-line and adaptive speed adjustment mechanism which reduces the energy consumption while the system is running.
A Framework Introducing Model Reversibility in SoC Design Space Exploration
Lecture Notes in Computer Science, 2007
... Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, and Frederic Robert ... Internation... more ... Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, and Frederic Robert ... International Journal of Emerging Technologies in Learning 2(1) (2007) 5. VSIA: Vsia system level design model taxonomy document (2001) 6. Panagopoulos, I.: Models, specification languages and ...
A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation
Lecture Notes in Computer Science, 2008
... Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, and Frederic Robert ...Panagopoulos... more ... Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, and Frederic Robert ...Panagopoulos, I.: Models, specification languages and their interrelationship mod-els, specification languages and their interrelationship for system level design. ...
2012 24th Euromicro Conference on Real-Time Systems, 2012
A multiprocessor scheduling algorithm named U-EDF, was presented in [1] for the scheduling of per... more A multiprocessor scheduling algorithm named U-EDF, was presented in [1] for the scheduling of periodic tasks with implicit deadlines. It was claimed that U-EDF is optimal for periodic tasks (i.e., it can meet all deadlines of every schedulable task set) and extensive simulations showed a drastic improvement in the number of task preemptions and migrations in comparison to state-of-the-art optimal algorithms. However, there was no proof of its optimality and U-EDF was not designed to schedule sporadic tasks.
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Papers by Dragomir Milojevic