Papers by Deeprose Subedi
VLSICS, 2012
In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idl... more In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistor- Static Energy Recovery CMOS adder (SERF) circuits.
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Papers by Deeprose Subedi