Papers by Andrea Silvagni
Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or programming one or more sectors
Computers, Oct 24, 2017
In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NA... more In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a "punch-and-plug" process-with gate-all-around (GAA) cell devices-against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production.
NAND DDR interface
Inside NAND Flash Memories, 2010
NAND design for testability and testing
Inside NAND Flash Memories, 2010
Proceedings of The IEEE, 2003
In the past few years, the complexity of logic functions and architectures inside a Flash memory ... more In the past few years, the complexity of logic functions and architectures inside a Flash memory device has grown in order to face the need for more complex system interfaces and to manage the increased amount of stored data. In this paper, an overview of these developments will be given. The paper is divided into sections describing areas where logic circuits play a key role: program/erase algorithms handling and user interface, redundancy management for yield enhancement, error correction codes to enhance reliability, and burst and page mode access control to enhance read bandwidth.
Modular architecture for a family of multilevel 256/192/128/64 Mbit 2-bit/cell 3 V-only NOR flash memory devices
Inorganic Chemistry Communications, 2001
This paper presents a family of 2 b/cell devices fabricated in 0.15 μm STI CMOS technology NOR-ty... more This paper presents a family of 2 b/cell devices fabricated in 0.15 μm STI CMOS technology NOR-type flash memory. The device organization is based on a modular architecture that allows a very fast generation of all devices of the family from 64 Mbit to 256 Mbit having very similar performance. The modular architecture mainly concerns read path and high Voltage management aspects. A very realistic chip emulation of all devices is possible by using the 256 Mbit parent chip. The 256 Mbit device has 90 mm2 die size and it is composed of 256 1-Mbit sectors with hierarchical row and column decoding. Asynchronous access time with error correction is 120 ns for the 256 Mbit. Burst mode read at 50 and 66 MHz is also available
Proceedings of The IEEE, 2003
This paper presents a survey of the principal architectures and blocks building up a Flash memory... more This paper presents a survey of the principal architectures and blocks building up a Flash memory, describing how these blocks are designed and how their design has changed over the years to satisfy the new specification requests. For example, the continuous supply voltage reduction aimed at portable electronic solutions has forced designers to find innovative design solutions. An overview of the test modes developed for the Flash device not only to debug the chip but also to try to improve reliability is given. Ad hoc test modes are useful to deeply increase the analysis capability. Finally, the test methodology for Flash memories, a challenge between the test time reduction and better test coverage, is presented.
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Papers by Andrea Silvagni