Papers by Ahmad Islam (CIV)
Ni/TiO2/ $\beta$-Ga2O3 Heterojunction Diodes with NiO Guard Ring Simultaneously Increasing Breakdown Voltage and Reducing Turn-on Voltage
2023 Device Research Conference (DRC)
arXiv (Cornell University), Feb 22, 2017
Process-related and stress-induced changes in threshold voltage are major variability concerns in... more Process-related and stress-induced changes in threshold voltage are major variability concerns in ultra-scaled CMOS transistors. The device designers consider this variability as an irreducible part of the design problem and use different circuit level optimization schemes to handle these variations. In this paper, we demonstrate how an increase in the negative steepness of the universal mobility relationship improves both the process-related (e.g., oxide thickness fluctuation, gate work-function fluctuation), as well as stress-induced or reliability-related (e.g., Bias Temperature Instability or BTI) parametric variation in CMOS technology. Therefore, we calibrate the universal mobility parameters to reflect the measured variation of negative steepness in uniaxially strained CMOS transistor. This allows us to study the extent of (process-related and stress-induced parametric) variation resilience in uniaxial strain technology by increasing the negative steepness of the mobility characteristics. Thus, we show that variability analysis in strained CMOS technology must consider the presence of self-compensation between mobility variation and threshold voltage variation, which leads to considerable amount of variation resilience. Finally, we use detailed circuit simulation to stress the importance of accurate mobility variation modeling in SPICE analysis and explain why the variability concerns in strained technology may be less severe than those in unstrained technology.
arXiv (Cornell University), Nov 14, 2010
APL Materials, 2022
Gallium Oxide has undergone rapid technological maturation over the last decade, pushing it to th... more Gallium Oxide has undergone rapid technological maturation over the last decade, pushing it to the forefront of ultra-wide band gap semiconductor technologies. Maximizing the potential for a new semiconductor system requires a concerted effort by the community to address technical barriers which limit performance. Due to the favorable intrinsic material properties of gallium oxide, namely, critical field strength, widely tunable conductivity, mobility, and melt-based bulk growth, the major targeted application space is power electronics where high performance is expected at low cost. This Roadmap presents the current state-of-the-art and future challenges in 15 different topics identified by a large number of people active within the gallium oxide research community. Addressing these challenges will enhance the state-of-the-art device performance and allow us to design efficient, high-power, commercially scalable microelectronic systems using the newest semiconductor platform.
(Invited) Gallium Oxide Process Development and Integration for Future RF and Power Switching Applications
ECS Meeting Abstracts, 2021
Electronics, 2013
Excellent electrical performance and extreme sensitivity to chemical species in semiconducting Si... more Excellent electrical performance and extreme sensitivity to chemical species in semiconducting Single-Walled Carbon NanoTubes (s-SWCNTs) motivated the study of using them to replace silicon as a next generation field effect transistor (FET) for electronic, optoelectronic, and biological applications. In addition, use of SWCNTs in the recently studied flexible electronics appears more promising because of SWCNTs' inherent flexibility and superior electrical performance over silicon-based materials. All these applications require SWCNT-FETs to have a wafer-scale uniform and reliable performance over time to a level that is at least comparable with the currently used silicon-based nanoscale FETs. Due to similarity in device configuration and its operation, SWCNT-FET inherits most of the variability and reliability concerns of silicon-based FETs, namely the ones originating from line edge roughness, metal work-function variation, oxide defects, etc. Additional challenges arise from the lack of chirality control in as-grown and post-processed SWCNTs and also from the presence of unstable hydroxyl (-OH) groups near the interface of SWCNT and dielectric. In this review article, we discuss these variability and reliability origins in SWCNT-FETs. Proposed solutions for mitigating each of these sources are presented and a future perspective is provided in general, which are required for commercial use of SWCNT-FETs in future nanoelectronic applications.
Advanced materials (Deerfield Beach, Fla.), Jan 5, 2015
High purity semiconducting single-walled carbon nanotubes (s-SWCNTs) with a narrow diameter distr... more High purity semiconducting single-walled carbon nanotubes (s-SWCNTs) with a narrow diameter distribution are required for high-performance transistors. Achieving this goal is extremely challenging because the as-grown material contains mixtures of s-SWCNTs and metallic- (m-) SWCNTs with wide diameter distributions, typically inadequate for integrated circuits. Since 2000, numerous ex situ methods have been proposed to improve the purity of the s-SWCNTs. The majority of these techniques fail to maintain the quality and integrity of the s-SWCNTs with a few notable exceptions. Here, the progress in realizing high purity s-SWCNTs in as-grown and post-processed materials is highlighted. A comparison of transistor parameters (such as on/off ratio and field-effect mobility) obtained from test structures establishes the effectiveness of various methods and suggests opportunities for future improvements.
Fundamentals of Bias Temperature Instability in MOS Transistors, 2015
Science, 2011
Electronic systems with physical properties matched to the human epidermis can be used in clinica... more Electronic systems with physical properties matched to the human epidermis can be used in clinical monitoring.
IEEE Transactions on Electron Devices, 2008
IEEE Transactions on Electron Devices, 2009
In this paper, a simple phenomenological technique is used to isolate the hole-trapping and inter... more In this paper, a simple phenomenological technique is used to isolate the hole-trapping and interface trap generation components during negative bias temperature instability (NBTI) stress in plasma nitrided oxide (PNO) p-MOSFETs. This isolation methodology reconciles the apparent differences between experimentally measured NBTI power-law time exponents obtained by ultrafast on-the-fly I DLIN method, which are the ones obtained using slightly delayed but very long-time measurements, and the corresponding exponents predicted by the reaction-diffusion model. A systematic validation of the isolation technique is provided through degradation data taken over a broad range of operating conditions and a wide variety of PNO processes, to establish the robustness and uniqueness of the separation procedure.
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Papers by Ahmad Islam (CIV)