Electronic Systems Engineering

In this reported work the interface properties of a process-induced thin interfacial oxide layer present between Ni and 4H-SiC substrate was examined systematically for fabricated Ni/4H-SiC (0 0 0 1) Schottky barrier diodes. Moreover, their contribution in the form of interface traps level density was investigated employing capacitance-conductance (C-C) spectroscopy techniques. The distinctive parameters of interface at Ni and 4H-SiC substrate were determined from the CC spectroscopy under forward bias condition. The increase in capacitance value towards lower frequencies results from the presence of interface traps at the Ni/4H-SiC interface however the observed maximums peaks in the normalized conductance curve of the diode indicates the presence of an interfacial layer in the fabricated Schottky barrier diode. It has been found that the density of interface traps level decreases (1.25 Â 10 13-1.16 Â 10 13 cm À 2 eV À 1) and time constant of interface traps (3.16 Â 10 À 5-1.47 Â 10 À 3 s) increases with bias voltage at anode in the range of Ec-0.06 to Ec-1.06 eV from the top of conduction band toward midgap of n-type 4H-SiC substrate. Furthermore, the capture cross section was found to vary from 9.31 Â 10 À 10 cm 2 in (E c-0.06) eV to 4.43 Â 10-11 cm 2 in (E c-1.06) eV.

For semiconductor industry to replace silicon CMOS integrated circuits by 2-D semiconductors or transition metal dichalcogenides (TMDs), TMD-based n-FETs as well as p-FETs having performance better than Si FETs are a must. While a lot of literature demonstrates n-channel characteristics, the major roadblocks in the realization of TMD-based CMOS integrated circuit are the lack of approach to realize p-channel transistors having performance comparable to n-channel transistors, all realized over the same TMD substrate. To address this, we propose a new technique by engineering WSe 2 /metal interface to realize WSe 2-based high-performance p-and n-channel transistors and therefore unveil its potential toward CMOS-integrated technology. The technique involves a dry process, based on the chemistry between the sulfur atom and WSe 2 surface, that induces unique metal-induced gap states in the source/drain (S/D) contact area, which causes improved hole (electron) injection when Cr (Ni) as S/D metal was used. This has enabled the controlled realization of high-performance WSe 2 FETs with desired polarity (N, P, or ambipolar), which solely depends on the contact metal used and contact engineering (CE)/surface engineering. Fundamental investigations on the effect of the proposed CE on metal-WSe 2 interface revealed interesting and counter-intuitive facts, which very well corroborate with experimental observations. Index Terms-CMOS integrated circuits, FET, metal-induced gap states (MIGSs), tungsten diselenide (WSe 2).

This work reports, for the first time, time dependent degradation and failure of CVD monolayer MoS2 based field-effect transistor channel under DC voltage stress, which seem to have originated from its unique molecular description. Degradation was found to be permanent, which takes place at fields lower than critical field for breakdown and have been discovered to be a strong function of channel temperature and e-field. Strong dependence of channel current on self-heating across the channel has also been observed, which resulted in significant drop in channel current under stress, which however recovers when stress was removed. Reversal in degradation trends and permanent channel failure was observed at lower (77-150K) channel temperatures. Unique localized low resistance regions as well as field assisted physical damage result in overall (ON and OFF state) performance degradation of MoS2 transistors. Micro-Raman and Photoluminescence investigations, as a function of stress time, are performed to investigate the micro-origin of permanent degradation and failure.

Metal-semiconductor interface is a bottleneck for efficient transport of charge carriers through Transition Metal Dichalcogenide (TMD) based field-effect transistors (FETs). Injection of charge carriers across such interfaces is mostly limited by Schottky barrier at the contacts which must be reduced to achieve highly efficient contacts for carrier injection into the channel. Here we introduce a universal approach involving dry chemistry to enhance atomic orbital interaction between various TMDs (MoS 2 , WS 2 , MoSe 2 and WSe 2) & metal contacts has been experimentally demonstrated. Quantum chemistry between TMDs, Chalcogens and metals has been explored using detailed atomistic (DFT & NEGF) simulations, which is then verified using Raman, PL and XPS investigations. Atomistic investigations revealed lower contact resistance due to enhanced orbital interaction and unique physics of charge sharing between constituent atoms in TMDs with introduced Chalcogen atoms which is subsequently validated through experiments. Besides contact engineering, which lowered contact resistance by 72, 86, 1.8, 13 times in MoS 2 , WS 2 , MoSe 2 and WSe 2 respectively, a novel approach to cure / passivate dangling bonds present at the 2D TMD channel surface has been demonstrated. While the contact engineering improved the ON-state performance (I ON , g m ,  R ON) of 2D TMD FETs by orders of magnitude, Chalcogen based channel passivation was found to improve gate control (I OFF , SS, & V TH) significantly. This resulted in an overall performance boost. The engineered TMD FETs were shown to have performance on par with best reported till date. I. Introduction Growth of semiconductor industry is driven by Moore's law 1 which intends to improve the efficiency of electronic gadgets in terms of speed and compactness by 2×, every 1.5 years. This is achieved by aggressive channel length scaling of Silicon MOSFETs. On the other hand, channel length scaling leads to short channel effects (SCE) like drain induced source barrier lowering and threshold voltage roll-off due to compromised gate control over channel. This results into higher source-to-drain leakage current, higher subthreshold slope and lower noise margins, which eventually increases the static power loss across the VLSI system. To mitigate SCE, devices like FinFETs 3, 4, 5 Multi-gate FET 2, 3, 6, 7 , Ultra-thin body (UTB) FETs 6, 8 and Tunnel FETs (TFETs) 9 have been proposed, which offer improved gate control and better SCE immunity. The key in most of the ultrascaled FET concepts is to reduce the channel thickness as the channel length is scaled down. However, scaling channel thickness beyond 5nm leads to mobility degradation and threshold voltage instability due to quantum confinement and surface dangling bonds, which leads to performance roll off. Atomically thin layers of 2D semiconductors like Transition Metal Dichalcogenides (TMDs) 10-15 on the other hand offer better gate control due to lack of dangling bonds perpendicular to their basal plane, as well as missing quantum issues when compared to bulk semiconductors. This makes 2D TMDs promising candidates for short channel FETs. While a decent amount of work has been reported by various authors on improving performance of 2D TMDs like MoS 2 13, 22, 24, 25, 26, 34 , MoSe 2 16, 17 , WS 2 18, 19 and WSe 2 20, 21 , they still suffer from high contact resistance, low ON state current, depletion mode operation and poor sub-threshold slope. Techniques reported earlier to improve device performance were often parameter-specific and while they resulted in striking improvement in the target parameter, the overall transistor behavior was often compromised, or the technique fails to offer a scalable process. For example, in earlier works, techniques like doping by Potassium 27 , PEI 28 , Chloride ion 29 , Benzyl Viologen 30 , Methanol 31 , Tetracyanoquinodimethane (TCNQ) 32 , phase engineering 33 on MoS 2 and/or WS 2 have been utilized to improve ON state current. These methods however suffered from one or the other limitations like non-scalability, involvement of wet chemistry or deterioration of other figure of merit parameters. For instance, Scandium contacts have resulted in record high ON currents in MoS 2 15 Simulation details for Device calculations: The metal semiconductor contacts are created using Virtual Nano Lab builder in ATK. The contact metal is cleaved along the surface which gives minimum strain to the contact interface. Extended Huckel Semi Empirical method of Atomistix ToolKit and NEGF are used for the calculations. The density mesh cutoff is 45 Hartee with 10 k-points along the width and 200 k-points along the channel of the devices. Different Huckel basis sets are used for different devices along with a multigrid Poisson solver with Dirichlet boundary condition. A source-drain bias of 250 mV is applied to conduct the carrier transport analysis on 300K electron temperature. Simulation details for bulk calculation: The DFT simulation is done for three different structures of the MoS 2 /WS 2 to validate the results. For Ab-initio simulation, QuantamWise ATK simulation package has been used. The DFT calculation is performed on a 5x5 MoS 2 /WS 2 supercell with single SV, Sulfur on the interstitial sites and on the perfect crystal. The Local Density Approximation (LDA) is used as the exchange-correlation with 7 k points sampling in the periodic direction. All the structures are optimized with 0.01eV/A force tolerance and 0.001 eV/A 3 stress tolerance before Band structure and DOS calculations. Fabrication method and H 2 S treatment: The fabrication process involves mechanically exfoliating TMDs using scotch tape method. The exfoliated flakes are then transferred onto a 90nm SiO 2 /Si sample. Contact pads for 500 nm channel length are then patterned through e-beam lithography on few-layered flakes identified through optical microscope followed by contact metal deposition using TECPORT e-beam evaporator. Post lift-off and annealing at 250 °C, electrical characterization is done on the as-fabricated back gated FETs. After electrical characterization, samples are placed inside a chamber with 20 torr partial pressure of H 2 S at 350 °C, as discussed earlier. Post-treatment, contact pads are patterned followed by metal deposition and lift-off on already processed flakes (previously fabricated FET). The complete process along with the mechanism of low temperature partial decomposition of H 2 S is shown in Supplementary information.