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Both the discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) blocks operates at a lower supply voltage in case of approximate adders than the exact mode. Here, DCT and IDCT operates at a supply voltage of 1.28 V and 1.13 V in the exact mode, respectively. The different supply operating voltages are demonstrated in Figures 12 and 13 for different approximations and truncations considering varied bits. Table 4 demonstrates the percentage power savings considering varied approximations and truncation against the base case. Approximation 3 saves the maximum power.

Table 4 Both the discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) blocks operates at a lower supply voltage in case of approximate adders than the exact mode. Here, DCT and IDCT operates at a supply voltage of 1.28 V and 1.13 V in the exact mode, respectively. The different supply operating voltages are demonstrated in Figures 12 and 13 for different approximations and truncations considering varied bits. Table 4 demonstrates the percentage power savings considering varied approximations and truncation against the base case. Approximation 3 saves the maximum power.

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Figure 1. Carry generator for 4-bit block wba): It is explained in varied traditional methods that the M;,,, processing of approximate computing i elatively faster with minimum power consumption than the M;, processing of exact computing. In th osroposed reconfigurable adder, two types of operating modes are discussed such as exact and approximat yperating modes based on this M;,41 processing. However, only one multiplexer is utilized in the propose somputing methodology M;,,, than the traditional computing methods. Multiplex consists of input and outpu nechanisms in which input signals are approximate and output signals are considered as augmented carr signals as the selector. The carry output generation is computed using operating mode signals in either th >xact computing or approximate computing. The gate-level computation is performed using the propose: nethodology as demonstrated in Figure 1. The power consumption of augmenting region is handled using thi »ower-gated p-channel metal-oxide semiconductor (p-MOS) headers when the carry computation block is i he approximate computing. All the computing signals of processing units are handled using only one signa when all the adder carry is generated using the proposed design structure and methodology. However, all th idder output bits may remain imprecise. The approximate adder accuracy is enhanced by utilizing the MS bi sroup of the exact carry generator as demonstrated in [10] and [20]. This approach can be used in designin, he carry look ahead adder with multiple accuracy levels. Adders are subdivided into a few differen segments for the approximate and exact operating modes to design adjustable accuracy composed structures hus, in this report, efficiency computation for approximate and exact computing is discussed. 3.2. Accuracy analysis of approximate adder
Figure 1. Carry generator for 4-bit block wba): It is explained in varied traditional methods that the M;,,, processing of approximate computing i elatively faster with minimum power consumption than the M;, processing of exact computing. In th osroposed reconfigurable adder, two types of operating modes are discussed such as exact and approximat yperating modes based on this M;,41 processing. However, only one multiplexer is utilized in the propose somputing methodology M;,,, than the traditional computing methods. Multiplex consists of input and outpu nechanisms in which input signals are approximate and output signals are considered as augmented carr signals as the selector. The carry output generation is computed using operating mode signals in either th >xact computing or approximate computing. The gate-level computation is performed using the propose: nethodology as demonstrated in Figure 1. The power consumption of augmenting region is handled using thi »ower-gated p-channel metal-oxide semiconductor (p-MOS) headers when the carry computation block is i he approximate computing. All the computing signals of processing units are handled using only one signa when all the adder carry is generated using the proposed design structure and methodology. However, all th idder output bits may remain imprecise. The approximate adder accuracy is enhanced by utilizing the MS bi sroup of the exact carry generator as demonstrated in [10] and [20]. This approach can be used in designin, he carry look ahead adder with multiple accuracy levels. Adders are subdivided into a few differen segments for the approximate and exact operating modes to design adjustable accuracy composed structures hus, in this report, efficiency computation for approximate and exact computing is discussed. 3.2. Accuracy analysis of approximate adder
Table 1. Exponent and mantissa bits for IEEE-754 basic and extended floating point types 3.4. Floating point adder architecture A generic FP adder architecture includes hardware blocks for exponent comparison, mantissa alignment, mantissa addition, normalization, and rounding of the mantissa (shown in Figure 3 and detailed in (30], [32], [33]). Two operands are first unpacked from the FP format, and each mantissa is added to the hidden 'I' bit. The addition of FP numbers involves comparing the two exponents, and adding the two mantissae; the exponents are first evaluated to find the larger number. The mantissa is then swapped according to the exponent comparison; they are then aligned to have an equal exponent prior to the addition Figure 2. General IEEE-754 floating-point format
Table 1. Exponent and mantissa bits for IEEE-754 basic and extended floating point types 3.4. Floating point adder architecture A generic FP adder architecture includes hardware blocks for exponent comparison, mantissa alignment, mantissa addition, normalization, and rounding of the mantissa (shown in Figure 3 and detailed in (30], [32], [33]). Two operands are first unpacked from the FP format, and each mantissa is added to the hidden 'I' bit. The addition of FP numbers involves comparing the two exponents, and adding the two mantissae; the exponents are first evaluated to find the larger number. The mantissa is then swapped according to the exponent comparison; they are then aligned to have an equal exponent prior to the addition Figure 2. General IEEE-754 floating-point format
Figure 3. Floating point adder algorithm in the mantissa adder. Following the addition, normalization shifts are required to restore the result to the IEEE standard format. The normalization is completed by left shifting with a number of leading zeros; therefore, leading zero detection is a key step for normalization. Rounding the normalized result is the last step before storing back the result; special cases (such as overflow underflow, and not a number) are also detected and represented by flags.
Figure 3. Floating point adder algorithm in the mantissa adder. Following the addition, normalization shifts are required to restore the result to the IEEE standard format. The normalization is completed by left shifting with a number of leading zeros; therefore, leading zero detection is a key step for normalization. Rounding the normalized result is the last step before storing back the result; special cases (such as overflow underflow, and not a number) are also detected and represented by flags.
Figure 4. Approximate adder concept The approximate FP adder design originates at the architecture level with the exponent and mantissa adder/substractor designed using approximate fixed-point adders. An N-bit adder consists of two parts, i.e., an m-bit exact adder and an n-bit inexact adder (Figure 4). The exact adder part can have the exact implementation as a full adder circuit. The inexact adder will ignore the carry bits for computation thereby reducing the critical path as well as the hardware utilization. The modified approximate adder concept can also be used for the mantissa adder for approximate computation. The mantissa adder will provide a larger scope, as the number of bits in the mantissa are higher than the exponent and at the same time, the approximate design in the mantissa adder has a lower impact on the error, because the mantissa part is less significant than the exponent part. Therefore, an inexact design of a mantissa adder is more appropriate.
Figure 4. Approximate adder concept The approximate FP adder design originates at the architecture level with the exponent and mantissa adder/substractor designed using approximate fixed-point adders. An N-bit adder consists of two parts, i.e., an m-bit exact adder and an n-bit inexact adder (Figure 4). The exact adder part can have the exact implementation as a full adder circuit. The inexact adder will ignore the carry bits for computation thereby reducing the critical path as well as the hardware utilization. The modified approximate adder concept can also be used for the mantissa adder for approximate computation. The mantissa adder will provide a larger scope, as the number of bits in the mantissa are higher than the exponent and at the same time, the approximate design in the mantissa adder has a lower impact on the error, because the mantissa part is less significant than the exponent part. Therefore, an inexact design of a mantissa adder is more appropriate.
Int J Reconfigurable & Embedded Syst, Vol. 13, No. 3, November 2024: 650-664
Int J Reconfigurable & Embedded Syst, Vol. 13, No. 3, November 2024: 650-664
Figure 5. W-bit window for approximate computation
Figure 5. W-bit window for approximate computation
In the proposed adder, for the LS, W-bit window sum and carry are computed as per (9). The schematic of 1-bit full adder in the proposed configuration is given in Figure 7. The sum and carry for most significant (8-W=4) bits are computed as for an exact adder given in (10). The truth table for the proposed sum and carry equations is given in Table 2.
In the proposed adder, for the LS, W-bit window sum and carry are computed as per (9). The schematic of 1-bit full adder in the proposed configuration is given in Figure 7. The sum and carry for most significant (8-W=4) bits are computed as for an exact adder given in (10). The truth table for the proposed sum and carry equations is given in Table 2.
Figure 7. Schematic for carry and sum generator of proposed adder Table 2. Truth table for the proposed sum and carry
Figure 7. Schematic for carry and sum generator of proposed adder Table 2. Truth table for the proposed sum and carry
Figure 8. Proposed 23 bit mantissa adder For realizing the 23-bit approximate adder, three 8-bit adders are used. The lower two 8-bit adders are the proposed 8-bit approximate adders, while the MS byte is implemented using an exact 8-bit adder. The proposed 23-bit mantissa adder is shown in Figure 8.
Figure 8. Proposed 23 bit mantissa adder For realizing the 23-bit approximate adder, three 8-bit adders are used. The lower two 8-bit adders are the proposed 8-bit approximate adders, while the MS byte is implemented using an exact 8-bit adder. The proposed 23-bit mantissa adder is shown in Figure 8.
Figure 10. Simplified approximate adder Figure 9. Traditional approximate adder A detailed analysis of full adder truth tab out of all possible 8 combinations, except when th Further, in the traditional approximate adder as sh one way to simplify the traditional approximate ad is set in the traditional approximate adder, then the mixture of 4 source-drain diffusion and 2 gates ca of total capacitance compared to the traditional ap der is by discarding the Sum circuit. Thus, i proximate adder. However, it will cause a de or more approximate adders are cascaded with each other. As mentioned, that Sum = C,,,, for all possible 8 combinations, thus the simplified a Figure 10. Moreover, Figure 11 shows the simplified approximate adder circuit using t approach. As a result, 3 errors in Sum and 1 error in C,,,, is generated as demonstrated in Table 3. e is carried out and observed that Sum = C,,,, for 6 times e value of A, B, Cj, is kept at 0 and 1 for all, respectively. own in Figure 9, C,,,, is evaluated in the first stage. Then, Sum = Coue amount of capacitance present in the Sum circuit will be a pacitance. As a result, there is a massive increase in terms ay where two 6 times out of pproximate adder is cascaded for C,,,, as demonstrated in he mentioned Table 3. Truth table for traditional full adder and approximations
Figure 10. Simplified approximate adder Figure 9. Traditional approximate adder A detailed analysis of full adder truth tab out of all possible 8 combinations, except when th Further, in the traditional approximate adder as sh one way to simplify the traditional approximate ad is set in the traditional approximate adder, then the mixture of 4 source-drain diffusion and 2 gates ca of total capacitance compared to the traditional ap der is by discarding the Sum circuit. Thus, i proximate adder. However, it will cause a de or more approximate adders are cascaded with each other. As mentioned, that Sum = C,,,, for all possible 8 combinations, thus the simplified a Figure 10. Moreover, Figure 11 shows the simplified approximate adder circuit using t approach. As a result, 3 errors in Sum and 1 error in C,,,, is generated as demonstrated in Table 3. e is carried out and observed that Sum = C,,,, for 6 times e value of A, B, Cj, is kept at 0 and 1 for all, respectively. own in Figure 9, C,,,, is evaluated in the first stage. Then, Sum = Coue amount of capacitance present in the Sum circuit will be a pacitance. As a result, there is a massive increase in terms ay where two 6 times out of pproximate adder is cascaded for C,,,, as demonstrated in he mentioned Table 3. Truth table for traditional full adder and approximations
Figure 12. Operating voltages considering different bits for DCT technique
Figure 12. Operating voltages considering different bits for DCT technique
Figure 13. Operating voltages considering different bits for IDCT technique 4.2. Performance metrics comparison for approximate carry look-ahead adder Here G,, is defined as the accurate result for the k — th input set. The performance of the proposed adder design is compared with previous works such as [23], [24] in terms of performance metrics like percentage error rate, average error detection, and normalized error detection. The adder design structure presented in [24] is called generic accuracy configurable (GeAr), and in [23] is called ethylene recovery unit (ERU). However, the ERU design structure is segregated into two design structures i.e. with an error reduction unit and without an error reduction unit. Their detailed description is presented in [23]. The proposed adder design structure is studied considering 8-bit added for varied window sizes while in [23], the window size is fixed as 2 k. Figure 14 shows the proposed 8-bit approximate adder design comparison in terms of error rate in percentage against GeAr considering different window sizes. It is evident from Figure 4 results that the proposed accuracy of the proposed approximate adder design is higher than the [24]. Other possible combinations regarding error metrics for performance comparison are average error detection and normalized error detection.
Figure 13. Operating voltages considering different bits for IDCT technique 4.2. Performance metrics comparison for approximate carry look-ahead adder Here G,, is defined as the accurate result for the k — th input set. The performance of the proposed adder design is compared with previous works such as [23], [24] in terms of performance metrics like percentage error rate, average error detection, and normalized error detection. The adder design structure presented in [24] is called generic accuracy configurable (GeAr), and in [23] is called ethylene recovery unit (ERU). However, the ERU design structure is segregated into two design structures i.e. with an error reduction unit and without an error reduction unit. Their detailed description is presented in [23]. The proposed adder design structure is studied considering 8-bit added for varied window sizes while in [23], the window size is fixed as 2 k. Figure 14 shows the proposed 8-bit approximate adder design comparison in terms of error rate in percentage against GeAr considering different window sizes. It is evident from Figure 4 results that the proposed accuracy of the proposed approximate adder design is higher than the [24]. Other possible combinations regarding error metrics for performance comparison are average error detection and normalized error detection.
Figure 14. Error rate (%) comparison of proposed adder vs GEAR bit approximate adder design comparison in terms of normalized error detection against [23], [24] considering three different window sizes. It is evident from Figure 16 results that the proposed adder design has slightly lower normalized error detection values than GeAR and similar values to the ERU design structure in cases of without and with the use of an error reduction unit. Thus, in terms of normalized error detection values, the proposed adder design performs well.
Figure 14. Error rate (%) comparison of proposed adder vs GEAR bit approximate adder design comparison in terms of normalized error detection against [23], [24] considering three different window sizes. It is evident from Figure 16 results that the proposed adder design has slightly lower normalized error detection values than GeAR and similar values to the ERU design structure in cases of without and with the use of an error reduction unit. Thus, in terms of normalized error detection values, the proposed adder design performs well.
Figure 15. Average error detection comparison of proposed adder against varied adder designs
Figure 15. Average error detection comparison of proposed adder against varied adder designs
Figure 16. Average error detection comparison of proposed adder against varied adder designs
Figure 16. Average error detection comparison of proposed adder against varied adder designs
Figure 17. Delay comparison considering proposed adder design against varied approximate adder designs Figure 17 demonstrates the performance results for the proposed 8-bit approximate adder design against varied adder designs in terms of delay (ps). It is visible from Figure 17 that an increase in the window size will increase delay for all the adder designs. This shows parameter values are different for different window sizes. However, the proposed approximate adder design shows the least delay among all the approximate adder designs.
Figure 17. Delay comparison considering proposed adder design against varied approximate adder designs Figure 17 demonstrates the performance results for the proposed 8-bit approximate adder design against varied adder designs in terms of delay (ps). It is visible from Figure 17 that an increase in the window size will increase delay for all the adder designs. This shows parameter values are different for different window sizes. However, the proposed approximate adder design shows the least delay among all the approximate adder designs.
Figure 18. Area comparison considering proposed adder design against varied approximate adder designs Figure 18 demonstrates the performance results for the proposed 8-bit approximate adder design against varied adder designs in terms of area (um7). It is visible from Figure 18 that area is different for different window sizes. However, the proposed approximate adder design requires the least area among all the approximate adder designs.
Figure 18. Area comparison considering proposed adder design against varied approximate adder designs Figure 18 demonstrates the performance results for the proposed 8-bit approximate adder design against varied adder designs in terms of area (um7). It is visible from Figure 18 that area is different for different window sizes. However, the proposed approximate adder design requires the least area among all the approximate adder designs.
Figure 19. Power comparison considering proposed adder design against varied approximate adder designs
Figure 19. Power comparison considering proposed adder design against varied approximate adder designs
Figure 20. Energy comparison considering proposed adder design against varied approximate adder designs
Figure 20. Energy comparison considering proposed adder design against varied approximate adder designs
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