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Fig. 11 Proposed circuit for hardware implementationof Sobel edge detection algorithm

Figure 11 Proposed circuit for hardware implementationof Sobel edge detection algorithm

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Please cite this article as: Nazma Nausheen, Ayan Seal, Pritee Khanna, Santanu Haldar, A FPGA based Implementation of Sobel Edge Detection, Microprocessors and Microsystems (2017), doi: 10.1016/j.micoro.2017.10.011
Please cite this article as: Nazma Nausheen, Ayan Seal, Pritee Khanna, Santanu Haldar, A FPGA based Implementation of Sobel Edge Detection, Microprocessors and Microsystems (2017), doi: 10.1016/j.micoro.2017.10.011
A FPGA based Implementation of Sobel Edge Detection presents a scope to parallelize subroutines in a program. Hence, hardware im, plementation provides much faster alternative as compared to software. In 1994 Boo et al. [3] have proposed hardware implementation of edge‘detection using Sobel operator using VLSI technology within application\specific inte- grated circuit (IC). In the past few years extensive work has been#done in the area of Field programmable Gate Array (FPGA) basedsimplementation of edge detection algorithm which in turn implements image processing in real time. In 2009 real time algorithms have been designed.to’detect edges on FPGA board [12]. Parallelism of any algorithm is.possible due to integration of large number of transistors (10k-100k) on a single silicon chip using VLSI technology [10]. All embedded systems are deSigned and implemented on Ap- plication Specific Integrated Circuit (ASIC) orN"PGA. FPGA is an IC with Configurable Logical Blocks (CLBs) [5/°CBBs are interconnected using rout- ing channels on a silicon board basedjon the desired operation. The internal connections can be configured usitig Hardware Description Languages (HDL) like VHDL [9] or Verilog. The silicon board consists of input/output ports on the boundary to take the input andyprovide the output as shown in figure 1. These HDLs provide a medium of simulation of the designed IC to see if anything can go wrong.These programmed ICs are emulated on FPGA board after correct simulation. Iu 2007, T.A.Abbasi et al. [1] presented an architec- ture for Sobel edgé detection on FPGA. Later in 2012, this architecture was found to be inefficient with respect to space and time complexity by S.Halder et al. [8]. Architecture proposed by them saved time and took lesser space than the architeéture proposed by T.A.Abbasi et al. [1]. However, this architecture also had/disadvantages of redundant storage of pixels and also there is scope of reductionjin the architecture. The motivation of proposed work is to overcome thes@eshortcomings of architecture proposed in [8]. The contributions of the present’ work are as follows:
A FPGA based Implementation of Sobel Edge Detection presents a scope to parallelize subroutines in a program. Hence, hardware im, plementation provides much faster alternative as compared to software. In 1994 Boo et al. [3] have proposed hardware implementation of edge‘detection using Sobel operator using VLSI technology within application\specific inte- grated circuit (IC). In the past few years extensive work has been#done in the area of Field programmable Gate Array (FPGA) basedsimplementation of edge detection algorithm which in turn implements image processing in real time. In 2009 real time algorithms have been designed.to’detect edges on FPGA board [12]. Parallelism of any algorithm is.possible due to integration of large number of transistors (10k-100k) on a single silicon chip using VLSI technology [10]. All embedded systems are deSigned and implemented on Ap- plication Specific Integrated Circuit (ASIC) orN"PGA. FPGA is an IC with Configurable Logical Blocks (CLBs) [5/°CBBs are interconnected using rout- ing channels on a silicon board basedjon the desired operation. The internal connections can be configured usitig Hardware Description Languages (HDL) like VHDL [9] or Verilog. The silicon board consists of input/output ports on the boundary to take the input andyprovide the output as shown in figure 1. These HDLs provide a medium of simulation of the designed IC to see if anything can go wrong.These programmed ICs are emulated on FPGA board after correct simulation. Iu 2007, T.A.Abbasi et al. [1] presented an architec- ture for Sobel edgé detection on FPGA. Later in 2012, this architecture was found to be inefficient with respect to space and time complexity by S.Halder et al. [8]. Architecture proposed by them saved time and took lesser space than the architeéture proposed by T.A.Abbasi et al. [1]. However, this architecture also had/disadvantages of redundant storage of pixels and also there is scope of reductionjin the architecture. The motivation of proposed work is to overcome thes@eshortcomings of architecture proposed in [8]. The contributions of the present’ work are as follows:
Nazma Nausheen et al. Fig. 3 An image J stored as two-dimensional array, ‘A’, with m rows and n columns
Nazma Nausheen et al. Fig. 3 An image J stored as two-dimensional array, ‘A’, with m rows and n columns
Fig. 8 A FPGA based architecture for extraction of indices A FPGA based Implementation of Sobel Edge Detection
Fig. 8 A FPGA based architecture for extraction of indices A FPGA based Implementation of Sobel Edge Detection
Fig. 10 Architecture for comparison with Threshold
Fig. 10 Architecture for comparison with Threshold
Table 1 Device Utilisation Summary The proposed architecture of Sobel edge detection uses direct indexing of de- sired pixelstunlike the redundant storage of sub-window pixels as in the previ- ous architectures thus reducing space complexity. The circuit is able to perform at a faster.frequency than existing designs. Hence, the time to process an im- age isaless comparatively. When this architecture is used for large databases it will show @ significant difference. The time complexity of the proposed algo-
Table 1 Device Utilisation Summary The proposed architecture of Sobel edge detection uses direct indexing of de- sired pixelstunlike the redundant storage of sub-window pixels as in the previ- ous architectures thus reducing space complexity. The circuit is able to perform at a faster.frequency than existing designs. Hence, the time to process an im- age isaless comparatively. When this architecture is used for large databases it will show @ significant difference. The time complexity of the proposed algo-
Related topics:
Computer ScienceComputer HardwareField Programmable Gate ArrayElectrical and Electronic EngineeringSobel operator
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