Academia.eduAcademia.edu

Figure 8 – uploaded by xuan hien ngo

See full PDFdownloadDownload figure
Figure 8. Pixelwise difference of AES layouts with 50% core utilization rate for Original layout and Infected Layout with (a) 1 AND gate, (b) 128 AND gate.

Figure 8 Pixelwise difference of AES layouts with 50% core utilization rate for Original layout and Infected Layout with (a) 1 AND gate, (b) 128 AND gate.

Related Figures (12)

‘Corresponding author. Figure 1. Minimalist Hardware Trojan Horse example attacker can change a design netlist or subvert the fabrication process by manipulating design masks, without affecting the main functionality of the design [2].
‘Corresponding author. Figure 1. Minimalist Hardware Trojan Horse example attacker can change a design netlist or subvert the fabrication process by manipulating design masks, without affecting the main functionality of the design [2].
Figure 2. Effect of a fault in last but one round of AES-128.
Figure 2. Effect of a fault in last but one round of AES-128.
Figure 3. Differential Fault Analysis (DFA) based HTH in AES — Illustration of a remote DFA enabled by the HTH
Figure 3. Differential Fault Analysis (DFA) based HTH in AES — Illustration of a remote DFA enabled by the HTH
USAGE OF ROUTING RESOURCES PER LAYER FOR THE AES CASE-STUDY WITH 95% CORE UTILIZATION RATE
USAGE OF ROUTING RESOURCES PER LAYER FOR THE AES CASE-STUDY WITH 95% CORE UTILIZATION RATE
Figure 4. Picture (left hand side) and GDSII layout (right hand side — M6 in orange for Middle and Side of the module, M5 in yellow for Side of the module) of an AES-128 cryptographic accelerator (area size: 67 zm x 60 yum)
Figure 4. Picture (left hand side) and GDSII layout (right hand side — M6 in orange for Middle and Side of the module, M5 in yellow for Side of the module) of an AES-128 cryptographic accelerator (area size: 67 zm x 60 yum)
Figure 5. HTH with N — 1 AND gates (AND tree) inserted in AES circuit
Figure 5. HTH with N — 1 AND gates (AND tree) inserted in AES circuit
Figure 6. 6th metal layer AES layouts (1200 wm x 1200 wm) with 50% core utilization rate for (a) Original AES, (b) AES with 1 AND gate HTH, (c) AE with 128 AND gate HTH
Figure 6. 6th metal layer AES layouts (1200 wm x 1200 wm) with 50% core utilization rate for (a) Original AES, (b) AES with 1 AND gate HTH, (c) AE with 128 AND gate HTH
Figure 7. AES layouts (1200 um x 1200 wm) with 50% core utilization rate for (a) Original AES, (b) AES with 1 AND gate HTH, (c) AES with 128 ANL gate HTH
Figure 7. AES layouts (1200 um x 1200 wm) with 50% core utilization rate for (a) Original AES, (b) AES with 1 AND gate HTH, (c) AES with 128 ANL gate HTH
CosT AND PERFORMANCE OVERHEAD OF THE INSERTED HTH oF Size N = 16 Tab IV compares the cost and performance of a HTH as described before which gets activated when the first two bytes of the plaintext are equal to Oxff i.e. N = 16. The HTH is very small i.e. only 10 LUTs and causes speed degradation of 1.6% (indeed, our HTH adds one XOR gate on the critical path). This configuration helps us to easily implement Piret’s Attack. Recall that the signal activation_cond[Q] is an input of the trigger part of the HTH; thus both a faulted and a fault-free ciphertext can be obtained (which is required for the DFA of Piret and Quisquater). In Tab V, we give the transcript of an example of the Piret’s Attack on an AES implementation with our inserted HTH. Table IV We implemented a HTH in an AES coprocessor to facilitate Piret’s DFA. The HTH gets activated when the switch is on and the first two bytes of the plaintext are equal to Oxff; it is thus an instantiation of the generic HTH depicted in Fig. 3 with parameter N set to 16. This configuration leads us to a unique key in a total of 4 encryptions. The key used in our example is same as in Appendix B of the AES standard [28]. The design is tested on a SASEBO-GII board running on the Virtex-5 FPGA.
CosT AND PERFORMANCE OVERHEAD OF THE INSERTED HTH oF Size N = 16 Tab IV compares the cost and performance of a HTH as described before which gets activated when the first two bytes of the plaintext are equal to Oxff i.e. N = 16. The HTH is very small i.e. only 10 LUTs and causes speed degradation of 1.6% (indeed, our HTH adds one XOR gate on the critical path). This configuration helps us to easily implement Piret’s Attack. Recall that the signal activation_cond[Q] is an input of the trigger part of the HTH; thus both a faulted and a fault-free ciphertext can be obtained (which is required for the DFA of Piret and Quisquater). In Tab V, we give the transcript of an example of the Piret’s Attack on an AES implementation with our inserted HTH. Table IV We implemented a HTH in an AES coprocessor to facilitate Piret’s DFA. The HTH gets activated when the switch is on and the first two bytes of the plaintext are equal to Oxff; it is thus an instantiation of the generic HTH depicted in Fig. 3 with parameter N set to 16. This configuration leads us to a unique key in a total of 4 encryptions. The key used in our example is same as in Appendix B of the AES standard [28]. The design is tested on a SASEBO-GII board running on the Virtex-5 FPGA.
Figure 9. Grid-wise RNCC of AES layouts for with 50% core utilization rate for Original layout and Infected Layout with (a) 1 AND gate, (b) 128 ANI gate.
Figure 9. Grid-wise RNCC of AES layouts for with 50% core utilization rate for Original layout and Infected Layout with (a) 1 AND gate, (b) 128 ANI gate.
Figure 10. Grid-wise RNCC of AES layouts for with 95% core utilization rate for Original layout and Infected Layout with (a) 1 AND gate, (b) 128 ANI gate.
Figure 10. Grid-wise RNCC of AES layouts for with 95% core utilization rate for Original layout and Infected Layout with (a) 1 AND gate, (b) 128 ANI gate.
Related topics:
Computer ScienceCryptographyLogic circuits
580 California St., Suite 400
San Francisco, CA, 94104
© 2025 Academia. All rights reserved