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en ee  To develop new hardware in the VHDL design environment, first a VHDL ource code is developed. The VHDL source code specifies the performance re- juirements of the target hardware system. It can be at one or more levels of a ystem design hierarchy such as system level, component level, logic level, gate evel, or below. The VHDL analyzer translates the source code into an intermedi- te form known as the abstract syntax tree (AST) which is incorporated into the lesign library. Based on user instructions, the profiler generates an AST represen- ation which reflects the correct configuration (i.e. entities with the correct revisions elected). The output of the profiler is incorporated into the design library and pre- ented to the hardware synthesizer tool. The hardware synthesizer then produces a ircuit design.

Figure 33 en ee To develop new hardware in the VHDL design environment, first a VHDL ource code is developed. The VHDL source code specifies the performance re- juirements of the target hardware system. It can be at one or more levels of a ystem design hierarchy such as system level, component level, logic level, gate evel, or below. The VHDL analyzer translates the source code into an intermedi- te form known as the abstract syntax tree (AST) which is incorporated into the lesign library. Based on user instructions, the profiler generates an AST represen- ation which reflects the correct configuration (i.e. entities with the correct revisions elected). The output of the profiler is incorporated into the design library and pre- ented to the hardware synthesizer tool. The hardware synthesizer then produces a ircuit design.