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Figure.3. Simulink Model for Bulk and Fractional Delay

Figure 3 3. Simulink Model for Bulk and Fractional Delay

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Figure.2. Architecture of Digital Beamformer Architecture In this paper we discuss about a dynamic digital beamformer for an ultrasound system which is resource- optimized, based on a FPGA[3]. A 64-channel receive beamformer is implemented on the FPGA (Altera Arria V Family). A novel method to achieve resource optimization and to improve spatial and contrast resolution, here we used a full dynamic beamforming. The above mentioned architecture is implemented by summing the bulk (coarse) delay and fractional (fine) delay. A frequency 40 MHz is used as sampling frequency and the beamformer has a enhanced the temporal resolution which is achieved by a 240 MHz poly phase filter, while we do some relaxing on the Analog-to-Digital converter (ADC) bandwidth requirement.
Figure.2. Architecture of Digital Beamformer Architecture In this paper we discuss about a dynamic digital beamformer for an ultrasound system which is resource- optimized, based on a FPGA[3]. A 64-channel receive beamformer is implemented on the FPGA (Altera Arria V Family). A novel method to achieve resource optimization and to improve spatial and contrast resolution, here we used a full dynamic beamforming. The above mentioned architecture is implemented by summing the bulk (coarse) delay and fractional (fine) delay. A frequency 40 MHz is used as sampling frequency and the beamformer has a enhanced the temporal resolution which is achieved by a 240 MHz poly phase filter, while we do some relaxing on the Analog-to-Digital converter (ADC) bandwidth requirement.
transition between two states. Dynamic receive focusing can be implemented with integer multiples of 0.5 mm step as the structure demands re-configuration. The maximum dept h for dynamic focusing is 8 mm as we use 16 states each of 0.5 mm step. The FD filters outputs are summed to obtain the Final beamformed data. The Hardware com com plexity of the 16 channel beamformer is very less pared to standard beamformers.
transition between two states. Dynamic receive focusing can be implemented with integer multiples of 0.5 mm step as the structure demands re-configuration. The maximum dept h for dynamic focusing is 8 mm as we use 16 states each of 0.5 mm step. The FD filters outputs are summed to obtain the Final beamformed data. The Hardware com com plexity of the 16 channel beamformer is very less pared to standard beamformers.
Figure.6 Coarse Delay Structure.
Figure.6 Coarse Delay Structure.
We have to choose the FPGA for realization of the delay pulse circuit with great care. We need one which is having shortest delays of intrinsic gates and interconnection. FPGA should have appropriate granularity and functionality of the basic logic blocks[6]. It should have a PLL which is built in, which supports advanced clock shift capability to provide programmable phase shifting. The architecture is depicted in the Figure 9. The input to PLL is a clk-25MHz clock, the outputs are three clock signals with a period of 6 ns. They are clk-out [0] (with 0 degree phase shift), clk-out [1] (with 60 degree phase shift) and clk-out [2] (with 120 degree phase shift) respectively. Three clock signals are derived from these with a period of 6 ns by inverting each of them . The clocks are named as clk-out [3] (with 180 degree phase shift), clk-out [4] (with 240 degree phase shift) and clk-out [5] (with 300 degree phase shift) respectively. In order to achieve a Ins time resolution, each of the six clock signals clk-out [0,..., 5] has a period of 6ns but separated by Ins from each other. Ins time resolution is obtained using PLL and inverters by using the above architecture. Figure.9 FPGA Delay Pulse Circuit with Ins Resolution.
We have to choose the FPGA for realization of the delay pulse circuit with great care. We need one which is having shortest delays of intrinsic gates and interconnection. FPGA should have appropriate granularity and functionality of the basic logic blocks[6]. It should have a PLL which is built in, which supports advanced clock shift capability to provide programmable phase shifting. The architecture is depicted in the Figure 9. The input to PLL is a clk-25MHz clock, the outputs are three clock signals with a period of 6 ns. They are clk-out [0] (with 0 degree phase shift), clk-out [1] (with 60 degree phase shift) and clk-out [2] (with 120 degree phase shift) respectively. Three clock signals are derived from these with a period of 6 ns by inverting each of them . The clocks are named as clk-out [3] (with 180 degree phase shift), clk-out [4] (with 240 degree phase shift) and clk-out [5] (with 300 degree phase shift) respectively. In order to achieve a Ins time resolution, each of the six clock signals clk-out [0,..., 5] has a period of 6ns but separated by Ins from each other. Ins time resolution is obtained using PLL and inverters by using the above architecture. Figure.9 FPGA Delay Pulse Circuit with Ins Resolution.
A low cost FPGA is selected to implement this circuit. A. The results of the simulation and its comparison with standard circuits show that a considerable improvement is there in the performance. A uniform sampling clock is used to spilt the delay of the beamformer into an integer multiple and a fractional part of the sampling period, we implemented the integral part with a memory delay line and the fractional part can be realized by interpolation filtering.
A low cost FPGA is selected to implement this circuit. A. The results of the simulation and its comparison with standard circuits show that a considerable improvement is there in the performance. A uniform sampling clock is used to spilt the delay of the beamformer into an integer multiple and a fractional part of the sampling period, we implemented the integral part with a memory delay line and the fractional part can be realized by interpolation filtering.
The receive beamforming architecture is shown as Figure 11. This design employs the phase shifting with the PLL to meet the resolution requirements, since PLL is built-in inside FPGA no extra logic is required for achieving this. The coarse and fine delays blocks are having the same architecture as transmit block. 1/4 frequency divider is used to derive the sample clock for our A/D converter. FIFO registers are used to store the Analog signals that are sampled by non-uniform sampling clocks, they are summed to produce the output signal. Figure.11 Logic Structure Implemented Receive Beamformer.
The receive beamforming architecture is shown as Figure 11. This design employs the phase shifting with the PLL to meet the resolution requirements, since PLL is built-in inside FPGA no extra logic is required for achieving this. The coarse and fine delays blocks are having the same architecture as transmit block. 1/4 frequency divider is used to derive the sample clock for our A/D converter. FIFO registers are used to store the Analog signals that are sampled by non-uniform sampling clocks, they are summed to produce the output signal. Figure.11 Logic Structure Implemented Receive Beamformer.
For the Transmition we need to generate trigger pulse with Ins resolution. We use a combination of coarse and fine delay structure is adopted here. The coarse delay structure is accomplished by multiplying the signal with integer multiples of the clock periods[6]. A 16-bit counter is used to store the coarse delay. With the help of 6-to-1 clock multiplexer, we select from one of six shifted clocks and the fine delay is obtained. The appropriate clock for the counter is selected to obtain the Ins resolution.
For the Transmition we need to generate trigger pulse with Ins resolution. We use a combination of coarse and fine delay structure is adopted here. The coarse delay structure is accomplished by multiplying the signal with integer multiples of the clock periods[6]. A 16-bit counter is used to store the coarse delay. With the help of 6-to-1 clock multiplexer, we select from one of six shifted clocks and the fine delay is obtained. The appropriate clock for the counter is selected to obtain the Ins resolution.
The proposed architecture is shown in Figure 14[8]. Every transducer element emits an RF signal s(t) on which time gain compensation is performed using a variable gain amplifier. The signal s(t) is converted to digital signal q[n] in the DSM block, which is then passed to circular buffer. We then multiply the signal with apodization coefficient ie weights of that channel and then summed accordingly from all channels. The summed output is then filtered to get in-phase and the quadrature components sI[n] and sQ[n] respectively. VII.CONCLUSION
The proposed architecture is shown in Figure 14[8]. Every transducer element emits an RF signal s(t) on which time gain compensation is performed using a variable gain amplifier. The signal s(t) is converted to digital signal q[n] in the DSM block, which is then passed to circular buffer. We then multiply the signal with apodization coefficient ie weights of that channel and then summed accordingly from all channels. The summed output is then filtered to get in-phase and the quadrature components sI[n] and sQ[n] respectively. VII.CONCLUSION
The Hybrid Beamformer (HBF), by utilizing an uniform ABF sampling system and an area efficient digital storage (FIFO) in the DBF, will reduce the area in the device. In comparison with the uniform sample ABF, this job suggests an area reduction of around 84.
The Hybrid Beamformer (HBF), by utilizing an uniform ABF sampling system and an area efficient digital storage (FIFO) in the DBF, will reduce the area in the device. In comparison with the uniform sample ABF, this job suggests an area reduction of around 84.
Related topics:
Electronic EngineeringComputer ScienceAdaptive BeamformerField Programmable Gate ArrayApplication Specific Integrated Circuit (ASIC)
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