process repeats itself many times over the course of the project. Bugs are only one source of change though. Marketing requests may also come in at any stage of the design cycle requiring the specification to change and all downstream code to be modified. Figure 1 captures this course in a flow chart. This is shown in Figure 2. The RDL file serves as a one-stop point for any register update required following a requirement change. 3.1.1 Choosing SystemRDL 4, DEMONSTRATING WITH A CSR EXAMPLE A complete VMM compliant randomized, coverage driven register verification environment can be created by extending the flow such that. Table 3: Verilog RTL Interface for CSR_EXAMPLE Table 2: RALF for CSR_EXAMPLE For each field, register, block and system component available in RALF, the RAL contains a System Verilog class. These classes are extended from RAL base classes. The attributes of the components in RALF such as base address, offset, reset value, domain name are passed to the individual classes as arguments. This RAL model can be integrated ina VMM environment for complete DUT register verification, as in Figure 4. The XL XACTOR translates the RAL commands to interface commands. The BFM uses these to drive DUT signals as per protocol. Figure 4: RAL integration in VMM environment Figure 4: RAL integration in VMM environment 2A L has several useful features that help in building verification snvironment for large and complex designs: Table 6: Interrupt Register Example RDL provides particular constructs to define registers like interrupt- enable/mask and internupt-status from which interrupt will be derived. Each bit in the interrupt status register has to be mapped with corresponding enable/mask bit in the interrupt enable/mask register using interrupt field access property enable or mask. If it is enable corresponding interrupt source is used to generate an interrupt. In case of mask, corresponding interrupt source is not used to generate an interrupt. Each fieldwidth defined in interrupt status and interrupt enable register should be 1.SystemRDL example for interrupt status and enable register and their mapping is given in Table 6.
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