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Fig. 5: L3 Contention under HWS 2 and HWS 3 Due to space constraints we analyse few configurations and interference channels. In particular, Figure 5 compares the execution time of a micro-benchmark performing sustained L3 (CPC) hits (benchL3H) by using 256KB of the IMB CPC1 with 1, 2 and 3 contenders that perform all of them either sustained CPC hits (benchL3H) or CPC misses (benchL3mem). This comparison is performed in HWS 2 and HWS 3, hence, with and without CPC partitioning.

Figure 5 L3 Contention under HWS 2 and HWS 3 Due to space constraints we analyse few configurations and interference channels. In particular, Figure 5 compares the execution time of a micro-benchmark performing sustained L3 (CPC) hits (benchL3H) by using 256KB of the IMB CPC1 with 1, 2 and 3 contenders that perform all of them either sustained CPC hits (benchL3H) or CPC misses (benchL3mem). This comparison is performed in HWS 2 and HWS 3, hence, with and without CPC partitioning.

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Fig. 1: Block diagram of the P4080 blocks we analyse
Fig. 1: Block diagram of the P4080 blocks we analyse
(a) HWS 1: Maximum HW Isolation. cO (b) HWS 2: Limited HW Isolation. CPC1 (c) HWS 3: Limited HW Isolation. CPC1 uses a private CPC/mem controller. shared and cO receives some private ways. shared among cO and cl — c3.
(a) HWS 1: Maximum HW Isolation. cO (b) HWS 2: Limited HW Isolation. CPC1 (c) HWS 3: Limited HW Isolation. CPC1 uses a private CPC/mem controller. shared and cO receives some private ways. shared among cO and cl — c3.
TABLE II: Identified P4080 Interference Channels ficiency): 1) memory controller interleaving is disabled and applications are distributed across the two memory controllers (e.g. DDR3_1 for c0 — c3 and DDR3_2 for c4 — c7); 2) CPC’ is partitioned by assigning one or more 32 KB ways to c0. As in HWS 1, these ways may be setup as SRAM, L3 cache or both. The remaining ways of CPC'1 and CPC2 may or may not be partitioned across the non-critical partitions. In particular, in CPC} we give 8 ways to cO and 24 ways (shared) to cl — c3; and 3) main memory is segregated as in HWS 1.
TABLE II: Identified P4080 Interference Channels ficiency): 1) memory controller interleaving is disabled and applications are distributed across the two memory controllers (e.g. DDR3_1 for c0 — c3 and DDR3_2 for c4 — c7); 2) CPC’ is partitioned by assigning one or more 32 KB ways to c0. As in HWS 1, these ways may be setup as SRAM, L3 cache or both. The remaining ways of CPC'1 and CPC2 may or may not be partitioned across the non-critical partitions. In particular, in CPC} we give 8 ways to cO and 24 ways (shared) to cl — c3; and 3) main memory is segregated as in HWS 1.
Fig. 3: DL1 Hit Latency variation across cores and runs.
Fig. 3: DL1 Hit Latency variation across cores and runs.
running benchDL1). Thus, all cores only exercise core local resources (i.e. DL1). Therefore, one would expect no impact of the other cores. However, as shown in Figure 4b, DLI1 hit latency increases noticeably with 1, 3, 5 and 7 contenders, but negligibly with 2, 4 and 6 contenders. While we suspect that this behaviour is produced by the coherence protocol, the snoop counter does not reveal any specific trend, so all we can state is that an unknown interference channel exists with non-obvious impact across cores.
running benchDL1). Thus, all cores only exercise core local resources (i.e. DL1). Therefore, one would expect no impact of the other cores. However, as shown in Figure 4b, DLI1 hit latency increases noticeably with 1, 3, 5 and 7 contenders, but negligibly with 2, 4 and 6 contenders. While we suspect that this behaviour is produced by the coherence protocol, the snoop counter does not reveal any specific trend, so all we can state is that an unknown interference channel exists with non-obvious impact across cores.
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Computer ScienceMulti-Core Processor
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