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FIGURE 4 shows different non-isolated and isolated switch model power supply (SMPS). At this stage of the project, different solutions have been analyzed in order to find the most suitable solution for NEWTON instrument taking into account the requirements of the three prototypes which are being developed within the project.

Figure 4 shows different non-isolated and isolated switch model power supply (SMPS). At this stage of the project, different solutions have been analyzed in order to find the most suitable solution for NEWTON instrument taking into account the requirements of the three prototypes which are being developed within the project.

Related Figures (58)

D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block FIGURE 1. Block Diagram of the NEWTON muti-sensor instrument for prototype 1 and prototype 2.
D3.3 - Preliminary design report for the power distribution block FIGURE 1. Block Diagram of the NEWTON muti-sensor instrument for prototype 1 and prototype 2.
FIGURE 2. Block Diagram of the NEWTON multi-sensor instrument for prototype 3.
FIGURE 2. Block Diagram of the NEWTON multi-sensor instrument for prototype 3.
TABLE 1. Requirements for the design of the PDU.
TABLE 1. Requirements for the design of the PDU.
FIGURE 3 shows the block diagram of the DC/DC converter. As it can be seen, the converter receives the primary power from the rover in the case of prototype 1 and 3, and from external batteries in the case of prototype 2, and provides three different output voltages with different power consumptions which interface with the sensor unit and the electronic control block respectively. As already mentioned in section 2, prototype 1 and 2 will be tested in field campaigns on different scientific demonstrations sites so external portable batteries will be used to emulate the primary power. In the case of prototype 3, which will be tested on the laboratory, commercial power sources will be used. Although, there is no concrete requirements in terms of efficiency, the target is to achieve maximum efficiency (>90%) in order to save a maximum electrical power due to the scenarios of application of all prototypes are a limited energy scenario. Similarly, there is no concrete requirements with respect to size and weight. However, the target is also to reduce the size and weight of the conversor while the efficiency is maximized.
FIGURE 3 shows the block diagram of the DC/DC converter. As it can be seen, the converter receives the primary power from the rover in the case of prototype 1 and 3, and from external batteries in the case of prototype 2, and provides three different output voltages with different power consumptions which interface with the sensor unit and the electronic control block respectively. As already mentioned in section 2, prototype 1 and 2 will be tested in field campaigns on different scientific demonstrations sites so external portable batteries will be used to emulate the primary power. In the case of prototype 3, which will be tested on the laboratory, commercial power sources will be used. Although, there is no concrete requirements in terms of efficiency, the target is to achieve maximum efficiency (>90%) in order to save a maximum electrical power due to the scenarios of application of all prototypes are a limited energy scenario. Similarly, there is no concrete requirements with respect to size and weight. However, the target is also to reduce the size and weight of the conversor while the efficiency is maximized.
D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block
TABLE 3. Comparative analysis between Flyback and Forward converters. DOUBLE-ENDED CONVERTERS (MEDIUM POWER): HALF-BRIDGE VS PUSH-PULL D3.3 - Preliminary design report for the power distribution block
TABLE 3. Comparative analysis between Flyback and Forward converters. DOUBLE-ENDED CONVERTERS (MEDIUM POWER): HALF-BRIDGE VS PUSH-PULL D3.3 - Preliminary design report for the power distribution block
FIGURE 5. Flyback circuit configuration. The Flyback is the simplest and most common of the isolated topologies for low-power (5-150W) and low cost with possibly the lower component count. The output voltage isolation is guaranteed with two coupled inductances, a primary inductance, L,, and a secondary inductance, L;. On the input side there is only one winding, Lp, which means that only one power transistor is required. On the output side there is only the output capacitor, C,, and one switch, which can be a power diode or a power transistor in the case of synchronous rectification. Therefore, there is no need to use an external inductor to filter the output voltage, which means less space required.
FIGURE 5. Flyback circuit configuration. The Flyback is the simplest and most common of the isolated topologies for low-power (5-150W) and low cost with possibly the lower component count. The output voltage isolation is guaranteed with two coupled inductances, a primary inductance, L,, and a secondary inductance, L;. On the input side there is only one winding, Lp, which means that only one power transistor is required. On the output side there is only the output capacitor, C,, and one switch, which can be a power diode or a power transistor in the case of synchronous rectification. Therefore, there is no need to use an external inductor to filter the output voltage, which means less space required.
As it’s shown in FIGURE 6, during t., energy is stored in the transformer magnetic core through L, inductance, while the output capacitor delivers energy to the load. During to; the energy stored in the core is transferred to the output, resulting on a current in Ls inductance which forward-biases the output diode and delivers current to the load while charging the output capacitor as well. FIGURE 7 shows some waveforms present in the Flyback converter operation depending on the state of the switch. FIGURE 6. Flyback converter operation: On-state (switch closed) and Off-state (switch open).
As it’s shown in FIGURE 6, during t., energy is stored in the transformer magnetic core through L, inductance, while the output capacitor delivers energy to the load. During to; the energy stored in the core is transferred to the output, resulting on a current in Ls inductance which forward-biases the output diode and delivers current to the load while charging the output capacitor as well. FIGURE 7 shows some waveforms present in the Flyback converter operation depending on the state of the switch. FIGURE 6. Flyback converter operation: On-state (switch closed) and Off-state (switch open).
TABLE 4. Comparative analysis between CCM and DCM Flyback converters. Flyback converters have two basic energy-transfer modes of operation: Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). In DCM, the Flyback period will continue till the output winding current drops to zero, so that all the stored energy in the Flyback transformer is transferred to the load. On the contrary, in the CCM, there is some residual energy stored in the transformer at the end of the ON and OFF periods. In general, DCM is recommended for high voltage and low current output applications while CCM is preferred for low voltage and high current applications. A comparison between CCM and DCM is presented in TABLE 4.
TABLE 4. Comparative analysis between CCM and DCM Flyback converters. Flyback converters have two basic energy-transfer modes of operation: Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). In DCM, the Flyback period will continue till the output winding current drops to zero, so that all the stored energy in the Flyback transformer is transferred to the load. On the contrary, in the CCM, there is some residual energy stored in the transformer at the end of the ON and OFF periods. In general, DCM is recommended for high voltage and low current output applications while CCM is preferred for low voltage and high current applications. A comparison between CCM and DCM is presented in TABLE 4.
Taking into account the analysis presented above, a Flyback operating in CCM is selected for its implementation. FIGURE 8 illustrates the block diagram and the schematic of the Flyback DC/DC converter.
Taking into account the analysis presented above, a Flyback operating in CCM is selected for its implementation. FIGURE 8 illustrates the block diagram and the schematic of the Flyback DC/DC converter.
aim of activating the clamping circuit as soon as possible. FIGURE 9 shows the circuits and Vd: waveform. In some occasions, and depending of the transformer manufacture, the leakage inductance could be placed in the secondary side, affecting the voltage over the rectifier. Due to the parasitic of the output diode (commonly a capacitance in parallel) and that undesired and not-coupled induction an oscillation or transient could happen in Vd. As shown in FIGURE 10 this effect can be minimized by placing a RC circuit to snub that overvoltage oscillation. D3.3 - Preliminary design report for the power distribution block
aim of activating the clamping circuit as soon as possible. FIGURE 9 shows the circuits and Vd: waveform. In some occasions, and depending of the transformer manufacture, the leakage inductance could be placed in the secondary side, affecting the voltage over the rectifier. Due to the parasitic of the output diode (commonly a capacitance in parallel) and that undesired and not-coupled induction an oscillation or transient could happen in Vd. As shown in FIGURE 10 this effect can be minimized by placing a RC circuit to snub that overvoltage oscillation. D3.3 - Preliminary design report for the power distribution block
FIGURE 12. Opto-coupler and feedback circuitry.
FIGURE 12. Opto-coupler and feedback circuitry.
The evaluation of the Flyback converter has been carried out using PSPICE simulator. FIGURE 13 shows the schematic used in the simulations. Simulations have been done with non-ideal components excluding feedback. FIGURE 13. Schematic of the Flyback converter (open loop simulation).
The evaluation of the Flyback converter has been carried out using PSPICE simulator. FIGURE 13 shows the schematic used in the simulations. Simulations have been done with non-ideal components excluding feedback. FIGURE 13. Schematic of the Flyback converter (open loop simulation).
D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block
FIGURE 16. Basic schematic of the Half-bridge converter.
FIGURE 16. Basic schematic of the Half-bridge converter.
D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block
FIGURE 18. Simulation schematic of the Half-bridge converter. D3.3 - Preliminary design report for the power distribution block
FIGURE 18. Simulation schematic of the Half-bridge converter. D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block FIGURE 21. Basic circuit configuration of a buck converter.
D3.3 - Preliminary design report for the power distribution block FIGURE 21. Basic circuit configuration of a buck converter.
FIGURE 22. Buck converter operation: On-state (switch closed) and Off-state (switch open).
FIGURE 22. Buck converter operation: On-state (switch closed) and Off-state (switch open).
At this point, a synchronous buck converter operating in continuous conduction mode is considered. The inductor current is continuous and never reaches zero during one switching period (Ts), the relation between output and input voltage is given by:
At this point, a synchronous buck converter operating in continuous conduction mode is considered. The inductor current is continuous and never reaches zero during one switching period (Ts), the relation between output and input voltage is given by:
FIGURE 24 shows the basic schematic of a synchronous buck converter. As can be seen, it is composed by two MOSFET, and output inductor and output capacitors.Q1, is connected directly to the input voltage circuit. When Q1 turns on, IUPPER is supplied to the load through Q1. During this time, the current through the inductor increases and Q2 is off. When Q1 turns off, Q2 turns on and ILOWER is supplied to the load through Q2. During this time, the inductor current decreases [10],[11]. At this stage of the project, a commercial solution based on GaN technology has been used to validate the concept and to analyzed experimentally the advantages and disadvantages of the buck converter. This solution is based on GaN-on silicon E-HEMT transistor (GS61008P). The properties of GaN allow for high current, high voltage breakdown and high switching frequency which combine to provide very high efficiency power switching. The validation of the concept has been carried out by means of using a demo board of a synchronous buck DC/DC converter provided by GaN Systems [12]. This demo board comprises a universal GaN half bridge with open loop control and on-board PWM dead time generation which is used to implement a 48-12V synchronous buck DC/DC conversor. The circuit schematic of the evaluation board is shown in FIGURE 25.
FIGURE 24 shows the basic schematic of a synchronous buck converter. As can be seen, it is composed by two MOSFET, and output inductor and output capacitors.Q1, is connected directly to the input voltage circuit. When Q1 turns on, IUPPER is supplied to the load through Q1. During this time, the current through the inductor increases and Q2 is off. When Q1 turns off, Q2 turns on and ILOWER is supplied to the load through Q2. During this time, the inductor current decreases [10],[11]. At this stage of the project, a commercial solution based on GaN technology has been used to validate the concept and to analyzed experimentally the advantages and disadvantages of the buck converter. This solution is based on GaN-on silicon E-HEMT transistor (GS61008P). The properties of GaN allow for high current, high voltage breakdown and high switching frequency which combine to provide very high efficiency power switching. The validation of the concept has been carried out by means of using a demo board of a synchronous buck DC/DC converter provided by GaN Systems [12]. This demo board comprises a universal GaN half bridge with open loop control and on-board PWM dead time generation which is used to implement a 48-12V synchronous buck DC/DC conversor. The circuit schematic of the evaluation board is shown in FIGURE 25.
D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block
TABLE 5. Interfaces of the DC/DC converter. 3.2. AC CURRENT POWER SOURCE (Prototype 3) At this stage of the project, the preliminary interfaces defined in TABLE 5 have been defined. As already indicated in section 2, the PDU of the NEWTON instrument is composed of the DC/DC conversor and the AC current source. The AC current source drives the primary winding of the sensor unit. In the case of prototype 1 and 2, it is not required to implement an individual AC current source, therefore the generation of the AC current will be implemented as part of the Electronic Control Unit by means of using a frequency generator and an external amplifier placed in the Sensor Unit. In the case of prototype 3, the demand of the AC current needs and ad hoc development, which is based on a Full-Bridge switching as described in this section. In this preliminary stage, the design of this source has been developed. D3.3 - Preliminary design report for the power distribution block
TABLE 5. Interfaces of the DC/DC converter. 3.2. AC CURRENT POWER SOURCE (Prototype 3) At this stage of the project, the preliminary interfaces defined in TABLE 5 have been defined. As already indicated in section 2, the PDU of the NEWTON instrument is composed of the DC/DC conversor and the AC current source. The AC current source drives the primary winding of the sensor unit. In the case of prototype 1 and 2, it is not required to implement an individual AC current source, therefore the generation of the AC current will be implemented as part of the Electronic Control Unit by means of using a frequency generator and an external amplifier placed in the Sensor Unit. In the case of prototype 3, the demand of the AC current needs and ad hoc development, which is based on a Full-Bridge switching as described in this section. In this preliminary stage, the design of this source has been developed. D3.3 - Preliminary design report for the power distribution block
2. LEVEL 2 - INTELLIGENT POWER INTEGRATION (PROPORTIONAL CONTROL): This integration level add: additional digital control to the standard analog design and Level 1 basic control features to actively adjust the output voltage, voltage limits, current limits and thermal limits. At this level, most of the operating parameters of the analog power supply can be digitally controlled and monitored. For instance, the output voltage can be fine-tuned to provide coordination between multiple power supplies in a system. Depending on the system I/O requirements, 8-bit solutions, like in the PIC12, PIC16 or PIC18 device families, car provide good performance, while larger systems may require the flexibility of a 16 bit microcontroller, as the included in PIC24 family. Intelligence can be added to an existing power supply design with minimal modifications. Level integration typically involves monitoring and basic control functions, so microcontrollers which integra‘ voltage comparators and ADCs are good choices. Additionally, communications peripherals may k required. Many microcontrollers, as Microchip's PICLOF and PIC12F 8-bit low pin count and small packag microcontrollers with built-in peripherals, such as ADC, PWM and GPIOs, can make the existing analc oower supplies intelligent by controlling the output sequencing and monitoring of input/output voltag: current and temperature.
2. LEVEL 2 - INTELLIGENT POWER INTEGRATION (PROPORTIONAL CONTROL): This integration level add: additional digital control to the standard analog design and Level 1 basic control features to actively adjust the output voltage, voltage limits, current limits and thermal limits. At this level, most of the operating parameters of the analog power supply can be digitally controlled and monitored. For instance, the output voltage can be fine-tuned to provide coordination between multiple power supplies in a system. Depending on the system I/O requirements, 8-bit solutions, like in the PIC12, PIC16 or PIC18 device families, car provide good performance, while larger systems may require the flexibility of a 16 bit microcontroller, as the included in PIC24 family. Intelligence can be added to an existing power supply design with minimal modifications. Level integration typically involves monitoring and basic control functions, so microcontrollers which integra‘ voltage comparators and ADCs are good choices. Additionally, communications peripherals may k required. Many microcontrollers, as Microchip's PICLOF and PIC12F 8-bit low pin count and small packag microcontrollers with built-in peripherals, such as ADC, PWM and GPIOs, can make the existing analc oower supplies intelligent by controlling the output sequencing and monitoring of input/output voltag: current and temperature.
A Level 2 control system has much greater integration with the power supply and allows better power supply environment monitoring. Integrated comparators can also be used to ensure fast response to system events or faults. A PWM peripheral is used to provide direct control of the analog PWM circuitry of the power unit, and can control the power-up conditions to provide soft-start. The MCU can monitor the power supply input current during the soft-start to ensure that components are not over-stressed. Serial
A Level 2 control system has much greater integration with the power supply and allows better power supply environment monitoring. Integrated comparators can also be used to ensure fast response to system events or faults. A PWM peripheral is used to provide direct control of the analog PWM circuitry of the power unit, and can control the power-up conditions to provide soft-start. The MCU can monitor the power supply input current during the soft-start to ensure that components are not over-stressed. Serial
=: 3. LEVEL 3 - INTELLIGENT POWER INTEGRATION (TOPOLOGY CONTROL): In addition to Level 1 and Level 2 features, this level permits the standard analog design to be reconfigured, including changing the analog loop configuration and alternating between two different analog control loop filters. For example, a power supply can change from a PWM control loop to a hysteretic control loop at light loads, thereby increasing system efficiency. Switching frequency adjustment can also be used to minimize losses. Microchip's entire range of PIC® MCUs and dsPIC® DSCs can assist in Level 3 control applications. communication peripherals allow coordination from a host device, control and monitoring of cooling fan and temperature sensors.
=: 3. LEVEL 3 - INTELLIGENT POWER INTEGRATION (TOPOLOGY CONTROL): In addition to Level 1 and Level 2 features, this level permits the standard analog design to be reconfigured, including changing the analog loop configuration and alternating between two different analog control loop filters. For example, a power supply can change from a PWM control loop to a hysteretic control loop at light loads, thereby increasing system efficiency. Switching frequency adjustment can also be used to minimize losses. Microchip's entire range of PIC® MCUs and dsPIC® DSCs can assist in Level 3 control applications. communication peripherals allow coordination from a host device, control and monitoring of cooling fan and temperature sensors.
For instance, Microchip’s family of Digitally-Enhanced Power Solution offer a Programmable, Hybrid Power Controller combining a mid-voltage analog power stage (including analog control loop, MOSFET drivers, and sensing) with a microcontroller, enabling a user-configurable power converter. So, as an example, the PIC16F785 can be used in a Level 3 application due to the on-chip analog peripherals. The device has two analog PWM modules that can control power stages. Two error amplifiers and two high-speed comparators
For instance, Microchip’s family of Digitally-Enhanced Power Solution offer a Programmable, Hybrid Power Controller combining a mid-voltage analog power stage (including analog control loop, MOSFET drivers, and sensing) with a microcontroller, enabling a user-configurable power converter. So, as an example, the PIC16F785 can be used in a Level 3 application due to the on-chip analog peripherals. The device has two analog PWM modules that can control power stages. Two error amplifiers and two high-speed comparators
1. LEVEL 4 - FULL DC/DC CONVERSION: Full digital control replaces the standard analog design and also provides the power management functions of Levels 1-3 integration. 1 The power supply regulation unction is directly controlled by the digital circuits on the processor and the software running on the rocessor. The full digital solution allows the designer to employ techniques t hat are not possible with the inalog solution, including proprietary digital compensation algorithms and non-linear control techniques. The full digital solution enables a customized response to power input change or load change events, which -an lower system cost and increase system efficiency. Microchip's 16-bit ds solution. Feedback from the power supply is obtained using high-speed -ontrolled using specialized high-speed PWM peripherals. The PWM module dower supply topologies and the CPU core allows digital compensation algori PIC DSCs enable the Level 4 ADCs. The power supply is can directly drive all popular thms to be executed quickly. isPIC DSCs can be used for various power conversion and power control applications, and they offer higher Jower densitv. lower svstem cost improved reliahility. and lower manufacturing and maintenance cost.
1. LEVEL 4 - FULL DC/DC CONVERSION: Full digital control replaces the standard analog design and also provides the power management functions of Levels 1-3 integration. 1 The power supply regulation unction is directly controlled by the digital circuits on the processor and the software running on the rocessor. The full digital solution allows the designer to employ techniques t hat are not possible with the inalog solution, including proprietary digital compensation algorithms and non-linear control techniques. The full digital solution enables a customized response to power input change or load change events, which -an lower system cost and increase system efficiency. Microchip's 16-bit ds solution. Feedback from the power supply is obtained using high-speed -ontrolled using specialized high-speed PWM peripherals. The PWM module dower supply topologies and the CPU core allows digital compensation algori PIC DSCs enable the Level 4 ADCs. The power supply is can directly drive all popular thms to be executed quickly. isPIC DSCs can be used for various power conversion and power control applications, and they offer higher Jower densitv. lower svstem cost improved reliahility. and lower manufacturing and maintenance cost.
FIGURE 33. Level 3 - Basic elements.
FIGURE 33. Level 3 - Basic elements.
e PFC with Advanced Digital Control: Power Factor Correction (PFC) is essential in higher wattage power supplies to reduce harmonic contents, system losses and radiated emissions. In this example, the dsPIC DSC simplifies implementing Boost-PFC algorithms with the Average Current Mode Control technique. The current signal is calculated digitally by computing the product of the rectified input voltage, the output of voltage error compensator and output of voltage feed-forward compensator. Implementing the digital PFC function uses little of the DSC resources, leaving plenty of additional capability to perform the rest of the primary side control. e AC-DC Conversion with Completed Digital Control: To design an efficient, reliable, cost effective AC-DC power supply with advanced features, the family of dsPIC DSCs can help optimize design cycles effectively. The high-speed PWM module with multiple advanced operating modes helps implement various advanced conversion stages such as PFC, phase shift, zero voltage, transition converter with full- bridge conversion and synchronous rectification and multi-phase buck converters. The microcontroller’s high-speed ADC can be triggered on an edge of the PWM to sample the various voltages and currents for high speed processing. The high-performance CPU helps in implementing advanced PID digital control loops and compensators in software.
e PFC with Advanced Digital Control: Power Factor Correction (PFC) is essential in higher wattage power supplies to reduce harmonic contents, system losses and radiated emissions. In this example, the dsPIC DSC simplifies implementing Boost-PFC algorithms with the Average Current Mode Control technique. The current signal is calculated digitally by computing the product of the rectified input voltage, the output of voltage error compensator and output of voltage feed-forward compensator. Implementing the digital PFC function uses little of the DSC resources, leaving plenty of additional capability to perform the rest of the primary side control. e AC-DC Conversion with Completed Digital Control: To design an efficient, reliable, cost effective AC-DC power supply with advanced features, the family of dsPIC DSCs can help optimize design cycles effectively. The high-speed PWM module with multiple advanced operating modes helps implement various advanced conversion stages such as PFC, phase shift, zero voltage, transition converter with full- bridge conversion and synchronous rectification and multi-phase buck converters. The microcontroller’s high-speed ADC can be triggered on an edge of the PWM to sample the various voltages and currents for high speed processing. The high-performance CPU helps in implementing advanced PID digital control loops and compensators in software.
D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block
This last approach would be the better for NEWTON design, but as a previous stage, it is necessary t develop a solution with a more modest 8 bit microprocessor, to test the validly of the system as ilt is showr in next point.
This last approach would be the better for NEWTON design, but as a previous stage, it is necessary t develop a solution with a more modest 8 bit microprocessor, to test the validly of the system as ilt is showr in next point.
The system basically must obtain two symmetrical outputs of +-40V and a very high current, to excite the solenoid that generates the heavy magnetic field, used to drive the detection head.
The system basically must obtain two symmetrical outputs of +-40V and a very high current, to excite the solenoid that generates the heavy magnetic field, used to drive the detection head.
D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block
D3.3 - Preliminary design report for the power distribution block FIGURE 40 shows the PCB designed for the current source of NEWTON instrument prototype 3. This board is under manufacturing, therefore it has not been possible to validate the performance of this part of the design. This taks will be developed during the next stage of the project.
D3.3 - Preliminary design report for the power distribution block FIGURE 40 shows the PCB designed for the current source of NEWTON instrument prototype 3. This board is under manufacturing, therefore it has not been possible to validate the performance of this part of the design. This taks will be developed during the next stage of the project.
FIGURE 40. Picture of the board designed for the source of the prototype 3.
FIGURE 40. Picture of the board designed for the source of the prototype 3.
TABLE 6. Results obtained from the validation of the Flyback converter.
TABLE 6. Results obtained from the validation of the Flyback converter.
FIGURE 41. Prototype manufactured for the validation of the Flyback converter. FIGURE 41 shows the prototype manufactured for the validation of the Flyback converter. The performance of this prototype has been evaluated in the laboratory for an output voltage of 12V. The results obtained from the validation of this PCB are shown in TABLE 6 while FIGURE 42 represents the main parameters obtained from the validation of the Flyback converter.
FIGURE 41. Prototype manufactured for the validation of the Flyback converter. FIGURE 41 shows the prototype manufactured for the validation of the Flyback converter. The performance of this prototype has been evaluated in the laboratory for an output voltage of 12V. The results obtained from the validation of this PCB are shown in TABLE 6 while FIGURE 42 represents the main parameters obtained from the validation of the Flyback converter.
D3.3 - Preliminary design report for the power distribution block The results obtained from the measurements of the Flyback converter asses the performance observed during the design period. Though this kind of DC/DC converters are suitable for medium power applications, the fact of having only one switch doesn’t provide good efficiency at very low loads, due to the intrinsic losses of this architecture.
D3.3 - Preliminary design report for the power distribution block The results obtained from the measurements of the Flyback converter asses the performance observed during the design period. Though this kind of DC/DC converters are suitable for medium power applications, the fact of having only one switch doesn’t provide good efficiency at very low loads, due to the intrinsic losses of this architecture.
FIGURE 43. Prototype manufactured for the validation of the Half-Bridge converter. FIGURE 43 shows the prototype manufactured for the validation of the Half-Bridge converter. TABLE 7 anc FIGURE 44 represent the results obtained from the measurement of the converter in the laboratory.
FIGURE 43. Prototype manufactured for the validation of the Half-Bridge converter. FIGURE 43 shows the prototype manufactured for the validation of the Half-Bridge converter. TABLE 7 anc FIGURE 44 represent the results obtained from the measurement of the converter in the laboratory.
TABLE 7. Results obtained from the validation of the Half-Bridge converter.
TABLE 7. Results obtained from the validation of the Half-Bridge converter.
D3.3 - Preliminary design report for the power distribution block There are some possible improvements to be consider for a future stage, such as selecting a more suitabl. transformer which allows the use of a better duty cycle, closer to 40-45% in order to stress both switche: and rectifier diodes in a more symmetrical way, or study each individual component requirements trying not to oversize each element in excess. Some derating must be considered when we are designing thi converter, even more knowing the critical application in which it’s going to be placed, but a trade-off mus be carefully carried out during the final design and selection of components process.
D3.3 - Preliminary design report for the power distribution block There are some possible improvements to be consider for a future stage, such as selecting a more suitabl. transformer which allows the use of a better duty cycle, closer to 40-45% in order to stress both switche: and rectifier diodes in a more symmetrical way, or study each individual component requirements trying not to oversize each element in excess. Some derating must be considered when we are designing thi converter, even more knowing the critical application in which it’s going to be placed, but a trade-off mus be carefully carried out during the final design and selection of components process.
FIGURE 45. Demo Board for the proof-of-concept of the buck converter. FIGURE 45 shows a picture of the demo board used for the validation of the buck converter topology. 4.1.3. Buck DC/DC converter
FIGURE 45. Demo Board for the proof-of-concept of the buck converter. FIGURE 45 shows a picture of the demo board used for the validation of the buck converter topology. 4.1.3. Buck DC/DC converter
FIGURE 46. Measurement setup for the validation of the Buck converter.
FIGURE 46. Measurement setup for the validation of the Buck converter.
TABLE 8. Results obtained from the validation of the Buck converter.
TABLE 8. Results obtained from the validation of the Buck converter.
FIGURE 47. Buck converter main PWM signal. D3.3 - Preliminary design report for the power distribution block
FIGURE 47. Buck converter main PWM signal. D3.3 - Preliminary design report for the power distribution block
FIGURE 48. Measurement results obtained from the validation of Buck converter.
FIGURE 48. Measurement results obtained from the validation of Buck converter.
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