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Figure 2. The maximum operating temperature of SiC power electronic devices

Figure 2 The maximum operating temperature of SiC power electronic devices

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Note: Bulk Si, SOL, WBG, and N/A stand for bulk silicon, silicon-on-insulator, wide band-gap, and currently no available, respectively. Table 1. Applications of high-temperature power electronics.
Note: Bulk Si, SOL, WBG, and N/A stand for bulk silicon, silicon-on-insulator, wide band-gap, and currently no available, respectively. Table 1. Applications of high-temperature power electronics.
Table 2. The physical properties of the available semiconductor materials under room temperature (25 °C). However, high-purity SiC powder, which can be used to grow SiC boules, is only available from a limited number of suppliers, and is relatively expensive [25]. At present, the United States is the global leader in the production of SiC substrates and wafers, followed by Europe and Japan. The quality of SiC substrate is critical for the manufacturing of high-quality chips, and the SiC substrate constitutes a major portion of the chip cost. However, the cost of epi-growth and chips can also be reduced by the use of larger-area substrates, so manufacturers that are able to successfully fabricate 6-inch diameter SiC substrates with acceptable quality. From the Yole’s report, the market size of SiC N-type wafers will increase to US$110 million by 2020 with a 21% compound annual growth rate (CAGR). With a fast growing rate of CAGR, the production of SiC-based devices will be dramatically increased.
Table 2. The physical properties of the available semiconductor materials under room temperature (25 °C). However, high-purity SiC powder, which can be used to grow SiC boules, is only available from a limited number of suppliers, and is relatively expensive [25]. At present, the United States is the global leader in the production of SiC substrates and wafers, followed by Europe and Japan. The quality of SiC substrate is critical for the manufacturing of high-quality chips, and the SiC substrate constitutes a major portion of the chip cost. However, the cost of epi-growth and chips can also be reduced by the use of larger-area substrates, so manufacturers that are able to successfully fabricate 6-inch diameter SiC substrates with acceptable quality. From the Yole’s report, the market size of SiC N-type wafers will increase to US$110 million by 2020 with a 21% compound annual growth rate (CAGR). With a fast growing rate of CAGR, the production of SiC-based devices will be dramatically increased.
Figure 1. The milestones of the development process of SiC power electronic devices. As early as 2001, Infineon produced the first commercial SiC Schottky barrier diode (SiC SBD) with characteristics of high blocking voltage, better thermal stability, and hardly any reverse recovery time. This paved the way for the development of SiC power devices in the field of power electronics. Since then, more discrete devices and power modules have gradually come out [26]. Figure 1 shows the milestones of the development process of commercialized SiC semiconductor devices. Until 2014, GeneSiC and Micross components have sold SiC bipolar junction transistor (BJT) with junction temperature up to 210 °C. At the research and development level, the operating junction temperature of SiC-SBD can reach up to 300 °C, and the performance of SiC positive-negative (P-N) diode under the temperature of 600 °C has also been verified.
Figure 1. The milestones of the development process of SiC power electronic devices. As early as 2001, Infineon produced the first commercial SiC Schottky barrier diode (SiC SBD) with characteristics of high blocking voltage, better thermal stability, and hardly any reverse recovery time. This paved the way for the development of SiC power devices in the field of power electronics. Since then, more discrete devices and power modules have gradually come out [26]. Figure 1 shows the milestones of the development process of commercialized SiC semiconductor devices. Until 2014, GeneSiC and Micross components have sold SiC bipolar junction transistor (BJT) with junction temperature up to 210 °C. At the research and development level, the operating junction temperature of SiC-SBD can reach up to 300 °C, and the performance of SiC positive-negative (P-N) diode under the temperature of 600 °C has also been verified.
Figure 3. Simplified non-self-aligned SiC metal oxide MOSFET (a) Ion implantation of p-type dopants (arrows) into source and drain (dashed boxes) is performed with an ion implant hard mask; (b) during ion implantation annealing, the surface has to be protected with a carbon cap, which prevents Si out-diffusion and surface roughening even at 1,800 °C; (c) the field oxide (FOX) and polycrystalline silicon gate (poly) stack is aligned with global alignment marks (not shown), and some overlap must be allowed; (d) the metal must be patterned before annealing at ~800-900 °C to form the metal silicide (otherwise the reaction will occur with SiO). temperature, Schottky barriers between metal and semiconductor become larger, which makes ohmic contact on SiC more difficult. By contrast, with Si and GaAs devices, the operating temperature is limited by the electronic properties of the semiconductor material; but the maximum operating temperature of SiC devices is limited by the stability of the contacts. Some device parameters such as response time and output power, depend strongly on the ohmic contact resistivity and its stability at high operating temperature. Therefore, the thermal stability of ohmic contacts and Schottky interfaces at high operating temperature is considered the critical factor for determining their power application.
Figure 3. Simplified non-self-aligned SiC metal oxide MOSFET (a) Ion implantation of p-type dopants (arrows) into source and drain (dashed boxes) is performed with an ion implant hard mask; (b) during ion implantation annealing, the surface has to be protected with a carbon cap, which prevents Si out-diffusion and surface roughening even at 1,800 °C; (c) the field oxide (FOX) and polycrystalline silicon gate (poly) stack is aligned with global alignment marks (not shown), and some overlap must be allowed; (d) the metal must be patterned before annealing at ~800-900 °C to form the metal silicide (otherwise the reaction will occur with SiO). temperature, Schottky barriers between metal and semiconductor become larger, which makes ohmic contact on SiC more difficult. By contrast, with Si and GaAs devices, the operating temperature is limited by the electronic properties of the semiconductor material; but the maximum operating temperature of SiC devices is limited by the stability of the contacts. Some device parameters such as response time and output power, depend strongly on the ohmic contact resistivity and its stability at high operating temperature. Therefore, the thermal stability of ohmic contacts and Schottky interfaces at high operating temperature is considered the critical factor for determining their power application.
Table 3. The thermal mechanical characteristics of materials for the substrate. The substrate, as the backing of SiC chips, must meet the material requirement with characteristics of excellent thermal conductivity, high mechanical strength, high flexural strength, and the similar coefficient of thermal expansion (CTE) with SiC. The direct-bond-copper (DBC) substrate presents a sandwich structure, which consists of two layers of copper, lying on the top and bottom, and with insulation ceramics in between. The available materials for insulating ceramics could be quantized as Al2O3, AIN, BeO, and Si3N4, and Table 3 shows the thermal mechanical characteristics. As it can be seen, the CTE of AIN is close to that of SiC material with the value of approximately 4-6 ppm/°C, and the mechanical stress resulted by heat expansion can be significantly reduced by the uniformity of parameters. Moreover, the thermal conductivity of AIN is highly relative to two other materials like AlyO3 and SigNq, which will significantly promote the cooling capacity of power modules. Therefore, AIN is one of the most appropriate choices for the substrate to encapsulate SiC power modules, and the relevant power modules can endure in the high-temperature environment which is above 250 °C [33]. The base plate, as the foundation and heat conductor of power modules, also has the strict material requirement, which should have characteristics of excellent thermal conductivity and similar CTE with the substrate [34]. Table 4 shows the thermal mechanical attributes of possible materials fot the base plate. CTE of Cu and Al are much higher than that of AIN (only 4.5 ppm/°C), while CTE of metal matrix composites with Mo and Cu is close to that of AIN. The thermal conductivity of metal matrix composites makes these materials have excellent heat dissipation property. With these advantages, the metal matrix composite is an excellent choice for power modules to endure in a high-temperature environment. Due to the adjustable CTE from 6.5 to 9.5 ppm/°C, and relatively high thermal conductivity with the range of 170-200 W/m-K, AISiC is also an excellent material to constitute base plate.
Table 3. The thermal mechanical characteristics of materials for the substrate. The substrate, as the backing of SiC chips, must meet the material requirement with characteristics of excellent thermal conductivity, high mechanical strength, high flexural strength, and the similar coefficient of thermal expansion (CTE) with SiC. The direct-bond-copper (DBC) substrate presents a sandwich structure, which consists of two layers of copper, lying on the top and bottom, and with insulation ceramics in between. The available materials for insulating ceramics could be quantized as Al2O3, AIN, BeO, and Si3N4, and Table 3 shows the thermal mechanical characteristics. As it can be seen, the CTE of AIN is close to that of SiC material with the value of approximately 4-6 ppm/°C, and the mechanical stress resulted by heat expansion can be significantly reduced by the uniformity of parameters. Moreover, the thermal conductivity of AIN is highly relative to two other materials like AlyO3 and SigNq, which will significantly promote the cooling capacity of power modules. Therefore, AIN is one of the most appropriate choices for the substrate to encapsulate SiC power modules, and the relevant power modules can endure in the high-temperature environment which is above 250 °C [33]. The base plate, as the foundation and heat conductor of power modules, also has the strict material requirement, which should have characteristics of excellent thermal conductivity and similar CTE with the substrate [34]. Table 4 shows the thermal mechanical attributes of possible materials fot the base plate. CTE of Cu and Al are much higher than that of AIN (only 4.5 ppm/°C), while CTE of metal matrix composites with Mo and Cu is close to that of AIN. The thermal conductivity of metal matrix composites makes these materials have excellent heat dissipation property. With these advantages, the metal matrix composite is an excellent choice for power modules to endure in a high-temperature environment. Due to the adjustable CTE from 6.5 to 9.5 ppm/°C, and relatively high thermal conductivity with the range of 170-200 W/m-K, AISiC is also an excellent material to constitute base plate.
Figure 4. The package of SiC power module.
Figure 4. The package of SiC power module.
Table 4. The thermal mechanical attributes of materials for the base plate.
Table 4. The thermal mechanical attributes of materials for the base plate.
Table 5. The thermal mechanical characteristics of materials for die attach. @ Heat sink
Table 5. The thermal mechanical characteristics of materials for die attach. @ Heat sink
Figure 5. A buried insulator layer in a fully depleted SOI structure. Based on the silicon-on-insulator (SOI) technology, a buried insulator layer in SOI structure shown in Figure 5 can effectively reduce the leakage current in high-temperature operation, improve the latch-up immunity, and suppress the threshold voltage variation to the temperature. The SOI-based integrated circuits can successfully operate at the temperature range from 200 °C to 300 °C [46], which is much higher than that of conventional bulk Si devices.
Figure 5. A buried insulator layer in a fully depleted SOI structure. Based on the silicon-on-insulator (SOI) technology, a buried insulator layer in SOI structure shown in Figure 5 can effectively reduce the leakage current in high-temperature operation, improve the latch-up immunity, and suppress the threshold voltage variation to the temperature. The SOI-based integrated circuits can successfully operate at the temperature range from 200 °C to 300 °C [46], which is much higher than that of conventional bulk Si devices.
Figure 6. Developed high-temperature gate drive and the experimental set setup. — eo e——e———e——ee eee eee eee Due to the high cost of SOI ICs and SiC fabrication technologies, an alternative way to develop high-temperature gate drives is the utilization of commercial-off-the-shelf (COTS) discrete transistors and diodes. With the COTS discrete component, the operating temperature of gate drives can reach up to 180-200 °C [55]. The main drawback of this kind of gate drives is the large propagation delay due to the high number of SOI ICs, and the protection features of desaturation and under voltage lockout (UVLO) are not included. To solve these issues, a COTS gate drive is proposed with the integrated circuit of overcurrent and UVLO, which can operate under the ambient temperature of 180 °C [56]. The proposed COTS gate drive shows better performance than the commercial gate drive (EVK-HADES 1210) produced by CISSOID in the aspects of propagation delay and total power consumption. Figure 6 shows the prototype of the COTS gate drive and the test bench. In Figure 6a, the numbers shown from 1 to 5 represent on-state voltage monitoring diode, driving buffer stage, overcurrent detection circuit, UVLO with control logic, and isolated transformer, respectively.
Figure 6. Developed high-temperature gate drive and the experimental set setup. — eo e——e———e——ee eee eee eee Due to the high cost of SOI ICs and SiC fabrication technologies, an alternative way to develop high-temperature gate drives is the utilization of commercial-off-the-shelf (COTS) discrete transistors and diodes. With the COTS discrete component, the operating temperature of gate drives can reach up to 180-200 °C [55]. The main drawback of this kind of gate drives is the large propagation delay due to the high number of SOI ICs, and the protection features of desaturation and under voltage lockout (UVLO) are not included. To solve these issues, a COTS gate drive is proposed with the integrated circuit of overcurrent and UVLO, which can operate under the ambient temperature of 180 °C [56]. The proposed COTS gate drive shows better performance than the commercial gate drive (EVK-HADES 1210) produced by CISSOID in the aspects of propagation delay and total power consumption. Figure 6 shows the prototype of the COTS gate drive and the test bench. In Figure 6a, the numbers shown from 1 to 5 represent on-state voltage monitoring diode, driving buffer stage, overcurrent detection circuit, UVLO with control logic, and isolated transformer, respectively.
Table 6. Commercially manufactured capacitors for high-temperature applications.
Table 6. Commercially manufactured capacitors for high-temperature applications.
Figure 7. Capacitance stability with temperature and DC link voltage for the XHT stacked ceramic capacitors from Presidio. Alternatively, the stacked ceramic capacitors with XHT dielectric from Presidio components, 1c. present improved capacitance stability when DC bus voltage is very high, as shown in Figure 7. . capacitance reduction of 50% from 25 °C to 175 °C is quantified. This kind of capacitors is more to racks when used under the conditions of shock and vibration. Thus, the de-rating and reliability nould be considered when designing capacitors for a high-temperature converter. With the new iaterials and fabrication technologies, Si capacitors exhibit the promising temperature resistance p to 250 °C [60]. Table 6 shows some commercially manufactured capacitors for high-temperature pplications, and few comments are also made in this table.
Figure 7. Capacitance stability with temperature and DC link voltage for the XHT stacked ceramic capacitors from Presidio. Alternatively, the stacked ceramic capacitors with XHT dielectric from Presidio components, 1c. present improved capacitance stability when DC bus voltage is very high, as shown in Figure 7. . capacitance reduction of 50% from 25 °C to 175 °C is quantified. This kind of capacitors is more to racks when used under the conditions of shock and vibration. Thus, the de-rating and reliability nould be considered when designing capacitors for a high-temperature converter. With the new iaterials and fabrication technologies, Si capacitors exhibit the promising temperature resistance p to 250 °C [60]. Table 6 shows some commercially manufactured capacitors for high-temperature pplications, and few comments are also made in this table.
Table 7. Commercially manufactured resistors for high-temperature applications. Metal foil resistors have high precision and stability in harsh environments, but the maximum erating temperature is limited to 240 °C due to the bondable chip, wire-wound resistors show quite od high-temperature characteristics, but they are not suitable for high frequency, and they act as luctors at high frequency. Thin film resistors seem to be an economical way with small size and od performance, but they are not suitable in overload conditions, whereas thick film resistors show yerior overload characteristics [61].
Table 7. Commercially manufactured resistors for high-temperature applications. Metal foil resistors have high precision and stability in harsh environments, but the maximum erating temperature is limited to 240 °C due to the bondable chip, wire-wound resistors show quite od high-temperature characteristics, but they are not suitable for high frequency, and they act as luctors at high frequency. Thin film resistors seem to be an economical way with small size and od performance, but they are not suitable in overload conditions, whereas thick film resistors show yerior overload characteristics [61].
Figure 8. Electrical connection diagram of three-phase inverter and motor. ef Y — 0 Oo Figure 8 shows the electrical connection diagram of a three-phase inverter and motor, where a selection of power electronic devices is full SiC-MOSFET, full SiC-JFET, full SiC-BJT, or SiC/Si (e.g., SiC-SBD/Si-IGBT) hybrid devices. As the anti-parallel diode, SiC-SBD is hardly any reverse recovery time and is not affected by temperature variation. The radiator volume of a 2.5 kW motor drive based on SiC-SBD hybrid devices is reduced by 2/3 when compared with the radiator of the motor drive based on Si diode [64]. In [65], a three-phase air-cooling inverter is designed by using full SiC-JFET devices, the motor drive can work in the high-temperature environment of 200 °C, and the output efficiency with 18 kW power rating reaches up to 98.2%.
Figure 8. Electrical connection diagram of three-phase inverter and motor. ef Y — 0 Oo Figure 8 shows the electrical connection diagram of a three-phase inverter and motor, where a selection of power electronic devices is full SiC-MOSFET, full SiC-JFET, full SiC-BJT, or SiC/Si (e.g., SiC-SBD/Si-IGBT) hybrid devices. As the anti-parallel diode, SiC-SBD is hardly any reverse recovery time and is not affected by temperature variation. The radiator volume of a 2.5 kW motor drive based on SiC-SBD hybrid devices is reduced by 2/3 when compared with the radiator of the motor drive based on Si diode [64]. In [65], a three-phase air-cooling inverter is designed by using full SiC-JFET devices, the motor drive can work in the high-temperature environment of 200 °C, and the output efficiency with 18 kW power rating reaches up to 98.2%.
Figure 9. Multichip power module with high-density power electronics designed by Arkansas Power Electronics International.
Figure 9. Multichip power module with high-density power electronics designed by Arkansas Power Electronics International.
Figure 10. A prototype of 3-phase motor drive by using multichip power module (MCPM).
Figure 10. A prototype of 3-phase motor drive by using multichip power module (MCPM).
Figure 11. Loss and efficiency comparison of the rectifier with Si IGBT and SiC MOSFET. module using the flat-packaged structure has advantages of small parasitic parameters, flexible line layout and, double side cooling characteristics. In switching individual tests, the parasitic inductance is reduced by 14 nH compared to the pin-packaged structure, which makes the drain-source spike voltage decrease from 295.7 V to 279 V and further lowers switching losses [70]. In temperature detection, the temperature rise of grid resistance and the voltage regulator is apparent, but the temperature rise is not more than 10 °C from the environment temperature, which benefits from the lower power losses and excellent heat-sinking capability of the high-temperature AC-DC converter.
Figure 11. Loss and efficiency comparison of the rectifier with Si IGBT and SiC MOSFET. module using the flat-packaged structure has advantages of small parasitic parameters, flexible line layout and, double side cooling characteristics. In switching individual tests, the parasitic inductance is reduced by 14 nH compared to the pin-packaged structure, which makes the drain-source spike voltage decrease from 295.7 V to 279 V and further lowers switching losses [70]. In temperature detection, the temperature rise of grid resistance and the voltage regulator is apparent, but the temperature rise is not more than 10 °C from the environment temperature, which benefits from the lower power losses and excellent heat-sinking capability of the high-temperature AC-DC converter.
Figure 12. Hardware configuration diagram of the high-temperature three-phase AC-DC converter.
Figure 12. Hardware configuration diagram of the high-temperature three-phase AC-DC converter.
Figure 13. Conceptual drawing and the assembled prototype rectifier system. In [71], Virginia Tech developed a 15 kW 650 V dc/230 V ac three-phase rectifier with interleaving structure by substitution of all Si devices with SiC JFETs, and the SiC power modules in the rectifier can operate at the junction temperature of 250 °C. With the volumetric power density of 6.3 kW/L, it successfully achieved a 2 kW/L target in more electric aircraft. It gives a detailed design for each component, including the active component, passive component, and the system. Figure 13 shows the drawing and the prototype of the rectifier system.
Figure 13. Conceptual drawing and the assembled prototype rectifier system. In [71], Virginia Tech developed a 15 kW 650 V dc/230 V ac three-phase rectifier with interleaving structure by substitution of all Si devices with SiC JFETs, and the SiC power modules in the rectifier can operate at the junction temperature of 250 °C. With the volumetric power density of 6.3 kW/L, it successfully achieved a 2 kW/L target in more electric aircraft. It gives a detailed design for each component, including the active component, passive component, and the system. Figure 13 shows the drawing and the prototype of the rectifier system.
Figure 14. A topology of the boost DC-DC converter. For Si power electronic devices, switching losses increase significantly with the increase of switching frequency. When it mentions SiC power electronic devices, the switching losses, and junction temperature are measured as shown in Figure 15, where the switching frequency of SiC- MOSFET changes from 100 kHz to 800 kHz in a 1 kW boost DC-DC converter [74]. It can be seen that both switching loss and junction temperature keep a linear relationship with switching frequency when the high-temperature and thinner layer solder is used for die attach. If the solder with a low melting point of 180 °C and low thermal conductivity is adopted for the die attach, the junction temperature can rise at an accelerating rate when the switching frequency is above 500 kHz. NASA has reported that a 100 kW DC/DC converter based SiC JFET can reach up to the operating temperature of 415 °C in 2006. In 2008, Mazumder [75] reported that the efficiency of a DC/DC converter based on SiC-JFETs can reach up to 95% at 20 °C, while the efficiency of 100 V/270 V 2 kW boost converter proposed by Kosai [76] can reach up to 90% at the temperature 200 °C, the design and performance of the boost converter were evaluated over the temperature range from 20 °C to 200 °C. The capacitance variation of the output filter is also presented in [74], reporting that a 1 kW all-SiC boost converter with the output voltage of 800V can work reliably over a switching frequency range of 100 to 800 kHz, and the steady-state working junction temperature of SiC MOSFETs has been extended to 320 °C. However,
Figure 14. A topology of the boost DC-DC converter. For Si power electronic devices, switching losses increase significantly with the increase of switching frequency. When it mentions SiC power electronic devices, the switching losses, and junction temperature are measured as shown in Figure 15, where the switching frequency of SiC- MOSFET changes from 100 kHz to 800 kHz in a 1 kW boost DC-DC converter [74]. It can be seen that both switching loss and junction temperature keep a linear relationship with switching frequency when the high-temperature and thinner layer solder is used for die attach. If the solder with a low melting point of 180 °C and low thermal conductivity is adopted for the die attach, the junction temperature can rise at an accelerating rate when the switching frequency is above 500 kHz. NASA has reported that a 100 kW DC/DC converter based SiC JFET can reach up to the operating temperature of 415 °C in 2006. In 2008, Mazumder [75] reported that the efficiency of a DC/DC converter based on SiC-JFETs can reach up to 95% at 20 °C, while the efficiency of 100 V/270 V 2 kW boost converter proposed by Kosai [76] can reach up to 90% at the temperature 200 °C, the design and performance of the boost converter were evaluated over the temperature range from 20 °C to 200 °C. The capacitance variation of the output filter is also presented in [74], reporting that a 1 kW all-SiC boost converter with the output voltage of 800V can work reliably over a switching frequency range of 100 to 800 kHz, and the steady-state working junction temperature of SiC MOSFETs has been extended to 320 °C. However,
Figure 15. Switching loss and junction temperature distribution diagram under different frequencies. the high-frequency gate drive capability and high-temperature die-attachment technology can be the issues to develop SiC-based converter operating beyond 320 °C junction temperature.
Figure 15. Switching loss and junction temperature distribution diagram under different frequencies. the high-frequency gate drive capability and high-temperature die-attachment technology can be the issues to develop SiC-based converter operating beyond 320 °C junction temperature.
Figure 16. An optical photo for 4H-SiC power integrated circuit after packaging. © re "The first SiC-based power ICs were reported i in 2008 [77]. Figure 16 shows the optical photo for 4H-SiC power integrated circuit after packaging, which includes a large power JFET and two buffer circuits. Reference [78] proposes an integrated bipolar OR/NOR gate based on 4H-SiC BJTs, and it can successfully operate up to 500 °C. References [79] and [80] report the differential amplifiers based on 4H-SiC JFET and 6H-SiC bipolar can reach up to the temperature of 500 °C and 600 °C, respectively. In [81], a 500 °C Schmitt trigger in 4H-SiC has designed and characterized, the proposed Schmitt trigger shows superior characteristics with a higher slew rate and almost independent temperature operation.
Figure 16. An optical photo for 4H-SiC power integrated circuit after packaging. © re "The first SiC-based power ICs were reported i in 2008 [77]. Figure 16 shows the optical photo for 4H-SiC power integrated circuit after packaging, which includes a large power JFET and two buffer circuits. Reference [78] proposes an integrated bipolar OR/NOR gate based on 4H-SiC BJTs, and it can successfully operate up to 500 °C. References [79] and [80] report the differential amplifiers based on 4H-SiC JFET and 6H-SiC bipolar can reach up to the temperature of 500 °C and 600 °C, respectively. In [81], a 500 °C Schmitt trigger in 4H-SiC has designed and characterized, the proposed Schmitt trigger shows superior characteristics with a higher slew rate and almost independent temperature operation.
Figure 17. Fast high temperature isolated DC/AC current measurement. (a) Photograph of the bidirectional saturated current transformer, and (b) PCB circuit. The current divider and Hall sensor are usually employed to measure the current for converter control; however, they are challenging to work in the high-temperature environment. To tackle this problem, the saturated current sensor is developed for high-temperature application. While the B/H curve of magnetic materials can drift with the temperature variation, which will lead to a significant measurement error for the current sensor, a compensation algorithm or new measurement method is proposed for the high measurement accuracy. For example, the isolated DC and AC current measurement method based on a bidirectional saturated current transformer (Figure 17) can be applied to the high-temperature converter with SiC devices, which can suppress the effect of the coercive force of magnetic materials on detection precision [90].
Figure 17. Fast high temperature isolated DC/AC current measurement. (a) Photograph of the bidirectional saturated current transformer, and (b) PCB circuit. The current divider and Hall sensor are usually employed to measure the current for converter control; however, they are challenging to work in the high-temperature environment. To tackle this problem, the saturated current sensor is developed for high-temperature application. While the B/H curve of magnetic materials can drift with the temperature variation, which will lead to a significant measurement error for the current sensor, a compensation algorithm or new measurement method is proposed for the high measurement accuracy. For example, the isolated DC and AC current measurement method based on a bidirectional saturated current transformer (Figure 17) can be applied to the high-temperature converter with SiC devices, which can suppress the effect of the coercive force of magnetic materials on detection precision [90].
Figure 1. A cross-sectional schematic view of the epitaxial layer structure and a single pixel n-type Ni/4H-SiC Schottky barrier device (SBD) mounted on a printed circuit board (PCB). The square shaped back contact is visible through the wafer. The circular contact on the top is connected using a 25 um thin gold wire. inspected whether the contact produced reliable electrical contacts or not. We adopted the minimum thickness as the optimized thickness of detector window, which produced reliable contacts confirmed from repeated I-V measurements. Ni/4H-SiC Schottky barrier device (SBD) mounted on a printed circuit board (PCB). The square shaped A wire bonding technique was developed in our laboratory for achieving strong and durable electrical connections with the Ni contacts and minimizing the bonding area for efficient radiation detection. This technique involves special type of silver epoxy rated for high temperature and vacuum applications. The same type of the silver epoxy was used for mounting the chip on a printed circuit board (PCB). A photograph of a typical single pixel detector is shown in Figure 1.
Figure 1. A cross-sectional schematic view of the epitaxial layer structure and a single pixel n-type Ni/4H-SiC Schottky barrier device (SBD) mounted on a printed circuit board (PCB). The square shaped back contact is visible through the wafer. The circular contact on the top is connected using a 25 um thin gold wire. inspected whether the contact produced reliable electrical contacts or not. We adopted the minimum thickness as the optimized thickness of detector window, which produced reliable contacts confirmed from repeated I-V measurements. Ni/4H-SiC Schottky barrier device (SBD) mounted on a printed circuit board (PCB). The square shaped A wire bonding technique was developed in our laboratory for achieving strong and durable electrical connections with the Ni contacts and minimizing the bonding area for efficient radiation detection. This technique involves special type of silver epoxy rated for high temperature and vacuum applications. The same type of the silver epoxy was used for mounting the chip on a printed circuit board (PCB). A photograph of a typical single pixel detector is shown in Figure 1.
Table 1. Categorization of 4H-SiC wafers used in this study.
Table 1. Categorization of 4H-SiC wafers used in this study.
Figure 2. Forward (a) and reverse (b) I-V characteristics obtained for SI 4H-SiC sample (SI-M50) with 1 mm diameter Ni contact at various temperatures. The concentration of trap centers with activation energy E;, unoccupied by the injected carriers, (pro) is given by = *t exp| AE — Fon. Here, kg is the Boltzmann’s constant, L is the thickness of the epitaxial layer, q is the elechenie charge, €sic is the permittivity of the material, Fo is the Fermi energy, N; is the trap concentration, and g is the degeneracy factor. Using Equation (1) for the step voltages Vs; = —70 V and Vs» = —1 V, the trap densities for the centers unoccupied by the injection carriers was calculated to be 2 x 10'4 cm™ and 3 x 10!2 cm~°, respectively. The former trap concentration was assumed to be the total trap concentration considering traps corresponding to step 1 were emptied at V = 0.
Figure 2. Forward (a) and reverse (b) I-V characteristics obtained for SI 4H-SiC sample (SI-M50) with 1 mm diameter Ni contact at various temperatures. The concentration of trap centers with activation energy E;, unoccupied by the injected carriers, (pro) is given by = *t exp| AE — Fon. Here, kg is the Boltzmann’s constant, L is the thickness of the epitaxial layer, q is the elechenie charge, €sic is the permittivity of the material, Fo is the Fermi energy, N; is the trap concentration, and g is the degeneracy factor. Using Equation (1) for the step voltages Vs; = —70 V and Vs» = —1 V, the trap densities for the centers unoccupied by the injection carriers was calculated to be 2 x 10'4 cm™ and 3 x 10!2 cm~°, respectively. The former trap concentration was assumed to be the total trap concentration considering traps corresponding to step 1 were emptied at V = 0.
Figure 3. Activation energy plot for a 50 um n-type 4H-SiC epitaxial layer (n-M50) SBD with 3.2 mm diameter Ni contact. The solid red line shows the linear fit to the experimental data.
Figure 3. Activation energy plot for a 50 um n-type 4H-SiC epitaxial layer (n-M50) SBD with 3.2 mm diameter Ni contact. The solid red line shows the linear fit to the experimental data.
Figure 4. Forward and reverse I-V characteristics obtained for 50 um n-type 4H-SiC epitaxial layer (n-S50) SBD with 3.8 mm diameter Ni contact. where Nc is the effective density of states in the conduction band of 4H-SiC and is taken equal to 1.6 x 10'9 cm=? [15]. The effective doping concentration and the built-in potential was calculated to be 1.1 x 10!5 cm- and 1.4 V, respectively. The $pc-v) was calculated to be 1.47 eV using Equations (5) and (6) which is slightly higher compared to that calculated from the I-V measurements (1.3 eV). The difference can be attributed to the difference in the underlying mechanism of the two measurements. As has been mentioned earlier, the current flow in the I-V measurements is mostly in the low barrier height regions and hence the barrier height reflects those regions only, whereas the C-V measurements gives the average value of the barrier height for the entire surface area of the Schottky contact. More work is needed to further understand the defects in the material and devise preparation approaches such as surface passivation and edge termination for mitigating these effects [21,22].
Figure 4. Forward and reverse I-V characteristics obtained for 50 um n-type 4H-SiC epitaxial layer (n-S50) SBD with 3.8 mm diameter Ni contact. where Nc is the effective density of states in the conduction band of 4H-SiC and is taken equal to 1.6 x 10'9 cm=? [15]. The effective doping concentration and the built-in potential was calculated to be 1.1 x 10!5 cm- and 1.4 V, respectively. The $pc-v) was calculated to be 1.47 eV using Equations (5) and (6) which is slightly higher compared to that calculated from the I-V measurements (1.3 eV). The difference can be attributed to the difference in the underlying mechanism of the two measurements. As has been mentioned earlier, the current flow in the I-V measurements is mostly in the low barrier height regions and hence the barrier height reflects those regions only, whereas the C-V measurements gives the average value of the barrier height for the entire surface area of the Schottky contact. More work is needed to further understand the defects in the material and devise preparation approaches such as surface passivation and edge termination for mitigating these effects [21,22].
Figure 5. Plot of 1/C? as a function of reverse bias voltage recorded at room temperature for a 50 um n-type Ni/4H-SiC (n-S50) SBD. The original C-V plot is shown in the inset.
Figure 5. Plot of 1/C? as a function of reverse bias voltage recorded at room temperature for a 50 um n-type Ni/4H-SiC (n-S50) SBD. The original C-V plot is shown in the inset.
Figure 6. Rocking curve ((0008) reflection) of the 4H-SiC semi-insulating epitaxial layer (SI-M50) used for detector fabrication. where aj, b;, and c are the atom-specific Cromer—Mann coefficients, which can be found in [26-28]. The FWHM of the (0008) plane reflection was calculated using Equations (7)-(9) and was found to be less than 2.7 arc sec. Figure 6 shows the experimentally obtained rocking curve for (0008) reflection for a semi-insulating 50 um thick 4H-SiC epitaxial layer [17]. The FWHM of the rocking curve peak was found to be ~3.6 arc sec, revealing high quality of our epitaxial layer. Structural defect densities were also estimated using a Nomarski microscope. An etch pit density (EPD) of threading screw dislocations (TSDs) was found to be ~1.7x10° cm~?. The concentration of the threading edge dislocations (TEDs) was calculated to be ~1 x 104 cm~ and basal plane dislocation (BPD) density was found to be ~70 cm7?, 3.3. Radiation Detection Measurements
Figure 6. Rocking curve ((0008) reflection) of the 4H-SiC semi-insulating epitaxial layer (SI-M50) used for detector fabrication. where aj, b;, and c are the atom-specific Cromer—Mann coefficients, which can be found in [26-28]. The FWHM of the (0008) plane reflection was calculated using Equations (7)-(9) and was found to be less than 2.7 arc sec. Figure 6 shows the experimentally obtained rocking curve for (0008) reflection for a semi-insulating 50 um thick 4H-SiC epitaxial layer [17]. The FWHM of the rocking curve peak was found to be ~3.6 arc sec, revealing high quality of our epitaxial layer. Structural defect densities were also estimated using a Nomarski microscope. An etch pit density (EPD) of threading screw dislocations (TSDs) was found to be ~1.7x10° cm~?. The concentration of the threading edge dislocations (TEDs) was calculated to be ~1 x 104 cm~ and basal plane dislocation (BPD) density was found to be ~70 cm7?, 3.3. Radiation Detection Measurements
Figure 7. Schematic of the radiation detection set-up.
Figure 7. Schematic of the radiation detection set-up.
Figure 8. Variation of CCE,), and CCE¢neoy with reverse bias voltage for an n-type Ni/4H-SiC (n-S20) SBD. The contributions of CCE gepietion aNd CCE gif fusion to the total CCE,,; are also plotted. The solid line shows the variation of depletion width with bias. where d is the depletion width at the particular bias, 42 ax is the electronic stopping power of the alpha particles calculated using SRIM [39], x; is the projected range of the alpha particles with energy Ey. We fitted the CCE ¢neory values to the CCE,,,; values considering Lj, the minority carrier diffusion length as a free parameter. The Ly value corresponding to the best fit was returned as the average minority carrier diffusion length. For the present SBD, the average value of Lg was found to be ~18.6 um From Figure 8 it was also observed that the CCEgjf fusion values dominate considerably over that of CCE gepietion Up to a reverse bias of —30 V. At even higher bias voltages the depletion width becomes equal or more than the projected range of alpha particles (~18 jm in SiC for 5486 keV alpha particle, and hence charge collection was mainly due to the drifting of charge carriers within the depletion width. Hence, above bias voltage of —70 V, the CCE depletion matched the CCE,y; values.
Figure 8. Variation of CCE,), and CCE¢neoy with reverse bias voltage for an n-type Ni/4H-SiC (n-S20) SBD. The contributions of CCE gepietion aNd CCE gif fusion to the total CCE,,; are also plotted. The solid line shows the variation of depletion width with bias. where d is the depletion width at the particular bias, 42 ax is the electronic stopping power of the alpha particles calculated using SRIM [39], x; is the projected range of the alpha particles with energy Ey. We fitted the CCE ¢neory values to the CCE,,,; values considering Lj, the minority carrier diffusion length as a free parameter. The Ly value corresponding to the best fit was returned as the average minority carrier diffusion length. For the present SBD, the average value of Lg was found to be ~18.6 um From Figure 8 it was also observed that the CCEgjf fusion values dominate considerably over that of CCE gepietion Up to a reverse bias of —30 V. At even higher bias voltages the depletion width becomes equal or more than the projected range of alpha particles (~18 jm in SiC for 5486 keV alpha particle, and hence charge collection was mainly due to the drifting of charge carriers within the depletion width. Hence, above bias voltage of —70 V, the CCE depletion matched the CCE,y; values.
Figure 9. A pulse-height spectrum obtained for a 20 um n-type 4H-SiC (n-S20) SBD and 241 Am alpha source. It can be noted that the authors used a collimated *°Pu source and circular diode contacts of 200 and 400 um. Later on, Ruddy et al. also reported [42] an energy resolution of 5.7% for a deposited energy of 89.5 keV alpha particles from a 100 um collimated 148Gd source in similar detectors with comparatively larger Schottky contact diameter of 2.5, 3.5, 4.5, 6.0, and 10 mm thick 4H-SiC epitaxial layers. In another work [8], Ruddy et al. reported an energy resolution close to 46 keV (~0.8%) for alpha particles from a 238Pu source and 41.5 keV (~1.3%) for alpha particles from a 148Gd source for devices with an aluminum guard ring. Ivanov et al. [43] reported an energy resolution of 20 keV (~0.4%) in the energy range 5.4-5.5 MeV. In yet another work, Ruddy et al. [44] reported an energy resolution of 20.6 keV (~0.4%) for *3°Pu alpha particles. In our earlier work [20] we reported an energy resolution of 2.7% for 5486 keV alpha particles in 50 um thick n-type Ni/4H-SiC detectors. The energy resolution mentioned in the above works were found to be primarily dependent on the defect type and concentrations within the 4H-SiC epilayers. The nature of defects, which controls the detector properties, will be described in detail in a later section.
Figure 9. A pulse-height spectrum obtained for a 20 um n-type 4H-SiC (n-S20) SBD and 241 Am alpha source. It can be noted that the authors used a collimated *°Pu source and circular diode contacts of 200 and 400 um. Later on, Ruddy et al. also reported [42] an energy resolution of 5.7% for a deposited energy of 89.5 keV alpha particles from a 100 um collimated 148Gd source in similar detectors with comparatively larger Schottky contact diameter of 2.5, 3.5, 4.5, 6.0, and 10 mm thick 4H-SiC epitaxial layers. In another work [8], Ruddy et al. reported an energy resolution close to 46 keV (~0.8%) for alpha particles from a 238Pu source and 41.5 keV (~1.3%) for alpha particles from a 148Gd source for devices with an aluminum guard ring. Ivanov et al. [43] reported an energy resolution of 20 keV (~0.4%) in the energy range 5.4-5.5 MeV. In yet another work, Ruddy et al. [44] reported an energy resolution of 20.6 keV (~0.4%) for *3°Pu alpha particles. In our earlier work [20] we reported an energy resolution of 2.7% for 5486 keV alpha particles in 50 um thick n-type Ni/4H-SiC detectors. The energy resolution mentioned in the above works were found to be primarily dependent on the defect type and concentrations within the 4H-SiC epilayers. The nature of defects, which controls the detector properties, will be described in detail in a later section.
Figure 10. Measured responsivity of a 4H-SiC n-type epitaxial device biased to 250 V and an IFW JEC4 photodiode biased to 120 V. Absolute measurement of photo-responsivity and probing of physical construction of photonic sensors can be very effectively done using synchrotron light sources. N-type 4H-SiC epitaxial layer detectors fabricated at UofSC were studied at NSLS at BNL for detection of low energy X-rays. The results were compared to a commercial off-the-shelf (COTS) SiC UV photodiode by IFW optronics GmbH (Jena, Germany), model JEC4 which was known to be the best commercially available for such applications [45]. An X-ray spectrometer for such a low energy spectral range is not available commercially. Figure 10 shows the responsivity of one of our detectors and a IFW JEC4 SiC UV photodiode to soft X-ray energy ranges biased at 250 and 120 V, respectively [17]. The following results were derived using a statistical analysis of these data based on energy-dependent X-ray attenuation lengths [46].
Figure 10. Measured responsivity of a 4H-SiC n-type epitaxial device biased to 250 V and an IFW JEC4 photodiode biased to 120 V. Absolute measurement of photo-responsivity and probing of physical construction of photonic sensors can be very effectively done using synchrotron light sources. N-type 4H-SiC epitaxial layer detectors fabricated at UofSC were studied at NSLS at BNL for detection of low energy X-rays. The results were compared to a commercial off-the-shelf (COTS) SiC UV photodiode by IFW optronics GmbH (Jena, Germany), model JEC4 which was known to be the best commercially available for such applications [45]. An X-ray spectrometer for such a low energy spectral range is not available commercially. Figure 10 shows the responsivity of one of our detectors and a IFW JEC4 SiC UV photodiode to soft X-ray energy ranges biased at 250 and 120 V, respectively [17]. The following results were derived using a statistical analysis of these data based on energy-dependent X-ray attenuation lengths [46].
Figure 11. (a) Responsivity of the detectors on 4H-SiC n-type epitaxial layer at two different locations and (b) surface scan profiles along line L obtained to assess the detector’s uniformity. Responsivity measurements were carried out using the U3C [45] and X8A [46] lines by recording successive measures of photocurrent in response to a high flux, mono-energetic beam of photons in well-calibrated silicon sensor (with known responsivity) and in the sensor of interest (Figure 11a). Deac layers and a limited active volume thickness led to responsivity that varies greatly with photon energ) Further, edges were also apparent in the responsivity curve, arising from discrete atomic transitions Edges associated with silicon and carbon is clearly observed in the data, providing a quantitative measure of the composition and dimension of the active and dead layers [46]. The general feature of < steep decrease starting at 2-3 keV provides information on active layer thicknesses, which is deducec to be 21 um in our detector compared to roughly 6 um for the JEC4 diode [47]. Due to the higher active layer thickness our sensor chip showed significant improvement of responsivity in the few keV rang¢ compared to COTS SiC UV photodiode. Our detector has shown much higher response in the low energy part of the spectra as well, which could be attributed to a much thinner dead/blocking laye1 deduced from the responsivity curve to result solely from the 10 nm thick nickel layer (which leads tc the pronounced edge at 70 eV). In comparison, the JEC4 diode has been found to include a significan oxidation and inactive SiC layer on the order of 100 nm each, which limits responsivity at low photor energies [47]. It should be noted that the JEC4 diode is intended for UV detection, for which it is wel suited. The significant dead layers are likely due to passivation, which may be preferred over reducing the thickness of dead layers on the active face of the sensor.
Figure 11. (a) Responsivity of the detectors on 4H-SiC n-type epitaxial layer at two different locations and (b) surface scan profiles along line L obtained to assess the detector’s uniformity. Responsivity measurements were carried out using the U3C [45] and X8A [46] lines by recording successive measures of photocurrent in response to a high flux, mono-energetic beam of photons in well-calibrated silicon sensor (with known responsivity) and in the sensor of interest (Figure 11a). Deac layers and a limited active volume thickness led to responsivity that varies greatly with photon energ) Further, edges were also apparent in the responsivity curve, arising from discrete atomic transitions Edges associated with silicon and carbon is clearly observed in the data, providing a quantitative measure of the composition and dimension of the active and dead layers [46]. The general feature of < steep decrease starting at 2-3 keV provides information on active layer thicknesses, which is deducec to be 21 um in our detector compared to roughly 6 um for the JEC4 diode [47]. Due to the higher active layer thickness our sensor chip showed significant improvement of responsivity in the few keV rang¢ compared to COTS SiC UV photodiode. Our detector has shown much higher response in the low energy part of the spectra as well, which could be attributed to a much thinner dead/blocking laye1 deduced from the responsivity curve to result solely from the 10 nm thick nickel layer (which leads tc the pronounced edge at 70 eV). In comparison, the JEC4 diode has been found to include a significan oxidation and inactive SiC layer on the order of 100 nm each, which limits responsivity at low photor energies [47]. It should be noted that the JEC4 diode is intended for UV detection, for which it is wel suited. The significant dead layers are likely due to passivation, which may be preferred over reducing the thickness of dead layers on the active face of the sensor.
Figure 12. *41Am spectrum of a 4H-SiC detector (8.0 mm?) at 300 K, 250 V bias, and 4 us shaping time. The width (FWHM) of the pulser peak then gives the idea of the overall noise of the spectrometer (FWHM totai)-
Figure 12. *41Am spectrum of a 4H-SiC detector (8.0 mm?) at 300 K, 250 V bias, and 4 us shaping time. The width (FWHM) of the pulser peak then gives the idea of the overall noise of the spectrometer (FWHM totai)-
Figure 13. Variation of 5.48 MeV alpha peak FWHM, pulser peak FWHM, and alpha peak percentage resolution as a function of detector bias voltage. Figure 13 shows the results of a typical noise monitoring measurement [36,37]. The energy resolution of the detector could be seen to improve with increase in bias voltage up to 100 V reverse bias because of the increase in depletion width (active volume of the detector) and lowering in capacitance. The energy resolution beyond 100 V was seen to deteriorate with increase in bias. The increase in leakage current was ruled out as an explanation as it could be seen from the figure that the pulser noise did not increase at all. A possible reason behind the deterioration of the resolution is incorporation of the threading dislocation as the depletion width approaches towards the epilayer-substrate interface with the increase in reverse bias. The epilayer—substrate interfacial region is prone to have a larger threading type dislocation concentration, which propagates from the substrate to the epilayer [36].
Figure 13. Variation of 5.48 MeV alpha peak FWHM, pulser peak FWHM, and alpha peak percentage resolution as a function of detector bias voltage. Figure 13 shows the results of a typical noise monitoring measurement [36,37]. The energy resolution of the detector could be seen to improve with increase in bias voltage up to 100 V reverse bias because of the increase in depletion width (active volume of the detector) and lowering in capacitance. The energy resolution beyond 100 V was seen to deteriorate with increase in bias. The increase in leakage current was ruled out as an explanation as it could be seen from the figure that the pulser noise did not increase at all. A possible reason behind the deterioration of the resolution is incorporation of the threading dislocation as the depletion width approaches towards the epilayer-substrate interface with the increase in reverse bias. The epilayer—substrate interfacial region is prone to have a larger threading type dislocation concentration, which propagates from the substrate to the epilayer [36].
Figure 14. Variation of equivalent noise charge as a function of shaping time constant (a) without the detector connected, (b) with the detector connected. Figure 14a,b shows the variation of ENC with shaping time without and with the detector (20 um n-type Ni/4H-SiC (n-S20) SBD) connected [37]. The contributions from the three different terms were plotted separately. The minimum noise without the detector was observed to correspond to a shaping time value between 1 and 2 us. The same shifted to a higher range of shaping time (between 3 and 6 us) when the detector was plugged in. It can also be seen that the white parallel noise increased almost by a factor of five after connecting the detector and the pink noise marginally increased for any given 7 after connecting the detector. In contrast, the white series noise increased by an order of magnitude when the detector was connected. The increase in white parallel noise can be attributed to the increase in the leakage current (from the detector) and the increase in white series and parallel noise is supposedly due to the increase in input capacitance when the detector is plugged in.
Figure 14. Variation of equivalent noise charge as a function of shaping time constant (a) without the detector connected, (b) with the detector connected. Figure 14a,b shows the variation of ENC with shaping time without and with the detector (20 um n-type Ni/4H-SiC (n-S20) SBD) connected [37]. The contributions from the three different terms were plotted separately. The minimum noise without the detector was observed to correspond to a shaping time value between 1 and 2 us. The same shifted to a higher range of shaping time (between 3 and 6 us) when the detector was plugged in. It can also be seen that the white parallel noise increased almost by a factor of five after connecting the detector and the pink noise marginally increased for any given 7 after connecting the detector. In contrast, the white series noise increased by an order of magnitude when the detector was connected. The increase in white parallel noise can be attributed to the increase in the leakage current (from the detector) and the increase in white series and parallel noise is supposedly due to the increase in input capacitance when the detector is plugged in.
Figure 15. Microscopic image of the morphological defects revealed after KOH etching in n-type 4H-SiC samples. the n-type epitaxial layer samples followed by KOH etching, optical microscopy, and EBIC studies [52]. While the n-type epitaxial layers showed features like comet tails, pits, hillocks, triangular defects, and step bunching, the SI epitaxial layers showed the presence of carrot defects only. The hillocks were proposed to originate from foreign impurities and silicon precipitates. Silicon can also have pits if it evaporates during the epitaxial growth. Triangular defects indicate the inclusion of 3C-SiC and Shockley-type stacking faults nucleating on micropipes and elementary threading screw and edge dislocation [53]. The presence of these defects is believed to increase the leakage current upon application of high electrical fields to the devices [54]. Pits and step bunching types of morphological defects are not believed to influence the leakage current but can interfere with proper functioning of the Schottky contacts in case the epilayer surface is not smooth enough due to their presence [54]. Figure 16 shows an EBIC image of an n-type 4H-SiC epitaxial layer. The typical signatures of threading dislocation type defects could be seen as black spots [55,56]. The EBIC features were mapped on to the morphological defect images and it was correlated that the dark spots are the signatures of the comet tail morphological defects in the n-type epitaxial layers. The superior samples did not show any presence of morphological defects.
Figure 15. Microscopic image of the morphological defects revealed after KOH etching in n-type 4H-SiC samples. the n-type epitaxial layer samples followed by KOH etching, optical microscopy, and EBIC studies [52]. While the n-type epitaxial layers showed features like comet tails, pits, hillocks, triangular defects, and step bunching, the SI epitaxial layers showed the presence of carrot defects only. The hillocks were proposed to originate from foreign impurities and silicon precipitates. Silicon can also have pits if it evaporates during the epitaxial growth. Triangular defects indicate the inclusion of 3C-SiC and Shockley-type stacking faults nucleating on micropipes and elementary threading screw and edge dislocation [53]. The presence of these defects is believed to increase the leakage current upon application of high electrical fields to the devices [54]. Pits and step bunching types of morphological defects are not believed to influence the leakage current but can interfere with proper functioning of the Schottky contacts in case the epilayer surface is not smooth enough due to their presence [54]. Figure 16 shows an EBIC image of an n-type 4H-SiC epitaxial layer. The typical signatures of threading dislocation type defects could be seen as black spots [55,56]. The EBIC features were mapped on to the morphological defect images and it was correlated that the dark spots are the signatures of the comet tail morphological defects in the n-type epitaxial layers. The superior samples did not show any presence of morphological defects.
Figure 16. Electron beam induced current spectroscopy (EBIC) image of a n-type 4H-SiC epitaxial layer.
Figure 16. Electron beam induced current spectroscopy (EBIC) image of a n-type 4H-SiC epitaxial layer.
Figure 17. Thermally stimulated current (TSC) spectra obtained using an n-type 4H-SiC (n-M50) epitaxial layer at two different reverse bias voltages: (a) 12 V and (b) 4 V. where, Q is the total charge emitted by the given trap which in turn is determined by the area under the corresponding peak, A is the contact area, Ng is the effective doping concentration, V); is the built-in potential, V, is the applied bias voltage, q is the electronic charge, ¢sic is the dielectric permittivity of SiC, and €0 is the dielectric permittivity of vacuum. It can be noted here that being a shallow defect level, the trap center corresponding to peak #1 is not expected to cause significant trapping/polarization even though its concentration is relatively high. The intensity of peak#2 was also observed to increase with reverse bias voltage. However, it depended on other conditions such as pumping time. Overnight pumping, since the exposure of the I'SC chamber and the sample to air, resulted in decrease of the intensity of peak#2 by a factor of two to three. This suggests that peak#2 could have contributions from levels/dipoles produced by adsorption of residues in the vacuum chamber (such as water) onto the surface of the sample. Additionally, peak#2 was always distorted by the negative spike, the origin of which could not be explained. The intensities of peaks #3 and #4 do not show voltage dependence of the peak intensities as can be observed when zoomed-in (inset in Figure 17). This is an indicative of the fact that the traps associated with peaks #3 and #4 are located mostly near the metal-semiconductor interface and not in the interior of the epitaxial layer. The activation energies for peaks #3 and #4 could not be determined as the TSC signals were too weak. However, the traps corresponding to peaks #3 and #4 could be identified using their maximum temperatures and previously reported data in similar samples [12,14,56]. The peak#3 (Tm ~226 K) can be assigned to D-center, a boron (B) related defect, boron at C-site (Bc) or boron at Si site (Bg), and carbon vacancy Vc [57], whereas peak#4 can be assigned to intrinsic defects such as IL2 center [58,59]. Figure 18 shows TSC spectra obtained for a semi-insulating 4H-SiC epitaxial layer (SI-M50) sample at 0 V applied bias (higher bias resulted in large leakage currents for these samples) [14]. The thermally stimulated current at 0 V is due to a thermoelectric effect caused by small temperature gradient between
Figure 17. Thermally stimulated current (TSC) spectra obtained using an n-type 4H-SiC (n-M50) epitaxial layer at two different reverse bias voltages: (a) 12 V and (b) 4 V. where, Q is the total charge emitted by the given trap which in turn is determined by the area under the corresponding peak, A is the contact area, Ng is the effective doping concentration, V); is the built-in potential, V, is the applied bias voltage, q is the electronic charge, ¢sic is the dielectric permittivity of SiC, and €0 is the dielectric permittivity of vacuum. It can be noted here that being a shallow defect level, the trap center corresponding to peak #1 is not expected to cause significant trapping/polarization even though its concentration is relatively high. The intensity of peak#2 was also observed to increase with reverse bias voltage. However, it depended on other conditions such as pumping time. Overnight pumping, since the exposure of the I'SC chamber and the sample to air, resulted in decrease of the intensity of peak#2 by a factor of two to three. This suggests that peak#2 could have contributions from levels/dipoles produced by adsorption of residues in the vacuum chamber (such as water) onto the surface of the sample. Additionally, peak#2 was always distorted by the negative spike, the origin of which could not be explained. The intensities of peaks #3 and #4 do not show voltage dependence of the peak intensities as can be observed when zoomed-in (inset in Figure 17). This is an indicative of the fact that the traps associated with peaks #3 and #4 are located mostly near the metal-semiconductor interface and not in the interior of the epitaxial layer. The activation energies for peaks #3 and #4 could not be determined as the TSC signals were too weak. However, the traps corresponding to peaks #3 and #4 could be identified using their maximum temperatures and previously reported data in similar samples [12,14,56]. The peak#3 (Tm ~226 K) can be assigned to D-center, a boron (B) related defect, boron at C-site (Bc) or boron at Si site (Bg), and carbon vacancy Vc [57], whereas peak#4 can be assigned to intrinsic defects such as IL2 center [58,59]. Figure 18 shows TSC spectra obtained for a semi-insulating 4H-SiC epitaxial layer (SI-M50) sample at 0 V applied bias (higher bias resulted in large leakage currents for these samples) [14]. The thermally stimulated current at 0 V is due to a thermoelectric effect caused by small temperature gradient between
Table 2. Defect parameters acquired from TSC spectroscopy for a SI Ni/4H-SiC sample. 3.5.3. Deep Level Transient Spectroscopy (DLTS) Measurements
Table 2. Defect parameters acquired from TSC spectroscopy for a SI Ni/4H-SiC sample. 3.5.3. Deep Level Transient Spectroscopy (DLTS) Measurements
Figure 18. TSC spectra obtained using a SI 4H-SiC (SI-M50) epitaxial layer for three different heating rates from the Arrhenius plots, and their identity are tabulated in Table 2. Due to high stray currents at high temperatures, peak E could not be used for Arrhenius plots.
Figure 18. TSC spectra obtained using a SI 4H-SiC (SI-M50) epitaxial layer for three different heating rates from the Arrhenius plots, and their identity are tabulated in Table 2. Due to high stray currents at high temperatures, peak E could not be used for Arrhenius plots.
Figure 19. Arrhenius plots obtained from TSC spectra of a SI 4H-SiC (SI-M50) epitaxial layer at OV bias. voltage.
Figure 19. Arrhenius plots obtained from TSC spectra of a SI 4H-SiC (SI-M50) epitaxial layer at OV bias. voltage.
Table 3. Defect parameters acquired from DLTS spectroscopy for a 50 um n-type Ni/4H-SiC (n-S50) epitaxial Schottky barrier detector. Figure 22 shows DLTS spectra obtained from a 20 um Ni/4H-SiC epitaxial (n-S20) SBD using a —2 to 0 V pulse with a pulse width of 1 ms on the temperature range 84 to 750 K. Figure 22a was recorded using correlator delays of 100, 50, 20, and 10 ms and Figure 22b was recorded using 0.2, 0.1, 0.05, and 0.02 ms for a shorter temperature range. The initial spectra showed four peaks; however, after gaussian
Table 3. Defect parameters acquired from DLTS spectroscopy for a 50 um n-type Ni/4H-SiC (n-S50) epitaxial Schottky barrier detector. Figure 22 shows DLTS spectra obtained from a 20 um Ni/4H-SiC epitaxial (n-S20) SBD using a —2 to 0 V pulse with a pulse width of 1 ms on the temperature range 84 to 750 K. Figure 22a was recorded using correlator delays of 100, 50, 20, and 10 ms and Figure 22b was recorded using 0.2, 0.1, 0.05, and 0.02 ms for a shorter temperature range. The initial spectra showed four peaks; however, after gaussian
Figure 20. A typical deep level transient spectroscopy (DLTS) spectra obtained using the 50 um n-type Ni/4H-SiC (n-S50) epitaxial Schottky barrier detector in a temperature range of (a) 80-140 K and (b) 80-800 K.
Figure 20. A typical deep level transient spectroscopy (DLTS) spectra obtained using the 50 um n-type Ni/4H-SiC (n-S50) epitaxial Schottky barrier detector in a temperature range of (a) 80-140 K and (b) 80-800 K.
Figure 21. Arrhenius plots obtained for peaks #1—-#6 corresponding to the DLTS spectra shown in Figure 20.
Figure 21. Arrhenius plots obtained for peaks #1—-#6 corresponding to the DLTS spectra shown in Figure 20.
Table 4. Defect parameters acquired from the DLTS spectra for a 20 um n-type Ni/4H-SiC epitaxial (n-S20) Schottky barrier detector. Peak #1 is well established to correlate with the transition of substitutional titanium (Ti) in the cubic lattice site, Ti(c), from the +3 charge state to +2 [64] and is well known to appear in SiC as a side effect of the growth process [61,64,66]. The upward bending of the left side tail of the peak for the lowest two correlators suggest the presence of the Ti(h) defect at approximately E, — 0.12 eV; however, its peak was not observed in the temperature range used. Peak #2 is the Z1/2 center which appears in all 4H-SiC samples and has been strongly correlated to carbon vacancies as established by several annealing studies using DLTS and EPR [74-76]. Theoretical calculations and EPR measurements suggest that the identity of the three levels could be the (—2/0) transition of the cubic and (—1/0) transition of both the cubic and hexagonal site carbon vacancies [72,73,76,77]. Peak #3 is identified as Cil which is suspected to originate from chlorine impurities introduced during the growth process to compensate for silicon droplet formation [61,71]. Peaks #4 and #5 were labeled as EHg and EH7 and are commonly grouped together as the single peak EHg)7 due to their close proximity [14,51,52,56,66,75,78-81]. Its concentration has a one to one correlation with Z1/2 suggesting its relation to the carbon vacancy. Further EPR measurements suggest that EH, is the +1 donor state and EH7 is the +2 state [77] and this is supported by theoretical calculations as well [72,73,79]. In contrast to the n-S50 samples, the n-S20 sample did not show the presence of Ti(h), EHs, and the unidentified defect situated at 2.4 eV below the conduction band edge. However, n-S20 samples did show the presence of EH¢ and EH7 defect levels which were not encountered in the n-S50 samples.
Table 4. Defect parameters acquired from the DLTS spectra for a 20 um n-type Ni/4H-SiC epitaxial (n-S20) Schottky barrier detector. Peak #1 is well established to correlate with the transition of substitutional titanium (Ti) in the cubic lattice site, Ti(c), from the +3 charge state to +2 [64] and is well known to appear in SiC as a side effect of the growth process [61,64,66]. The upward bending of the left side tail of the peak for the lowest two correlators suggest the presence of the Ti(h) defect at approximately E, — 0.12 eV; however, its peak was not observed in the temperature range used. Peak #2 is the Z1/2 center which appears in all 4H-SiC samples and has been strongly correlated to carbon vacancies as established by several annealing studies using DLTS and EPR [74-76]. Theoretical calculations and EPR measurements suggest that the identity of the three levels could be the (—2/0) transition of the cubic and (—1/0) transition of both the cubic and hexagonal site carbon vacancies [72,73,76,77]. Peak #3 is identified as Cil which is suspected to originate from chlorine impurities introduced during the growth process to compensate for silicon droplet formation [61,71]. Peaks #4 and #5 were labeled as EHg and EH7 and are commonly grouped together as the single peak EHg)7 due to their close proximity [14,51,52,56,66,75,78-81]. Its concentration has a one to one correlation with Z1/2 suggesting its relation to the carbon vacancy. Further EPR measurements suggest that EH, is the +1 donor state and EH7 is the +2 state [77] and this is supported by theoretical calculations as well [72,73,79]. In contrast to the n-S50 samples, the n-S20 sample did not show the presence of Ti(h), EHs, and the unidentified defect situated at 2.4 eV below the conduction band edge. However, n-S20 samples did show the presence of EH¢ and EH7 defect levels which were not encountered in the n-S50 samples.
Figure 22. DLTS spectra of the detector obtained using the highest (a) and lowest (b) sets of initial delays over the temperature range of 84-750 K. deconvolution a fifth peak labeled peak #4 was observed between peaks #3 and #5. The most dominant peak is clearly peak #2.
Figure 22. DLTS spectra of the detector obtained using the highest (a) and lowest (b) sets of initial delays over the temperature range of 84-750 K. deconvolution a fifth peak labeled peak #4 was observed between peaks #3 and #5. The most dominant peak is clearly peak #2.
To study the defect dynamics, i.e., transformation or disappearance of defects because of atomic motion under the influence of temperature, isochronal annealing experiments were carried out on 50 um n-type Ni/4H-SiC (n-S50) SBDs [82]. As mentioned earlier in Section 2, the samples were annealed at a particular temperature for 30 min followed by DLTS measurements. The annealing treatments were carried out in the temperature range 100-800 °C. Figure 23 summarizes the DLTS results obtained after each annealing stage. For the sake of simplicity, the defect levels with activation energy above room temperature are shown in the figure. As is evident from the DLTS spectra, all the deep level defects were very much stable up to an annealing temperature of 800 °C. The lesser apparent defects as have been observed previously [82] are also summarized as follows. The capture cross-sections of the trap centers Ti(c), Zi/2, and EHs were reduced by an order of magnitude when the samples were annealed at a temperature of 400 °C. The respective defect densities were observed to follow a similar trend throughout the isochronal annealing studies. Figure 23. DLTS spectra obtained in a temperature range 250-750 K: (a) as-fabricated and annealed at 100 and 200 °C; and (b) annealed at 400, 600, and 800 °C.
To study the defect dynamics, i.e., transformation or disappearance of defects because of atomic motion under the influence of temperature, isochronal annealing experiments were carried out on 50 um n-type Ni/4H-SiC (n-S50) SBDs [82]. As mentioned earlier in Section 2, the samples were annealed at a particular temperature for 30 min followed by DLTS measurements. The annealing treatments were carried out in the temperature range 100-800 °C. Figure 23 summarizes the DLTS results obtained after each annealing stage. For the sake of simplicity, the defect levels with activation energy above room temperature are shown in the figure. As is evident from the DLTS spectra, all the deep level defects were very much stable up to an annealing temperature of 800 °C. The lesser apparent defects as have been observed previously [82] are also summarized as follows. The capture cross-sections of the trap centers Ti(c), Zi/2, and EHs were reduced by an order of magnitude when the samples were annealed at a temperature of 400 °C. The respective defect densities were observed to follow a similar trend throughout the isochronal annealing studies. Figure 23. DLTS spectra obtained in a temperature range 250-750 K: (a) as-fabricated and annealed at 100 and 200 °C; and (b) annealed at 400, 600, and 800 °C.
Figure 24. Capacitance-DLTS spectra obtained in the temperature range 250-750 K for (a) AS2, (b) AS1, and (c) AS3. The detectors were fabricated on n-S20 type epitaxial layers.
Figure 24. Capacitance-DLTS spectra obtained in the temperature range 250-750 K for (a) AS2, (b) AS1, and (c) AS3. The detectors were fabricated on n-S20 type epitaxial layers.
Figure 1. The structure design of the developed 1200V/200A full-SiC power module: (a) Design structure; (b) circuit topology.
Figure 1. The structure design of the developed 1200V/200A full-SiC power module: (a) Design structure; (b) circuit topology.
Figure 2. Comparison of common source paths inside the developed SiC power module with the commercial one. (a) Developed module in this work (design structure), (b) commercial module (physical structure). For the symmetry design, the two parallel-connected DBCs (direct bonding copper) for both upper-side and lower-side are symmetrical, the two parallel-connected pair of SiC- MOSFET and anti-parallel SiC-SBDs for both upper-side and lower-side are also symmetrical. The symmetry of the gate loops between the parallel chips is realized by placing the gate and source routings of the lower-side near the central line of the module as shown in Figure 2a. When compared to some commercial power module (Figure 2b) where the gate and source routings of the lower-side are placed to one side of the power module, our design has an enhanced symmetry for the gate-source routings of the parallel-connected chips. On the other hand, the parasitic inductance of the gate-source loop of our design is also reduced.
Figure 2. Comparison of common source paths inside the developed SiC power module with the commercial one. (a) Developed module in this work (design structure), (b) commercial module (physical structure). For the symmetry design, the two parallel-connected DBCs (direct bonding copper) for both upper-side and lower-side are symmetrical, the two parallel-connected pair of SiC- MOSFET and anti-parallel SiC-SBDs for both upper-side and lower-side are also symmetrical. The symmetry of the gate loops between the parallel chips is realized by placing the gate and source routings of the lower-side near the central line of the module as shown in Figure 2a. When compared to some commercial power module (Figure 2b) where the gate and source routings of the lower-side are placed to one side of the power module, our design has an enhanced symmetry for the gate-source routings of the parallel-connected chips. On the other hand, the parasitic inductance of the gate-source loop of our design is also reduced.
Table 1. The circuit parameters of components of the testing rig.
Table 1. The circuit parameters of components of the testing rig.
Figure 3. The clamped inductive load double pulse testing circuit platform: (a) Physical picture, (b) schematic diagram of circuit. The clamped inductive double-pulse test rig is shown in Figure 3a. The DUT is the developed 1200V/200A full-SiC power module. The electrolytic capacitor of FG810K901-1 from VDTCAP (Shenzhen, China) is used as the DC bus capacitor. Two capacitors from KEMET (Fort Lauderdale, FL, USA) is used as decoupling capacitor. Two serial-connected self-fabricated inductors are used as load inductor with a total inductance of 160 1H. The voltage and current signals are acquired by a Teledyne Lecroy HDO6104 1GHz high definition oscilloscope (Teledyne LeCroy, Chestnut Ridge, New York, USA). A Rogowski current waveform transducer CWT miniHF 1B (Power Electronic Measurements Ltd (PEM), Nottingham, UK) with bandwidth 30 MHz is utilized to measure the drain current of the DUT. A passive voltage probe PP026-2 with bandwidth of 500 MHz and a high voltage differential probe HVD3106 with the bandwidth of 120 MHz from Teledyne Lecroy are used to obtain the waveforms of Ugs and vps of DUT respectively.
Figure 3. The clamped inductive load double pulse testing circuit platform: (a) Physical picture, (b) schematic diagram of circuit. The clamped inductive double-pulse test rig is shown in Figure 3a. The DUT is the developed 1200V/200A full-SiC power module. The electrolytic capacitor of FG810K901-1 from VDTCAP (Shenzhen, China) is used as the DC bus capacitor. Two capacitors from KEMET (Fort Lauderdale, FL, USA) is used as decoupling capacitor. Two serial-connected self-fabricated inductors are used as load inductor with a total inductance of 160 1H. The voltage and current signals are acquired by a Teledyne Lecroy HDO6104 1GHz high definition oscilloscope (Teledyne LeCroy, Chestnut Ridge, New York, USA). A Rogowski current waveform transducer CWT miniHF 1B (Power Electronic Measurements Ltd (PEM), Nottingham, UK) with bandwidth 30 MHz is utilized to measure the drain current of the DUT. A passive voltage probe PP026-2 with bandwidth of 500 MHz and a high voltage differential probe HVD3106 with the bandwidth of 120 MHz from Teledyne Lecroy are used to obtain the waveforms of Ugs and vps of DUT respectively.
Figure 4. Typical diagram of turn-on switching transient for SiC power module.
Figure 4. Typical diagram of turn-on switching transient for SiC power module.
Table 2. Comparison of turn-on time for SiC power module. First of all, the factors that take effects on the vgs characteristic will be discussed in the following s well known that the increased Vpp and Io affects the slew rate of vps. Due to the coupling effects of > drain-gate capacitors, the vg; characteristic will change along with the rise of Vpp and Io. In order to vestigate thoroughly the influences of Vpp and Io (i.e., output power) on vgs characteristics at turn-on nsient for the developed high frequency SiC power module, and clarify the difference between the . characteristics of upper-side and lower-side of the SiC power module, some experiments were nducted. The conditions of these experiments are listed in Table 3. As shown in Table 3, the output wer of SiC power module in experiment is increased gradually from case_1 to case_3.
Table 2. Comparison of turn-on time for SiC power module. First of all, the factors that take effects on the vgs characteristic will be discussed in the following s well known that the increased Vpp and Io affects the slew rate of vps. Due to the coupling effects of > drain-gate capacitors, the vg; characteristic will change along with the rise of Vpp and Io. In order to vestigate thoroughly the influences of Vpp and Io (i.e., output power) on vgs characteristics at turn-on nsient for the developed high frequency SiC power module, and clarify the difference between the . characteristics of upper-side and lower-side of the SiC power module, some experiments were nducted. The conditions of these experiments are listed in Table 3. As shown in Table 3, the output wer of SiC power module in experiment is increased gradually from case_1 to case_3.
Figure 5. Comparison of transient waveforms between the module developed in this work and one commercial SiC power module (Vpp = 400 V, Ig = 200 A). (a) Developed SiC power module in this work; (b) commercial SiC power module.
Figure 5. Comparison of transient waveforms between the module developed in this work and one commercial SiC power module (Vpp = 400 V, Ig = 200 A). (a) Developed SiC power module in this work; (b) commercial SiC power module.
Table 3. Vpp and Ip parameters for the three cases.
Table 3. Vpp and Ip parameters for the three cases.
Figure 7. Turn-on transient waveform of case_2. As output power of the power module rose, the vgs spike started to show different characteristics between the upper-side and lower-side. As shown in Figure 7, the vgs spike of the upper-side was pulled down to an excessively negative voltage (—9.94 V) and accompanied by a significant oscillation with 83.3 MHz frequency during the 72 (on) interval. On the other hand, the vgs spike of the lower-side was only pulled down to a negative voltage slightly, and no oscillation was observed from the waveform.
Figure 7. Turn-on transient waveform of case_2. As output power of the power module rose, the vgs spike started to show different characteristics between the upper-side and lower-side. As shown in Figure 7, the vgs spike of the upper-side was pulled down to an excessively negative voltage (—9.94 V) and accompanied by a significant oscillation with 83.3 MHz frequency during the 72 (on) interval. On the other hand, the vgs spike of the lower-side was only pulled down to a negative voltage slightly, and no oscillation was observed from the waveform.
Figure 6. Turn-on transient waveform of case_1. In the experiment of case_1, the switching waveforms of vg; were almost normal for both upper-side and lower-side though there was minor difference between them as shown in Figure 6. The vgs of upper-side was pulled down by 12.76 V during the Tz (on) interval (as shown in Figure 4) while the lower-side’s was pulled down by 8.8 V during the 71 (07) interval. The v,; spikes for both sides were kept positive during the turn-on transient, negative ves spike was absent from the waveforms for both upper-side and lower-side of the SiC power module.
Figure 6. Turn-on transient waveform of case_1. In the experiment of case_1, the switching waveforms of vg; were almost normal for both upper-side and lower-side though there was minor difference between them as shown in Figure 6. The vgs of upper-side was pulled down by 12.76 V during the Tz (on) interval (as shown in Figure 4) while the lower-side’s was pulled down by 8.8 V during the 71 (07) interval. The v,; spikes for both sides were kept positive during the turn-on transient, negative ves spike was absent from the waveforms for both upper-side and lower-side of the SiC power module.
Figure 8. Turn-on transient waveform of case_3. For the experiment of case_3, the transient waveforms are shown in Figure 8. The Vgs spike of the upper-side oscillated more seriously than case_1 and case_2. Both the excessively positive and negative voltage spikes were observed from vg; characteristics of the upper-side, which resulted from the serious oscillation. On the other hand, the Vgs of the lower-side was pulled down to a lower negative voltage (-13.7 V), and no oscillation was observed from the waveform.
Figure 8. Turn-on transient waveform of case_3. For the experiment of case_3, the transient waveforms are shown in Figure 8. The Vgs spike of the upper-side oscillated more seriously than case_1 and case_2. Both the excessively positive and negative voltage spikes were observed from vg; characteristics of the upper-side, which resulted from the serious oscillation. On the other hand, the Vgs of the lower-side was pulled down to a lower negative voltage (-13.7 V), and no oscillation was observed from the waveform.
As shown in Table 4, with an increased output power, the lowest Ugs spike continues to decrease, and the amplitude of the Vgs pulling down rises significantly for the lower-side. On the other hand, for the upper-side, the pulling down amplitude of vg; in case_3 is smaller than that of case_2. This is because the oscillation of vgs in case_3 is more serious than that of case_2 and the highest vgs spike is up to 29.0 V. These differences of the vgs characteristics between the upper-side and the lower-side is probably attributed to the different dups/dt of drain loop for the upper-side and lower-side.
As shown in Table 4, with an increased output power, the lowest Ugs spike continues to decrease, and the amplitude of the Vgs pulling down rises significantly for the lower-side. On the other hand, for the upper-side, the pulling down amplitude of vg; in case_3 is smaller than that of case_2. This is because the oscillation of vgs in case_3 is more serious than that of case_2 and the highest vgs spike is up to 29.0 V. These differences of the vgs characteristics between the upper-side and the lower-side is probably attributed to the different dups/dt of drain loop for the upper-side and lower-side.
Figure 9. Comparison of turn-on transient waveform of vgs under different output power conditions: (a) Turn-on vg; of the upper-side; (b) turn-on v¢s of the lower-side. Table 4. Comparison of trainset waveform of vgs at turn-on transient.
Figure 9. Comparison of turn-on transient waveform of vgs under different output power conditions: (a) Turn-on vg; of the upper-side; (b) turn-on v¢s of the lower-side. Table 4. Comparison of trainset waveform of vgs at turn-on transient.
Table 5. Comparison of dups /dt between upper and lower sides. 4. Modeling and Simulation
Table 5. Comparison of dups /dt between upper and lower sides. 4. Modeling and Simulation
The equivalent circuit model of the gate loop is obtained based on the analysis of the actual physical structure of the power module and the output stage of the gate driver circuit. For the standard package outline of the half-bridge module, the internal structure of the upper-side is different from that of the lower-side. The routings of drain circuit and gate circuit inside the power module are shown in Figure 10a,b, respectively. Since all the gate input terminals are placed to the outer edge area of the upper-side of the power module, the gate routings of the lower-side must pass through the upper-side before connecting to the power chips of the lower-side.
The equivalent circuit model of the gate loop is obtained based on the analysis of the actual physical structure of the power module and the output stage of the gate driver circuit. For the standard package outline of the half-bridge module, the internal structure of the upper-side is different from that of the lower-side. The routings of drain circuit and gate circuit inside the power module are shown in Figure 10a,b, respectively. Since all the gate input terminals are placed to the outer edge area of the upper-side of the power module, the gate routings of the lower-side must pass through the upper-side before connecting to the power chips of the lower-side.
Table 6. Parasitic parameters extracted by Q3D software. The value of the equivalent current source stands for the extent of this influence, which is designated as ip_,g. The higher the slew rate of vps, the higher the ip_,g. The ip4c is given by Equation (3),
Table 6. Parasitic parameters extracted by Q3D software. The value of the equivalent current source stands for the extent of this influence, which is designated as ip_,g. The higher the slew rate of vps, the higher the ip_,g. The ip4c is given by Equation (3),
Figure 11. The equivalent circuit models of gate loop path at turn-on transient: (a) Upper-side, (b) lower-side. and shown in Figure 11a, b, respectively. The coupling effect is equivalent to a short-time current source. As this short-time current source is an external factor for the gate driver loop, it is parallel-connected to the equivalent circuit in the model. With the help of the models, vg; characteristics at the turn-on transient can be simulated.
Figure 11. The equivalent circuit models of gate loop path at turn-on transient: (a) Upper-side, (b) lower-side. and shown in Figure 11a, b, respectively. The coupling effect is equivalent to a short-time current source. As this short-time current source is an external factor for the gate driver loop, it is parallel-connected to the equivalent circuit in the model. With the help of the models, vg; characteristics at the turn-on transient can be simulated.
Figure 12. Simulation results of v’ gs Voltage spike for upper-side. For the upper-side, Ves is set to 15 V, the current source ip_,g starts to output pulse at time of 5 ns and it lasts a time interval of 7 ns in the simulation, the value of ip_,c is as listed in Table 5. The simulation results for the three cases as studied by the experiments in Section 3 are shown in Figure 12.
Figure 12. Simulation results of v’ gs Voltage spike for upper-side. For the upper-side, Ves is set to 15 V, the current source ip_,g starts to output pulse at time of 5 ns and it lasts a time interval of 7 ns in the simulation, the value of ip_,c is as listed in Table 5. The simulation results for the three cases as studied by the experiments in Section 3 are shown in Figure 12.
Figure 13. Simulation results of v's voltage spike for lower-side. OT ae - For the lower-side, the Vg. is set to 15 V, the equivalent current source of ipg starts to output pulse at time of 6 ns and it lasts a time interval of 5 ns in the simulation. The simulation results for the three cases as studied by the experiments in Section 3 are shown in Figure 13. As the output power increases, the ip_,g rises from 0.35 A to 1.34 A accordingly, v’ gs is pulled down to a lower value. There is no high frequency oscillation observed.
Figure 13. Simulation results of v's voltage spike for lower-side. OT ae - For the lower-side, the Vg. is set to 15 V, the equivalent current source of ipg starts to output pulse at time of 6 ns and it lasts a time interval of 5 ns in the simulation. The simulation results for the three cases as studied by the experiments in Section 3 are shown in Figure 13. As the output power increases, the ip_,g rises from 0.35 A to 1.34 A accordingly, v’ gs is pulled down to a lower value. There is no high frequency oscillation observed.
The pulling down amplitude of vg; spike of the lower-side increases as the output power rises in both simulation and experiment, but the pulling down amplitude of vg; of the upper-side in simulation is different from the experiment. In simulation, the pulling down amplitude of vs rises as output increases, but in experimental results the largest pulling down amplitude of vgs occurred in case_2 rather than case_3. This abnormal phenomenon in the experiment is mainly attributed to the high frequency oscillation on the pulling down waveform of vgs. As shown in Figure 9a, there is an excessively positive voltage spike of 29.0 V in case_3 during the high frequency oscillation process while the high frequency oscillation doesn’t bring the voltage spike back to a lower point as that in case_2. Table 7. Comparison of characteristics for simulation and experimental results at turn-on transient.
The pulling down amplitude of vg; spike of the lower-side increases as the output power rises in both simulation and experiment, but the pulling down amplitude of vg; of the upper-side in simulation is different from the experiment. In simulation, the pulling down amplitude of vs rises as output increases, but in experimental results the largest pulling down amplitude of vgs occurred in case_2 rather than case_3. This abnormal phenomenon in the experiment is mainly attributed to the high frequency oscillation on the pulling down waveform of vgs. As shown in Figure 9a, there is an excessively positive voltage spike of 29.0 V in case_3 during the high frequency oscillation process while the high frequency oscillation doesn’t bring the voltage spike back to a lower point as that in case_2. Table 7. Comparison of characteristics for simulation and experimental results at turn-on transient.
Table 8. Comparison of dvps /dt between the cases with external gate resistance of 5 O and 2.4 ©. Compared with that of 2.4 O, the slew rate of vps in the condition of gate resistor of 5 O. reduces significantly; accordingly, the equivalent current ip_,g from drain loop to gate driver loop due to the coupling effect at the turn-on transient also decreases dramatically.
Table 8. Comparison of dvps /dt between the cases with external gate resistance of 5 O and 2.4 ©. Compared with that of 2.4 O, the slew rate of vps in the condition of gate resistor of 5 O. reduces significantly; accordingly, the equivalent current ip_,g from drain loop to gate driver loop due to the coupling effect at the turn-on transient also decreases dramatically.
Figure 14. Transient waveform at the condition for output power of case_3 and the external gate resistor equal to 5 ©: (a) Upper-side, (b) lower-side.
Figure 14. Transient waveform at the condition for output power of case_3 and the external gate resistor equal to 5 ©: (a) Upper-side, (b) lower-side.
As the gate resistance rises, the characteristics of high frequency oscillation in the upper-side disappears for both experiment and simulation, the amplitude of the pulling down of Vgs in the upper-side is lowered significantly for both experiment and simulation. The pulling down amplitude in the experiment reduces from 28.20 V to zero while it decreases from 25.24 V to 6.92 V in the simulation. The amplitude of the pulling down of vgs in the lower-side is also reduced significantly for both experiment and simulation, which reduces from 28.66 V to 10.28 V in the experiment and decreases from 6.62 V to 3.25 V in the simulation. Table 9. Comparison of vgs characteristics between experiment and simulation.
As the gate resistance rises, the characteristics of high frequency oscillation in the upper-side disappears for both experiment and simulation, the amplitude of the pulling down of Vgs in the upper-side is lowered significantly for both experiment and simulation. The pulling down amplitude in the experiment reduces from 28.20 V to zero while it decreases from 25.24 V to 6.92 V in the simulation. The amplitude of the pulling down of vgs in the lower-side is also reduced significantly for both experiment and simulation, which reduces from 28.66 V to 10.28 V in the experiment and decreases from 6.62 V to 3.25 V in the simulation. Table 9. Comparison of vgs characteristics between experiment and simulation.
Figure 15. Simulation results of gs voltage spike for Regext = 5 O and Reext = 2.4 O: (a) Upper-side, (b) lower-side.
Figure 15. Simulation results of gs voltage spike for Regext = 5 O and Reext = 2.4 O: (a) Upper-side, (b) lower-side.
Figure 1. Photographs of the two microstrip detectors used in this work, together with a detail of their peripheral regions with bonding pads.
Figure 1. Photographs of the two microstrip detectors used in this work, together with a detail of their peripheral regions with bonding pads.
Figure 2. Cross-sectional view of the 4H-SiC microstrip structure.
Figure 2. Cross-sectional view of the 4H-SiC microstrip structure.
Figure 3. (a) Capacitance-voltage (C-V) and 1/C?-V per unit area characteristics. From the fit curve, the mean value of the donor concentration is expected to be (5.56 + 0.05) x 103 cm-3; (b) depleted layer and mean electric field as a function of applied voltage, as derived from C-V measurements. The theoretical result is obtained using 5.56 x 10!3 cm7? as the mean value of the doping concentration. was used to bias the device and measure the applied voltage. The measurement was performed with a 100 mV AC signal at 100 kHz. The donor-concentration profile as a function of the depleted layer width was determined from the slope of a 1/C2-V curve, according to [24], see Figure 3a. Please note that the C-V measurements were performed using a 4H-SiC Schottky diode with area A = 5 mm’, produced from the same wafer. A full depletion of 124 um was reached, polarizing the detector up to 600 V (Figure 3b). A mean value of <Np> = (5.20 + 0.06) x 10!5 cm-$ was determined (Figure 4).
Figure 3. (a) Capacitance-voltage (C-V) and 1/C?-V per unit area characteristics. From the fit curve, the mean value of the donor concentration is expected to be (5.56 + 0.05) x 103 cm-3; (b) depleted layer and mean electric field as a function of applied voltage, as derived from C-V measurements. The theoretical result is obtained using 5.56 x 10!3 cm7? as the mean value of the doping concentration. was used to bias the device and measure the applied voltage. The measurement was performed with a 100 mV AC signal at 100 kHz. The donor-concentration profile as a function of the depleted layer width was determined from the slope of a 1/C2-V curve, according to [24], see Figure 3a. Please note that the C-V measurements were performed using a 4H-SiC Schottky diode with area A = 5 mm’, produced from the same wafer. A full depletion of 124 um was reached, polarizing the detector up to 600 V (Figure 3b). A mean value of <Np> = (5.20 + 0.06) x 10!5 cm-$ was determined (Figure 4).
Figure 4. Donor concentration profile as a function of the depleted layer width. The full depletion of 124 um was reached at 600 V. A mean value of <Np> = 5.2 x 10!5 cm73 was determined.
Figure 4. Donor concentration profile as a function of the depleted layer width. The full depletion of 124 um was reached at 600 V. A mean value of <Np> = 5.2 x 10!5 cm73 was determined.
Figure 5. Current and current density measured at 25 °C and 200 V on the 32 strips of the two microstrip detectors, SM1 and SM3. Current values of few fA (current densities of low pA/cm?) were measured on all strips.
Figure 5. Current and current density measured at 25 °C and 200 V on the 32 strips of the two microstrip detectors, SM1 and SM3. Current values of few fA (current densities of low pA/cm?) were measured on all strips.
Figure 6. Current and current density dependence from temperature in the range 27 to 107 °C. The temperature dependence of the strip current as a function of reverse-bias voltage is shown in Figure 6. From now on, only results obtained with the detector SM1 are presented. In order to perform this measurement, the device was attached to a Teflon circuit board using a silver conductive glue. Electrical contacts were established using 25 um gold wire-bonding connections. Measurements were acquired, biasing up to 200 V the back contact with the Keithley 2410 source meter and reading the currents from the Keithley 6430 electrometer. Tests were carried out inside an environmental chamber, setting the temperature at 27 °C, 47 °C, 67 °C, 87 °C, and 107 °C, and monitoring it by means of a thermocouple placed near to the device. During each measurement, the temperature changes were monitored within +0.1 °C. The current density was calculated considering a strip active area of 5 x 1074 cm=?.
Figure 6. Current and current density dependence from temperature in the range 27 to 107 °C. The temperature dependence of the strip current as a function of reverse-bias voltage is shown in Figure 6. From now on, only results obtained with the detector SM1 are presented. In order to perform this measurement, the device was attached to a Teflon circuit board using a silver conductive glue. Electrical contacts were established using 25 um gold wire-bonding connections. Measurements were acquired, biasing up to 200 V the back contact with the Keithley 2410 source meter and reading the currents from the Keithley 6430 electrometer. Tests were carried out inside an environmental chamber, setting the temperature at 27 °C, 47 °C, 67 °C, 87 °C, and 107 °C, and monitoring it by means of a thermocouple placed near to the device. During each measurement, the temperature changes were monitored within +0.1 °C. The current density was calculated considering a strip active area of 5 x 1074 cm=?.
Figure 7. Arrhenius plots of the leakage current (and current density) versus the reverse of temperature at four different voltages. The activation energy values are from 0.57 eV to 0.65 eV in the voltage range 50 to 200 V.
Figure 7. Arrhenius plots of the leakage current (and current density) versus the reverse of temperature at four different voltages. The activation energy values are from 0.57 eV to 0.65 eV in the voltage range 50 to 200 V.
Figure 8. Mean value of resistance between two adjacent strips. and possible latent currents from adjacent strips were negligible. In order to determine the bias limit condition so that two adjacent strips can be considered isolated, we measured the interstrip resistance. Interstrip resistance measurements were carried out by measuring the current between two consecutive strips, keeping the back contact at 100 V and the guard at 0 V. One of the two strips (microstrip 2 in Figure 8) is biased from —5 V to +5 V while the current of the other strip (microstrip 1 in Figure 8), kept at 0 V, is measured by an electrometer. We repeated the test on three couples of strips. The negative slope shown in Figure 8 is due to the application of the bias voltage to microstrip 2 while measuring the current at microstrip 1. The mean value of resistance between two adjacent strips of SM1 resulted in 5.3 TO.
Figure 8. Mean value of resistance between two adjacent strips. and possible latent currents from adjacent strips were negligible. In order to determine the bias limit condition so that two adjacent strips can be considered isolated, we measured the interstrip resistance. Interstrip resistance measurements were carried out by measuring the current between two consecutive strips, keeping the back contact at 100 V and the guard at 0 V. One of the two strips (microstrip 2 in Figure 8) is biased from —5 V to +5 V while the current of the other strip (microstrip 1 in Figure 8), kept at 0 V, is measured by an electrometer. We repeated the test on three couples of strips. The negative slope shown in Figure 8 is due to the application of the bias voltage to microstrip 2 while measuring the current at microstrip 1. The mean value of resistance between two adjacent strips of SM1 resulted in 5.3 TO.
Figure 9. (a) X-ray spectrum from a 241 Am source acquired at 21 °C using the SiC microstrip detector SM1 and an ultra-low noise front-end (PRE5 no. 3); (b) detailed X-ray spectroscopy in the energy range 0 to 28 keV. elements. Conventionally, the energy resolution, that is the FWHM, is specified for the Mn Ka peak at 5.9 keV, which is 213 eV for our SiC microstrip detector at room temperature (Figure 9). It is notable that Si(Li) and silicon drift detectors can achieve 130-150 eV FWHM, and Ge detectors can even achieve 115 eV FWHM for the Mn Ka peak at 5.9 keV, but with liquid-nitrogen cooling [29].
Figure 9. (a) X-ray spectrum from a 241 Am source acquired at 21 °C using the SiC microstrip detector SM1 and an ultra-low noise front-end (PRE5 no. 3); (b) detailed X-ray spectroscopy in the energy range 0 to 28 keV. elements. Conventionally, the energy resolution, that is the FWHM, is specified for the Mn Ka peak at 5.9 keV, which is 213 eV for our SiC microstrip detector at room temperature (Figure 9). It is notable that Si(Li) and silicon drift detectors can achieve 130-150 eV FWHM, and Ge detectors can even achieve 115 eV FWHM for the Mn Ka peak at 5.9 keV, but with liquid-nitrogen cooling [29].
Figure 10. Analysis of linearity calculated on seven well-resolved peak lines, as shown in Figure 9. The percentage error from linearity is below +0.05%. The analysis of linearity calculated on seven well-resolved peak lines at 8.0, 11.87, 13.94, 17.8, 20.8, 26.35 and 59.54 keV is shown in Figure 10. The percentage error from linearity is below +0.05%.
Figure 10. Analysis of linearity calculated on seven well-resolved peak lines, as shown in Figure 9. The percentage error from linearity is below +0.05%. The analysis of linearity calculated on seven well-resolved peak lines at 8.0, 11.87, 13.94, 17.8, 20.8, 26.35 and 59.54 keV is shown in Figure 10. The percentage error from linearity is below +0.05%.
Figure 11. X-ray spectra from a 241 Am source acquired at 25 °C and at 10 V (bottom) and 200 V (top)
Figure 11. X-ray spectra from a 241 Am source acquired at 25 °C and at 10 V (bottom) and 200 V (top)
Figure 12. (a) Comparison between the two peaks at 13.94 eV obtained at 10 V and 200 V of applied voltage. The Gaussian symmetry without tails can be noticed; (b) Detected 13.94 keV photon rate as a function of the applied reverse bias.
Figure 12. (a) Comparison between the two peaks at 13.94 eV obtained at 10 V and 200 V of applied voltage. The Gaussian symmetry without tails can be noticed; (b) Detected 13.94 keV photon rate as a function of the applied reverse bias.
Figure 13. (a) X-ray spectra from 241 Am source after almost 2 and 10 h of acquisition at 30 °C ina thermostatic chamber. The very small broadening of pulser and emission lines demonstrates very good stability of the detector response to X-ray exposure; (b) linearity error after 10 h of acquisition based on K Cuand L Np X-ray monoenergetic lines.
Figure 13. (a) X-ray spectra from 241 Am source after almost 2 and 10 h of acquisition at 30 °C ina thermostatic chamber. The very small broadening of pulser and emission lines demonstrates very good stability of the detector response to X-ray exposure; (b) linearity error after 10 h of acquisition based on K Cuand L Np X-ray monoenergetic lines.
Figure 14. (a) Comparison between three X-ray spectra acquired at —20 °C, +30 °C, and +80 °C in the range 0-60 keV; (b) Detail of the X-ray spectra in the range 4~28 keV. Note a small broadening of the pulser line by increasing the operating temperature. 4. Discussion
Figure 14. (a) Comparison between three X-ray spectra acquired at —20 °C, +30 °C, and +80 °C in the range 0-60 keV; (b) Detail of the X-ray spectra in the range 4~28 keV. Note a small broadening of the pulser line by increasing the operating temperature. 4. Discussion
Figure 1. (a) Laser Scanning Microscope (LSM) image of the 4H-SiC membrane using stitching mode, obtained after the electrochemical etching (ECE) process. Circular insert added to show that the 4H-SiC membrane can be assimilated as a circle. (b) Focused ion beam (FIB) cross-section image allowing the membrane thickness determination. a a I a I a) aa) A Lext OLS4100 Laser Scanning Microscope (LSM), from Olympus Corporation (Shinjuku-ku Tokyo, Japan), was used in order to observe the full membrane using the stitching mode. Figure 1. shows the image of the membrane shape after ECE process. One can observe a slight membran asymmetric geometry, which is due to the fabrication process, i.e., to a non-uniform under-etchin; of the substrate with respect to the etching mask. Therefore, we assumed that the membrane can bi reasonably assimilated as a circle. The diameter measurements were performed in several direction and an average diameter value was evaluated at 4.5 mm. Thickness determination was performe¢ using a Strata DB235 Focused Ion Beam (FIB), from Thermo Fisher Scientific (Waltham, MA, USA To do that, we injected silver paste through the cavity of the membrane in order to fix and stiffen th suspended film to prevent any vibrations during the observations. After that, the FIB cross-sectio1 images were carried out in order to obtain a direct measurement of the film thickness as shown i1 Figure 1b. Thus, a membrane thickness of 8.8 um was measured and a thickness variation of + 0.2 un was evaluated. As expected, the thin film has a well-controlled thickness because the 4H-SiC epilaye acts as an etching stop.
Figure 1. (a) Laser Scanning Microscope (LSM) image of the 4H-SiC membrane using stitching mode, obtained after the electrochemical etching (ECE) process. Circular insert added to show that the 4H-SiC membrane can be assimilated as a circle. (b) Focused ion beam (FIB) cross-section image allowing the membrane thickness determination. a a I a I a) aa) A Lext OLS4100 Laser Scanning Microscope (LSM), from Olympus Corporation (Shinjuku-ku Tokyo, Japan), was used in order to observe the full membrane using the stitching mode. Figure 1. shows the image of the membrane shape after ECE process. One can observe a slight membran asymmetric geometry, which is due to the fabrication process, i.e., to a non-uniform under-etchin; of the substrate with respect to the etching mask. Therefore, we assumed that the membrane can bi reasonably assimilated as a circle. The diameter measurements were performed in several direction and an average diameter value was evaluated at 4.5 mm. Thickness determination was performe¢ using a Strata DB235 Focused Ion Beam (FIB), from Thermo Fisher Scientific (Waltham, MA, USA To do that, we injected silver paste through the cavity of the membrane in order to fix and stiffen th suspended film to prevent any vibrations during the observations. After that, the FIB cross-sectio1 images were carried out in order to obtain a direct measurement of the film thickness as shown i1 Figure 1b. Thus, a membrane thickness of 8.8 um was measured and a thickness variation of + 0.2 un was evaluated. As expected, the thin film has a well-controlled thickness because the 4H-SiC epilaye acts as an etching stop.
Table 1. C; and C> coefficients for circular membranes. 2.3. Membrane Vibration
Table 1. C; and C> coefficients for circular membranes. 2.3. Membrane Vibration
Figure 2. Schematic cross-sectional membrane with initial in-plane tension under uniform pressure P. function of the measured deflection, A and B coefficients can be estimated, leading to the determination of the Young’s modulus and the residual stress. The models describing the load-deflection behavior of a circular plate as a function of the pressure have been extensively discussed. Several authors examined the large deflection behavior for the pure plate case, originally described by Nadai and Way [25,26]. Beams was the first to report an experimental model using bulge test to measure the mechanical properties of thin films deposited on substrates [27]. For a circular membrane, Beams determined C; and C) values, 4 and 8/3, respectively. A more accurate numerical solution indicated that Cy can be expressed as (8/3) x (1.015 — 0.247v). Table 1 summarizes the reported value of C; and C> for circular suspended films from literature. For comparison purposes, C2 values assuming v = 0.25 are also listed.
Figure 2. Schematic cross-sectional membrane with initial in-plane tension under uniform pressure P. function of the measured deflection, A and B coefficients can be estimated, leading to the determination of the Young’s modulus and the residual stress. The models describing the load-deflection behavior of a circular plate as a function of the pressure have been extensively discussed. Several authors examined the large deflection behavior for the pure plate case, originally described by Nadai and Way [25,26]. Beams was the first to report an experimental model using bulge test to measure the mechanical properties of thin films deposited on substrates [27]. For a circular membrane, Beams determined C; and C) values, 4 and 8/3, respectively. A more accurate numerical solution indicated that Cy can be expressed as (8/3) x (1.015 — 0.247v). Table 1 summarizes the reported value of C; and C> for circular suspended films from literature. For comparison purposes, C2 values assuming v = 0.25 are also listed.
Figure 3. (a) Schematic of bulge test apparatus; (b) deflection of the circular 4H-SiC membrane, before and after, sample mounting; (c) typical topography used to measure the diaphragm deflection with LSM measurement. The bulge test setup is fully discussed in the literature, mainly for improving the methodology and the technique accuracy [16,29,34]. Indeed, the deflection measurement errors can lead to an over or under estimation of the mechanical properties. Consequently, this method requires paying special attention to the chip preparation and deflection measurements. The experimental apparatus is schematically presented in Figure 3a. The sample was mounted on a 3 x 3 cm? printed circuit board (PCB) holder with a drilled hole in the centre. Several studies have highlighted the importance of the bonding step for the reliability of the deflection measurements. The most common approach to fix the sample is to add adhesive around its edges. In such case, Jayaraman et al. observed that the sample moved during the measurement for a pressure up to 2.8 bars [35]. Mitchell et al. proposed a multi-step bonding method to seal and constrain the sample to the chuck without any displacement of the substrate [34]. Inspired by this method, we deposited an Ablebond 84-3] epoxy adhesive on the PCB and mounted the sample on it. Then, we applied the adhesive around all the edges of the sample to seal and prevent air leakage. Lastly, an annealing step of 1 h at 150 °C was carried out. For the bulge testing, the chip was placed in an airtight square cell, drilled on two lateral faces, in order to inject and measure the air pressure. The membrane is pressurized through its cavity while the front face remains at the atmospheric pressure. So, the sample was characterized under differential pressures, between 0.04 and 4 bars. Pressure regulation and measurements were carried out using both pressure controller and sensors, operating in the range of 0 to 4 bars.
Figure 3. (a) Schematic of bulge test apparatus; (b) deflection of the circular 4H-SiC membrane, before and after, sample mounting; (c) typical topography used to measure the diaphragm deflection with LSM measurement. The bulge test setup is fully discussed in the literature, mainly for improving the methodology and the technique accuracy [16,29,34]. Indeed, the deflection measurement errors can lead to an over or under estimation of the mechanical properties. Consequently, this method requires paying special attention to the chip preparation and deflection measurements. The experimental apparatus is schematically presented in Figure 3a. The sample was mounted on a 3 x 3 cm? printed circuit board (PCB) holder with a drilled hole in the centre. Several studies have highlighted the importance of the bonding step for the reliability of the deflection measurements. The most common approach to fix the sample is to add adhesive around its edges. In such case, Jayaraman et al. observed that the sample moved during the measurement for a pressure up to 2.8 bars [35]. Mitchell et al. proposed a multi-step bonding method to seal and constrain the sample to the chuck without any displacement of the substrate [34]. Inspired by this method, we deposited an Ablebond 84-3] epoxy adhesive on the PCB and mounted the sample on it. Then, we applied the adhesive around all the edges of the sample to seal and prevent air leakage. Lastly, an annealing step of 1 h at 150 °C was carried out. For the bulge testing, the chip was placed in an airtight square cell, drilled on two lateral faces, in order to inject and measure the air pressure. The membrane is pressurized through its cavity while the front face remains at the atmospheric pressure. So, the sample was characterized under differential pressures, between 0.04 and 4 bars. Pressure regulation and measurements were carried out using both pressure controller and sensors, operating in the range of 0 to 4 bars.
Figure 4. (a) Schematic diagram of the resonance frequency method. Vibration mode shapes measured using laser Doppler vibrometry for (b) (1, 1); (c) (0, 2); and (d) (1, 2) modes.
Figure 4. (a) Schematic diagram of the resonance frequency method. Vibration mode shapes measured using laser Doppler vibrometry for (b) (1, 1); (c) (0, 2); and (d) (1, 2) modes.
Table 2. Parameters used for both bulge test and finite element method (FEM) calculations. Table 3 reports the determined values of E and og. The calculated Young’s modulus values are scattered, depending on the model used. In fact, the main difference between these models is the expression of C7. Beams was the first to report a value for this dimensionless coefficient, using the spherical cap model based on a very simple approximation of the real case. However, it can lead to an under estimation of the mechanical property determination [29,38]. Therefore, the models proposed by Pan et al. and Small et al. led to close Young’s modulus values, which seems to be normal as both models were adjusted from finite element calculations [20]. Moreover, using the numerical solution proposed by Hohlfelder, we obtained almost the same Young’s modulus value. Mitchell et al explained that the difference in the governing equation, which results in measured values, could vary by as much as 20% [34]. In any case, the calculated Young’s modulus values are in reasonably good agreement with the published results in the literature for silicon carbide thin films. The residual stress value is determined using the linear term in Equation (1). In comparison with E, the stress o9 seems to be less dependent on the model used since C; is considered as constant.
Table 2. Parameters used for both bulge test and finite element method (FEM) calculations. Table 3 reports the determined values of E and og. The calculated Young’s modulus values are scattered, depending on the model used. In fact, the main difference between these models is the expression of C7. Beams was the first to report a value for this dimensionless coefficient, using the spherical cap model based on a very simple approximation of the real case. However, it can lead to an under estimation of the mechanical property determination [29,38]. Therefore, the models proposed by Pan et al. and Small et al. led to close Young’s modulus values, which seems to be normal as both models were adjusted from finite element calculations [20]. Moreover, using the numerical solution proposed by Hohlfelder, we obtained almost the same Young’s modulus value. Mitchell et al explained that the difference in the governing equation, which results in measured values, could vary by as much as 20% [34]. In any case, the calculated Young’s modulus values are in reasonably good agreement with the published results in the literature for silicon carbide thin films. The residual stress value is determined using the linear term in Equation (1). In comparison with E, the stress o9 seems to be less dependent on the model used since C; is considered as constant.
Figure 5. Dot line: Bulge test results for 4H-SiC diaphragm. Solid line: Theoretical fit.
Figure 5. Dot line: Bulge test results for 4H-SiC diaphragm. Solid line: Theoretical fit.
Table 3. Bulge test results depending on the models used. 3.2. Vibrometry Results
Table 3. Bulge test results depending on the models used. 3.2. Vibrometry Results
Figure 6. Measured spectrum of vibration of the 4H-SiC membrane associated with the corresponding mode shapes. In this study, we focused our purpose on the observed six-first vibration modes, which are clearly identified, even if the vibration amplitudes were small. The displacement spectrum of the 4H-SiC circular membrane is shown in Figure 6. The interference frequencies due to the piezoelectric excitation were also measured. The resonance peaks for asymmetric modes (1, 1), (2, 1), (3, 1), and (1, 2) seem to be splitted with lower magnitude peaks. The fabrication process led to a geometric asymmetry of the diaphragm, as previously shown in Figure 1, resulting in the creation of non-degenerated modes in asymmetric vibration modes [39,40]. Moreover, Fartash et al. reported that the presence of an anisotropic tension, due to internal stress or tension after mounting the sample, could also cause the splitting of degenerated modes. Thus, this phenomenon could shift the peaks of asymmetric vibration modes [41].
Figure 6. Measured spectrum of vibration of the 4H-SiC membrane associated with the corresponding mode shapes. In this study, we focused our purpose on the observed six-first vibration modes, which are clearly identified, even if the vibration amplitudes were small. The displacement spectrum of the 4H-SiC circular membrane is shown in Figure 6. The interference frequencies due to the piezoelectric excitation were also measured. The resonance peaks for asymmetric modes (1, 1), (2, 1), (3, 1), and (1, 2) seem to be splitted with lower magnitude peaks. The fabrication process led to a geometric asymmetry of the diaphragm, as previously shown in Figure 1, resulting in the creation of non-degenerated modes in asymmetric vibration modes [39,40]. Moreover, Fartash et al. reported that the presence of an anisotropic tension, due to internal stress or tension after mounting the sample, could also cause the splitting of degenerated modes. Thus, this phenomenon could shift the peaks of asymmetric vibration modes [41].
Figure 7. (a) Dashed lines: Computed resonance frequencies obtained with FEM calculations using the bulge test results. Solid line: Adjusted FEM calculations with the couple (E, og). Square symbols: Measured resonance frequencies determined with the vibrometry method; (b) calculated resonance frequency depending on E and oo. Dot line: Measured resonance frequency for the (0, 1) mode. Symbol lines: Calculated resonance frequencies depending on the residual stress and Young’s modulus values. Figure 7. (a) Dashed lines: Computed resonance frequencies obtained with FEM calculations using However, the residual stress value extracted from bulge test and FEM simulations are slightly different, even if the difference remains minor. This can be explained by the deflection measurements in the low-pressure range. The determination of the residual stress is allowed with the linear term of Equation (1). Thus, an error in the pressure or deflection measurements could lead to an over or under estimation of the residual stress value.
Figure 7. (a) Dashed lines: Computed resonance frequencies obtained with FEM calculations using the bulge test results. Solid line: Adjusted FEM calculations with the couple (E, og). Square symbols: Measured resonance frequencies determined with the vibrometry method; (b) calculated resonance frequency depending on E and oo. Dot line: Measured resonance frequency for the (0, 1) mode. Symbol lines: Calculated resonance frequencies depending on the residual stress and Young’s modulus values. Figure 7. (a) Dashed lines: Computed resonance frequencies obtained with FEM calculations using However, the residual stress value extracted from bulge test and FEM simulations are slightly different, even if the difference remains minor. This can be explained by the deflection measurements in the low-pressure range. The determination of the residual stress is allowed with the linear term of Equation (1). Thus, an error in the pressure or deflection measurements could lead to an over or under estimation of the residual stress value.
Figure 8. (a) LSM cross-section image of the etching profile; (b) LSM image of the membrane-undercut boundary.
Figure 8. (a) LSM cross-section image of the etching profile; (b) LSM image of the membrane-undercut boundary.
Figure 1. Schematic cross-sections of the (a) DR 4H-SiC MESFET, (b) partially low doped channel (PLDC) 4H-SiC MESFET. The 2D schematic cross-sections of the DR-MESFET and PLDC-MESFET structures are shown in Figure 1a,b, respectively. The difference between the two devices is that the PLDC-MESFET has a partially low doped channel under the gate. The PLDC was realized by high-energy ion implantation and high-temperature annealing processes. It should be noted that the P-type impurity is implanted to compensate for the formation of lightly doped regions [13]. The thickness and the concentration of the PLDC are denoted as H and Nprpc, respectively. The Np_pc was set to 1 x 10!7 em-3, 1 x 106 cm and 1 x 10'5 cm~$. The H was set from 0 to 0.25 um ina step of 0.05 um.
Figure 1. Schematic cross-sections of the (a) DR 4H-SiC MESFET, (b) partially low doped channel (PLDC) 4H-SiC MESFET. The 2D schematic cross-sections of the DR-MESFET and PLDC-MESFET structures are shown in Figure 1a,b, respectively. The difference between the two devices is that the PLDC-MESFET has a partially low doped channel under the gate. The PLDC was realized by high-energy ion implantation and high-temperature annealing processes. It should be noted that the P-type impurity is implanted to compensate for the formation of lightly doped regions [13]. The thickness and the concentration of the PLDC are denoted as H and Nprpc, respectively. The Np_pc was set to 1 x 10!7 em-3, 1 x 106 cm and 1 x 10'5 cm~$. The H was set from 0 to 0.25 um ina step of 0.05 um.
Figure 2. The effect of Nptpc and H on the device parameters: (a) Vi-Npipc and H, (b) Cgs-Np_pc and H, (¢) gm-Npipc and H, (d) lasat-Npipc and H. As showing in Figure 2, the parameters of the device are greatly affected by the doping concentratior Nptpc) and thickness (H) of the PLDC. The effect of Np_pc and H on V; is shown in Figure 2a. With the Jecrease of Npipc, the absolute value of V; decreases obviously. When H increases, the V; overall ‘rend is also decreasing. This is because the changes in Np_pc and H directly control the total carrie1 concentration in the channel, and V; is proportional to the total carrier. Figure 2b shows the effects of Nptpc and H on Cgs. With the decrease of Npypc and the increase of H, Cg, decreases. On the one hand, the PLDC suppresses the under-gate depletion layer extending to the source side, and on the other hand, it reduces the total number of carriers in the channel, thereby reducing the input capacitance of the device. In the Figure 2c, gm increases first and then decreases. The reason for this formation may be that the thinner low doped layer can increase the gate’s ability to control the current oy inhibiting the diffusion of the depletion layer to some extent. When H is thick enough, the ability of he gate to control the current will be reduced. So, gm decreases. In Figure 2d, Igsat is roughly decreased is H increases and Npypc decreases. This is mainly caused by the decrease of the channel carrie1 concentration. When H is 0.25 um, the parameters exhibit a sharp decrease and the DC characteristic of the device becomes poor. It is indicated by the simulation results that the PLDC-MESFET has smalle1 values of Cos, 2m, Vt and Igsat aS Compared to those of the original device.
Figure 2. The effect of Nptpc and H on the device parameters: (a) Vi-Npipc and H, (b) Cgs-Np_pc and H, (¢) gm-Npipc and H, (d) lasat-Npipc and H. As showing in Figure 2, the parameters of the device are greatly affected by the doping concentratior Nptpc) and thickness (H) of the PLDC. The effect of Np_pc and H on V; is shown in Figure 2a. With the Jecrease of Npipc, the absolute value of V; decreases obviously. When H increases, the V; overall ‘rend is also decreasing. This is because the changes in Np_pc and H directly control the total carrie1 concentration in the channel, and V; is proportional to the total carrier. Figure 2b shows the effects of Nptpc and H on Cgs. With the decrease of Npypc and the increase of H, Cg, decreases. On the one hand, the PLDC suppresses the under-gate depletion layer extending to the source side, and on the other hand, it reduces the total number of carriers in the channel, thereby reducing the input capacitance of the device. In the Figure 2c, gm increases first and then decreases. The reason for this formation may be that the thinner low doped layer can increase the gate’s ability to control the current oy inhibiting the diffusion of the depletion layer to some extent. When H is thick enough, the ability of he gate to control the current will be reduced. So, gm decreases. In Figure 2d, Igsat is roughly decreased is H increases and Npypc decreases. This is mainly caused by the decrease of the channel carrie1 concentration. When H is 0.25 um, the parameters exhibit a sharp decrease and the DC characteristic of the device becomes poor. It is indicated by the simulation results that the PLDC-MESFET has smalle1 values of Cos, 2m, Vt and Igsat aS Compared to those of the original device.
Figure 3. The effects of Np_pc and H on the PAE. The influences of the doping concentration and thickness on the PAE are shown in Figure It can be seen that when H is smaller than 0.20 um, the PAE of the device increases with the decrea: of Nptpc. When H is 0.20 um and Nprpc is 1 x 10!5 em-$ or 1 x 10!° cm", the PAE of the devi: decreases sharply. When H is 0.20 um and Npypc is 1 x 10!” cm73, the PAE of the device increasé When H is 0.25 um, the simulation results show that the DC characteristics and AC characteristics « the device are poor, and the PAE of these structures is low. The maximum value of the PAE is obtaine when the Nprpc is 1 x 10/5 cm7, the H is 0.15 um. The PAE of the new device is 43.67% while tk PAE of the original device is 23.43%. The optimized PAE is increased by 86.38%. The PAE of tk TUU-MESFET and DRBL AlGaN/GaN HEMT increase 18% and 48%, respectively. So, the PLDC has great effect on improving the PAE of the device. In the paper 107 W CW SiC MESFET with 48.1% PA the experimental PAE of the device at 2 W (33 dBm) is close to 25% [17]. The PAE of the DR-MESFET 23.43% at 0.63 W (28 dBm). This is essentially consistent with the simulation results.
Figure 3. The effects of Np_pc and H on the PAE. The influences of the doping concentration and thickness on the PAE are shown in Figure It can be seen that when H is smaller than 0.20 um, the PAE of the device increases with the decrea: of Nptpc. When H is 0.20 um and Nprpc is 1 x 10!5 em-$ or 1 x 10!° cm", the PAE of the devi: decreases sharply. When H is 0.20 um and Npypc is 1 x 10!” cm73, the PAE of the device increasé When H is 0.25 um, the simulation results show that the DC characteristics and AC characteristics « the device are poor, and the PAE of these structures is low. The maximum value of the PAE is obtaine when the Nprpc is 1 x 10/5 cm7, the H is 0.15 um. The PAE of the new device is 43.67% while tk PAE of the original device is 23.43%. The optimized PAE is increased by 86.38%. The PAE of tk TUU-MESFET and DRBL AlGaN/GaN HEMT increase 18% and 48%, respectively. So, the PLDC has great effect on improving the PAE of the device. In the paper 107 W CW SiC MESFET with 48.1% PA the experimental PAE of the device at 2 W (33 dBm) is close to 25% [17]. The PAE of the DR-MESFET 23.43% at 0.63 W (28 dBm). This is essentially consistent with the simulation results.
Figure 4. The effect of device parameters on PAE: (a) PAE-V+ and gin, (b) PAE-Cgs and Igsat- Figure 4a,b shows the influence of the parameters on PAE at the same bias when Vg, is —8.0 V, Vas 3 28 V, RF is 850 MHz and Pavs_dBm is 28 dBm. As shown in Figure 4a, the PAE increases with the icrease of V; when gm is a constant. When V; is a constant, the PAE also increases with the increase f gm. When gm is between 40 and 60 mS, the PAE of the device has the biggest change. This can e observed by the distance between the two curves. Figure 4b shows the influence of Igsat and Cgs n the PAE. With the increase of Cgs, the PAE decreases. With the increase of Idsat, the PAE increase urthermore, the larger Igsat is, the slower PAE increases.
Figure 4. The effect of device parameters on PAE: (a) PAE-V+ and gin, (b) PAE-Cgs and Igsat- Figure 4a,b shows the influence of the parameters on PAE at the same bias when Vg, is —8.0 V, Vas 3 28 V, RF is 850 MHz and Pavs_dBm is 28 dBm. As shown in Figure 4a, the PAE increases with the icrease of V; when gm is a constant. When V; is a constant, the PAE also increases with the increase f gm. When gm is between 40 and 60 mS, the PAE of the device has the biggest change. This can e observed by the distance between the two curves. Figure 4b shows the influence of Igsat and Cgs n the PAE. With the increase of Cgs, the PAE decreases. With the increase of Idsat, the PAE increase urthermore, the larger Igsat is, the slower PAE increases.
Table 1. Comparison of performance parameters of the two structures. 4. Conclusions
Table 1. Comparison of performance parameters of the two structures. 4. Conclusions
Figure 1. The all-SiC fabrication process flow. (a) A rendering of the Michigan-style 3C-SiC probe. The process flow inside the red rectangle shows the cross-section at the electrode sites while the blue rectangle provides the cross-section at the contact pads on the tab. (b) Starting SOI wafer, (c) ~8 um of p-type 3C-SiC was grown on top, followed by ~2 um of heavily n-type (n*) 3C-SiC. (d) The wafer was coated with photoresist and (e) patterned via photolithography. (f) DRIE process was used to form the conductive n* mesas and (g) a thin a-SiC insulating layer was deposited on top via PECVD. (h) Photoresist was then patterned with photolithography and (i) the a-SiC was etched to form windows for the electrode sites using a RIE process. (j) After the a-SiC windows were opened, a layer of titanium, followed by gold, was deposited on the contact pads and thermally annealed. A deep DRIE etch through both epi layers and the oxide was performed to (k;) define the probes and (kz) form through-holes in the contact pads. (1;, 1,) The oxide layer was etched in HF (49%) to release the probes. (mj, m ) Back-thinning via DRIE was performed to remove the residual silicon from the SOI device layer. Since p-n junctions are formed between the n* and p epitaxial films, back-to-back diodes are present between adjacent traces, which provides isolation. This isolation was evaluated by measuring the forward and reverse blocking voltages of test structures consisting of p-n diodes and n-p-n junctions formed between adjacent traces that were built on the 3C-SiC wafer. A Keithley 2400 SourceMeter (Tektronix, Inc., Beaverton, OR, USA) was used to generate current-voltage (I-V) plots for adjacent traces to observe these voltages. The voltage was increased from —10 V to +10 V ata rate of 0.1 V/s for the diodes and n-p-n junctions, and the observed currents recorded. The forward voltage was estimated using a semi-logarithmic current scale I-V plot [40]. The breakdown voltage occurs when the current rapidly increases during application of negative voltage. The root mean square (rms) of the current amplitude between breakdown and forward potentials for the diodes was defined as reverse leakage current [33]. The threshold current for defining the breakdown voltages was 10 LA.
Figure 1. The all-SiC fabrication process flow. (a) A rendering of the Michigan-style 3C-SiC probe. The process flow inside the red rectangle shows the cross-section at the electrode sites while the blue rectangle provides the cross-section at the contact pads on the tab. (b) Starting SOI wafer, (c) ~8 um of p-type 3C-SiC was grown on top, followed by ~2 um of heavily n-type (n*) 3C-SiC. (d) The wafer was coated with photoresist and (e) patterned via photolithography. (f) DRIE process was used to form the conductive n* mesas and (g) a thin a-SiC insulating layer was deposited on top via PECVD. (h) Photoresist was then patterned with photolithography and (i) the a-SiC was etched to form windows for the electrode sites using a RIE process. (j) After the a-SiC windows were opened, a layer of titanium, followed by gold, was deposited on the contact pads and thermally annealed. A deep DRIE etch through both epi layers and the oxide was performed to (k;) define the probes and (kz) form through-holes in the contact pads. (1;, 1,) The oxide layer was etched in HF (49%) to release the probes. (mj, m ) Back-thinning via DRIE was performed to remove the residual silicon from the SOI device layer. Since p-n junctions are formed between the n* and p epitaxial films, back-to-back diodes are present between adjacent traces, which provides isolation. This isolation was evaluated by measuring the forward and reverse blocking voltages of test structures consisting of p-n diodes and n-p-n junctions formed between adjacent traces that were built on the 3C-SiC wafer. A Keithley 2400 SourceMeter (Tektronix, Inc., Beaverton, OR, USA) was used to generate current-voltage (I-V) plots for adjacent traces to observe these voltages. The voltage was increased from —10 V to +10 V ata rate of 0.1 V/s for the diodes and n-p-n junctions, and the observed currents recorded. The forward voltage was estimated using a semi-logarithmic current scale I-V plot [40]. The breakdown voltage occurs when the current rapidly increases during application of negative voltage. The root mean square (rms) of the current amplitude between breakdown and forward potentials for the diodes was defined as reverse leakage current [33]. The threshold current for defining the breakdown voltages was 10 LA.
Figure 2. Analysis of epitaxial SiC results. (a) Cross-section SEM micrograph of the 3C-SiC epi films on SOL (b) AFM image (tapping mode) of the 3C-SiC epiwafer specular region on the wafer periphery that shows typical 3C-SiC surface morphology (mean roughness of ~21 nm). (c) AFM image (tapping mode) of the rough surface of the same epiwafer (center) (mean roughness of ~244 nm). The devices were fabricated from the center of the wafer. A cross-sectional SEM view of the wafer, which allows for accurate estimation of film thickness (n*-, p-SiC, Si device film, and buried oxide), is shown in Figure 2a. This figure highlights various layers and the approximate thickness of each layer on the wafer used for the fabrication. The two epitaxial 3C-SiC films were measured, and their combined thickness determined to be ~10 um. The SOI Si device layer (~26 um), as well as the thin (~2 um) buried oxide layer are also visible in this figure. The epitaxial n* film in the center of the wafer was quite rough with a mean surface roughness of ~244 nm and smoother near the wafer edge with a mean surface roughness of ~21 nm. Figure 2b shows surface morphology of the smooth n* layer, which was taken using a DI AFM (Dimension 3100). Although rough in the wafer center (Figure 2c), the surface roughness was low enough for thick layers of photoresist to properly cover the entire surface for the subsequent fabrication steps. However, this roughness would be expected to impact device electrical performance, particularly p-n diode leakage current.
Figure 2. Analysis of epitaxial SiC results. (a) Cross-section SEM micrograph of the 3C-SiC epi films on SOL (b) AFM image (tapping mode) of the 3C-SiC epiwafer specular region on the wafer periphery that shows typical 3C-SiC surface morphology (mean roughness of ~21 nm). (c) AFM image (tapping mode) of the rough surface of the same epiwafer (center) (mean roughness of ~244 nm). The devices were fabricated from the center of the wafer. A cross-sectional SEM view of the wafer, which allows for accurate estimation of film thickness (n*-, p-SiC, Si device film, and buried oxide), is shown in Figure 2a. This figure highlights various layers and the approximate thickness of each layer on the wafer used for the fabrication. The two epitaxial 3C-SiC films were measured, and their combined thickness determined to be ~10 um. The SOI Si device layer (~26 um), as well as the thin (~2 um) buried oxide layer are also visible in this figure. The epitaxial n* film in the center of the wafer was quite rough with a mean surface roughness of ~244 nm and smoother near the wafer edge with a mean surface roughness of ~21 nm. Figure 2b shows surface morphology of the smooth n* layer, which was taken using a DI AFM (Dimension 3100). Although rough in the wafer center (Figure 2c), the surface roughness was low enough for thick layers of photoresist to properly cover the entire surface for the subsequent fabrication steps. However, this roughness would be expected to impact device electrical performance, particularly p-n diode leakage current.
Figure 3. Physical characterization of the completed neural probe. (a) Optical image of a freestanding all-SiC probe after release. (b) SEM image of the shank tip showing four of the electrode sites and a magnified image of a single electrode site (inset). (c) SEM image of some of the metal contact pads with through holes. The shank is 5.1 mm long and the length of the tapered portion is 2.4 mm. The tab is 6.64 mm wide and 2.3 mm long, excluding the semi-circular top portion. The surface roughness of the electrode sites is shown in Figure 2c. PRET SEO GEE SARencwneor ore awe tame SORT MERGES mma drs esrE amma tAS ee ese MUANIE Aid AR OMDIE a: TON PES eTeceaiees Feeaiater Ente Sfatdeesoeeres See Neheuis™ The probe’s shank, which contains the traces ana. electrode sites, is shown in Figure 3b. This figure shows a scanning electron micrograph of the electrode sites, which have a-SiC windows on top tc allow contact with the extracellular environment. The traces and electrode sites are mesas formed from the n* 3C-SiC film. There are no metallic components on the shank, which is a homogeneous structure consisting entirely of SiC. The pads, which are shown in Figure 3c, contain titanium and gold layers in order to provide ohmic connections to external electronic devices via the Omnetics connector. However, since the metallic pads are not in direct contact with brain tissue, the issues regarding delamination of metallic parts and compatibility with CNS tissue are not a concern.
Figure 3. Physical characterization of the completed neural probe. (a) Optical image of a freestanding all-SiC probe after release. (b) SEM image of the shank tip showing four of the electrode sites and a magnified image of a single electrode site (inset). (c) SEM image of some of the metal contact pads with through holes. The shank is 5.1 mm long and the length of the tapered portion is 2.4 mm. The tab is 6.64 mm wide and 2.3 mm long, excluding the semi-circular top portion. The surface roughness of the electrode sites is shown in Figure 2c. PRET SEO GEE SARencwneor ore awe tame SORT MERGES mma drs esrE amma tAS ee ese MUANIE Aid AR OMDIE a: TON PES eTeceaiees Feeaiater Ente Sfatdeesoeeres See Neheuis™ The probe’s shank, which contains the traces ana. electrode sites, is shown in Figure 3b. This figure shows a scanning electron micrograph of the electrode sites, which have a-SiC windows on top tc allow contact with the extracellular environment. The traces and electrode sites are mesas formed from the n* 3C-SiC film. There are no metallic components on the shank, which is a homogeneous structure consisting entirely of SiC. The pads, which are shown in Figure 3c, contain titanium and gold layers in order to provide ohmic connections to external electronic devices via the Omnetics connector. However, since the metallic pads are not in direct contact with brain tissue, the issues regarding delamination of metallic parts and compatibility with CNS tissue are not a concern.
Figure 4. All-SiC p-n diode and n-p-n junction characterization and electrochemistry for four test microelectrodes with an area of 491 m2. (a) I-V measured from a p-n diode and a n-p-n junction between adjacent traces fabricated on the same wafer used for probe fabrication. (b) The cyclic voltammetry curves swept between +800 mV and —600 mV with a scan rate of 50 mV/s. (c) EIS Impedance (Z) magnitude (~165 kO. @1kHz) and (d) impedance phase angles. The curve for each microelectrode (b-d) is the average of three replicates.
Figure 4. All-SiC p-n diode and n-p-n junction characterization and electrochemistry for four test microelectrodes with an area of 491 m2. (a) I-V measured from a p-n diode and a n-p-n junction between adjacent traces fabricated on the same wafer used for probe fabrication. (b) The cyclic voltammetry curves swept between +800 mV and —600 mV with a scan rate of 50 mV/s. (c) EIS Impedance (Z) magnitude (~165 kO. @1kHz) and (d) impedance phase angles. The curve for each microelectrode (b-d) is the average of three replicates.
Figure 1. Dimension parameters and geometric shape of the Berkovich indenter: (a) model diagram, (b) top view, (c) side view, and (d) 3-D solid model. where R is the indenter nose radius, d* is the distance from the nose vertex to the top of the ideal indenter, a is the angle between the edge line and the centerline, 0 is the angle between the edge plane and the centerline, d; is the distance from Section 1 to the nose vertex, d> is the distance from Section 2 to the nose vertex, rg is the radius of Section 1, r is the circular arc radius of the intersection between the sphere and the triangular pyramid, and | is the length of the intersection between the section which is normally aligned to the centerline and the edge plane in the transition part. The normal projected area of the different indenter heights can be calculated using Equation (8).
Figure 1. Dimension parameters and geometric shape of the Berkovich indenter: (a) model diagram, (b) top view, (c) side view, and (d) 3-D solid model. where R is the indenter nose radius, d* is the distance from the nose vertex to the top of the ideal indenter, a is the angle between the edge line and the centerline, 0 is the angle between the edge plane and the centerline, d; is the distance from Section 1 to the nose vertex, d> is the distance from Section 2 to the nose vertex, rg is the radius of Section 1, r is the circular arc radius of the intersection between the sphere and the triangular pyramid, and | is the length of the intersection between the section which is normally aligned to the centerline and the edge plane in the transition part. The normal projected area of the different indenter heights can be calculated using Equation (8).
Figure 2. Force analysis model in the ductility leading stage. where Fy, is the normal force component caused by the elastic restoring force, F;,2 is the normal force component caused by the frictional and adhesive forces, Fy,,3 is the normal force component caused by the chip formation force, F4;1 is the tangential force component caused by the elastic restoring force, F419 is the tangential force component caused by the frictional and adhesive force, and F4;3 is the tangential force component caused by the chip formation force. The normal force components can be calculated using Equation (12).
Figure 2. Force analysis model in the ductility leading stage. where Fy, is the normal force component caused by the elastic restoring force, F;,2 is the normal force component caused by the frictional and adhesive forces, Fy,,3 is the normal force component caused by the chip formation force, F4;1 is the tangential force component caused by the elastic restoring force, F419 is the tangential force component caused by the frictional and adhesive force, and F4;3 is the tangential force component caused by the chip formation force. The normal force components can be calculated using Equation (12).
Figure 3. Core components of the TI 950 Triboindenter. Tek tras oe Om TLIC GOULS LIS 1IVOD LAU YI LLIS TIA. A laser cutting machine (HGLaser LCC0130-CO2, HGTECH, Wuhan, China) was used to prepare the sample used in this study. A nanomechanical test instrument (TI 950 Triboindenter, Hysitron, Minneapolis, MN, USA), with load sensitivity less than 30 nN and displacement sensitivity less than 0.2 nm, was used to scratch the sample surface and record the information of the scratching depth, tangential force, normal force, and time and to obtain in situ scanning probe microscopy (SPM) images. The instrument is shown in Figure 3. Scanning electron micrographs of the scratch were generated using a foucused ion beam-scanning electron microscope (FIB-SEM) system (Helios NanoLab 600i, FEI, Hillsboro, OR, USA).
Figure 3. Core components of the TI 950 Triboindenter. Tek tras oe Om TLIC GOULS LIS 1IVOD LAU YI LLIS TIA. A laser cutting machine (HGLaser LCC0130-CO2, HGTECH, Wuhan, China) was used to prepare the sample used in this study. A nanomechanical test instrument (TI 950 Triboindenter, Hysitron, Minneapolis, MN, USA), with load sensitivity less than 30 nN and displacement sensitivity less than 0.2 nm, was used to scratch the sample surface and record the information of the scratching depth, tangential force, normal force, and time and to obtain in situ scanning probe microscopy (SPM) images. The instrument is shown in Figure 3. Scanning electron micrographs of the scratch were generated using a foucused ion beam-scanning electron microscope (FIB-SEM) system (Helios NanoLab 600i, FEI, Hillsboro, OR, USA).
Table 1. Scratch test parameters. 4. Results, Analysis, and Discussion
Table 1. Scratch test parameters. 4. Results, Analysis, and Discussion
where Fmax is the maximum load. For standard fused quartz, the hardness is 9.5 GPa. For the Berkovich indenter used in this study, a = 77.3°, 6 = 57.64°, 0 = 65.27°, and y = 60°. Table 2 shows the indenter height and projected area for a variety of maximum loads. Using least squares, the projected area was related to the indenter height by Ap = 25.58 x (123.8 + d )*, as shown in Figure 4. The indenter nose radius was calculated as R = 4952 nm via Equation (8).
where Fmax is the maximum load. For standard fused quartz, the hardness is 9.5 GPa. For the Berkovich indenter used in this study, a = 77.3°, 6 = 57.64°, 0 = 65.27°, and y = 60°. Table 2 shows the indenter height and projected area for a variety of maximum loads. Using least squares, the projected area was related to the indenter height by Ap = 25.58 x (123.8 + d )*, as shown in Figure 4. The indenter nose radius was calculated as R = 4952 nm via Equation (8).
Figure 5. Full view and enlarged image of a scratch using SEM. The surface morphology of the scratch is shown in Figure 5. It was observed in the enlarged image that material is removed but no cracks are formed in the surface at Position 1. There are cracks at the bottom of the scratch at Positions 2 to 4; these are perpendicular to the scratch motion and are the result of median crack closure and lateral crack growth due to the residual stress caused by the indenter. The size of the cracks was amplified with increasing scratching depth. Subsurface cracks were revealed with the scanning electron microscope. Therefore, the results show that the ductile-brittle transition of 4H-SiC is located before Position 2, as shown in Figure 5, and the corresponding scratch length ranges from 0 to 80 um, with the scratching depth ranging from 0 to 120 nm.
Figure 5. Full view and enlarged image of a scratch using SEM. The surface morphology of the scratch is shown in Figure 5. It was observed in the enlarged image that material is removed but no cracks are formed in the surface at Position 1. There are cracks at the bottom of the scratch at Positions 2 to 4; these are perpendicular to the scratch motion and are the result of median crack closure and lateral crack growth due to the residual stress caused by the indenter. The size of the cracks was amplified with increasing scratching depth. Subsurface cracks were revealed with the scanning electron microscope. Therefore, the results show that the ductile-brittle transition of 4H-SiC is located before Position 2, as shown in Figure 5, and the corresponding scratch length ranges from 0 to 80 um, with the scratching depth ranging from 0 to 120 nm.
Figure 6. Tangential force as a function of lateral displacement. Figure 7. Scratching depth as a function of lateral displacement.
Figure 6. Tangential force as a function of lateral displacement. Figure 7. Scratching depth as a function of lateral displacement.
depth versus lateral displacement curve. In the elasticity leading stage, i-e., where the scratching depth is less than 40 nm, the experimental data were plugged into Equation (9), and we received a frictional and adhesive coefficient of : = 0.31; this is much larger than the frictional coefficient, which is equal to 0.05 [34].
depth versus lateral displacement curve. In the elasticity leading stage, i-e., where the scratching depth is less than 40 nm, the experimental data were plugged into Equation (9), and we received a frictional and adhesive coefficient of : = 0.31; this is much larger than the frictional coefficient, which is equal to 0.05 [34].
The sources of error in this study are as follows: (1) The frictional and adhesive coefficient between the indenter and sample surface is not a constant in the process of scratching when loaded linearly [41], but it was simplified to a constant in this study. (2) The wear of the indenter was ignored. (3) The
The sources of error in this study are as follows: (1) The frictional and adhesive coefficient between the indenter and sample surface is not a constant in the process of scratching when loaded linearly [41], but it was simplified to a constant in this study. (2) The wear of the indenter was ignored. (3) The
Table 3. Repeated test results. Figure 8. Average contact pressure as a function of scratching depth.
Table 3. Repeated test results. Figure 8. Average contact pressure as a function of scratching depth.
Table 4. Indenter height and contact area for different loads. 5. Summary and Conclusions
Table 4. Indenter height and contact area for different loads. 5. Summary and Conclusions
Table 1. Grinding conditions used in experiments.
Table 1. Grinding conditions used in experiments.
Figure 1. Principle of workpiece rotation grinding.
Figure 1. Principle of workpiece rotation grinding.
Table 2. Hardness and elastic modulus of Single crystal 6H-SiC substrates by quasi-static indentation.
Table 2. Hardness and elastic modulus of Single crystal 6H-SiC substrates by quasi-static indentation.
Figure 2. Experimental apparatus for cluster MR effect in plane polishing. workpiece was static, while the polishing plates rotated at C1 = 200 r/min to machine the workpiece for 35 min, thus producing arc polishing belts on the workpiece. In the experiment, water-based MR fluids mixed with certain proportions of abrasives were used as MR polishing fluids. These MR polishing fluids consisted mainly of W3.5 carbonyl iron powders (4 wt.%), deionized water (88 wt.%), W3.5 diamond powders (4 wt.%), and stabilizer (4 wt.%).
Figure 2. Experimental apparatus for cluster MR effect in plane polishing. workpiece was static, while the polishing plates rotated at C1 = 200 r/min to machine the workpiece for 35 min, thus producing arc polishing belts on the workpiece. In the experiment, water-based MR fluids mixed with certain proportions of abrasives were used as MR polishing fluids. These MR polishing fluids consisted mainly of W3.5 carbonyl iron powders (4 wt.%), deionized water (88 wt.%), W3.5 diamond powders (4 wt.%), and stabilizer (4 wt.%).
Figure 3. Surface topography of nanoindentation.
Figure 3. Surface topography of nanoindentation.
Figure 4. Test results of Single crystal 6H-SiC substrates under small loads (a) Load and depth curve in small loads of C face and (b) Load and depth curve in small loads of Si face. By using the static stiffness method, the load-depth curves between loads and indentation depth of the indenter are shown in Figures 4 and 5. Here, at 1.941 mN, a slight pop-in appeared on the C surface of SiC (considering the effects of the soft base of hot melt adhesives, the indentation depth was not used as a reference standard), while a micro pop-in was found on Si surface of 2.710 mN. Therefore, pop-ins under small loads were considered to be the turning point where materials changed from elastic to plastic deformation. Similarly, under higher loads, micro pop-ins appeared on the C and Si surfaces of SiC in 385.362 mN and 448.217 mN, respectively, showing that obvious brittle fractures occurred to the SiC materials under these loads.
Figure 4. Test results of Single crystal 6H-SiC substrates under small loads (a) Load and depth curve in small loads of C face and (b) Load and depth curve in small loads of Si face. By using the static stiffness method, the load-depth curves between loads and indentation depth of the indenter are shown in Figures 4 and 5. Here, at 1.941 mN, a slight pop-in appeared on the C surface of SiC (considering the effects of the soft base of hot melt adhesives, the indentation depth was not used as a reference standard), while a micro pop-in was found on Si surface of 2.710 mN. Therefore, pop-ins under small loads were considered to be the turning point where materials changed from elastic to plastic deformation. Similarly, under higher loads, micro pop-ins appeared on the C and Si surfaces of SiC in 385.362 mN and 448.217 mN, respectively, showing that obvious brittle fractures occurred to the SiC materials under these loads.
Figure 5. Test results of Single crystal 6H-SiC substrates under large loads (a) Load and depth curve in large loads of C face and (b) Load and depth curve in large loads of Si face. strain on the materials. Therefore, the effective evaluation and test of the critical stress and strain of the materials provided an important basis for analyzing the material removed.
Figure 5. Test results of Single crystal 6H-SiC substrates under large loads (a) Load and depth curve in large loads of C face and (b) Load and depth curve in large loads of Si face. strain on the materials. Therefore, the effective evaluation and test of the critical stress and strain of the materials provided an important basis for analyzing the material removed.
Figure 6. Schematic diagram of fixation abrasive grinding. Since the grains in the grinding experiment were always fixed onto the grinding wheels, it is known as machining with fixed grinding grains (Figure 6). Figure 7 presents the surface SEM morphologies of ground 6H-SiC substrates. Note also that the diameter, feed, and linear speed of the grinding wheels influences the surface finish, so the morphologies of the machined surfaces obviously changed and the methods for removing material were also different. Under the No.1 process condition, most single crystal SiC was removed through brittle fracture and small amounts of plastic removal. After decreasing the feed of the grinding wheels in the No.2 process, brittle removal dominated and there was more plastic removal. As process No.3 shows, the linear speed of the grinding wheels affected the material removal modes, and the faster the linear speed, the larger the proportion of plastic removal. Although same process parameters were used in the No.3 and No.4 conditions, No.4 resulted in completely different effects where materials were mainly removed via the plastic mode because the grains in the grinding wheels had different diameters and densities.
Figure 6. Schematic diagram of fixation abrasive grinding. Since the grains in the grinding experiment were always fixed onto the grinding wheels, it is known as machining with fixed grinding grains (Figure 6). Figure 7 presents the surface SEM morphologies of ground 6H-SiC substrates. Note also that the diameter, feed, and linear speed of the grinding wheels influences the surface finish, so the morphologies of the machined surfaces obviously changed and the methods for removing material were also different. Under the No.1 process condition, most single crystal SiC was removed through brittle fracture and small amounts of plastic removal. After decreasing the feed of the grinding wheels in the No.2 process, brittle removal dominated and there was more plastic removal. As process No.3 shows, the linear speed of the grinding wheels affected the material removal modes, and the faster the linear speed, the larger the proportion of plastic removal. Although same process parameters were used in the No.3 and No.4 conditions, No.4 resulted in completely different effects where materials were mainly removed via the plastic mode because the grains in the grinding wheels had different diameters and densities.
Figure 7. Morphology of Single crystal 6H-SiC substrates ground with different grades of grit (a) No.1 (Ra 0.303 pm), (b) No.2 (Ra 0.029 um), (c) No.3 (Ra 0.015 pum) and (d) No.4 (Ra 0.002 um).
Figure 7. Morphology of Single crystal 6H-SiC substrates ground with different grades of grit (a) No.1 (Ra 0.303 pm), (b) No.2 (Ra 0.029 um), (c) No.3 (Ra 0.015 pum) and (d) No.4 (Ra 0.002 um).
Figure 8. Three-Body and two-body abrasion. was exerted on single abrasives under the same loads, and the larger the material removed, the rougher the surface was.
Figure 8. Three-Body and two-body abrasion. was exerted on single abrasives under the same loads, and the larger the material removed, the rougher the surface was.
Figure 9. Morphology of single crystal 6H-SiC substrates after lapping. (a) After lapping by W14 diamond. (b) After lapping by W1.5 diamond.
Figure 9. Morphology of single crystal 6H-SiC substrates after lapping. (a) After lapping by W14 diamond. (b) After lapping by W1.5 diamond.
Figure 10. Contact state diagram of the abrasives, workpiece, and lapping plate. (a) Ideal contact state. (b) Actual contact state. In accordance with the equilibrium condition of forces, the following equation is obtained.
Figure 10. Contact state diagram of the abrasives, workpiece, and lapping plate. (a) Ideal contact state. (b) Actual contact state. In accordance with the equilibrium condition of forces, the following equation is obtained.
Figure 11. Scanning electron microscope (SEM) morphology of Single crystal 6H-SiC wafer polishing belt. (a) Schematic diagram of polishing, (b) schematic diagram of the polishing belt, (c) SEM morphology of entrance and (d) SEM morphology of exit. Figure 11 shows the surface SEM images at the entrance and exit of the micro grinding heads in the olishing belts on the 6H-SiC substrates obtained from the experiment. Note the deep elastic-plastic rooves where the arc polishing belts entered the surfaces of single crystal 6H-SiC; these grooves were leeper at the entry edge and then became shallower towards the interior, and since there were no rooves where the arc polishing belts exited, the surfaces were smoother and flatter. However, some its and pores generated by the lapping process remained but even though the polishing belts left leep grooves, there were no brittle removal scratches.
Figure 11. Scanning electron microscope (SEM) morphology of Single crystal 6H-SiC wafer polishing belt. (a) Schematic diagram of polishing, (b) schematic diagram of the polishing belt, (c) SEM morphology of entrance and (d) SEM morphology of exit. Figure 11 shows the surface SEM images at the entrance and exit of the micro grinding heads in the olishing belts on the 6H-SiC substrates obtained from the experiment. Note the deep elastic-plastic rooves where the arc polishing belts entered the surfaces of single crystal 6H-SiC; these grooves were leeper at the entry edge and then became shallower towards the interior, and since there were no rooves where the arc polishing belts exited, the surfaces were smoother and flatter. However, some its and pores generated by the lapping process remained but even though the polishing belts left leep grooves, there were no brittle removal scratches.
Table 3. Calculating Parameters. When the data in Table 3 were substituted into Equations (18) and (19), the theoretical pressures of abrasives at the entrance and exit of workpieces were computed as 1514.27 uN and 3.47 uN, respectively; this meant they were in the mechanical range for single crystal SiC producing elastic-plastic and elastic deformations and therefore single crystal SiC materials were removed in full elastic-plastic mode, thus realizing machining without any sub-surface damage.
Table 3. Calculating Parameters. When the data in Table 3 were substituted into Equations (18) and (19), the theoretical pressures of abrasives at the entrance and exit of workpieces were computed as 1514.27 uN and 3.47 uN, respectively; this meant they were in the mechanical range for single crystal SiC producing elastic-plastic and elastic deformations and therefore single crystal SiC materials were removed in full elastic-plastic mode, thus realizing machining without any sub-surface damage.
Figure 1. Experimental and simulated Rutherford backscattering spectrometry (RBS) spectra of the SiC films deposited on (a) Si substrate at 200 W; (b) Si substrate at 400 W; (c) AIN/Si substrate at 200 W and; (d) AIN/Si substrate at 400 W. 1pproximately 400 nm) consisted of SiC with 10% excess carbon. The next layer with a thickness f 250 nm had about 50% carbon excess and a substantial drop in the oxygen content was observed he subsequent layer of 170 nm was fully stoichiometric, followed by the last layer of 145 nm adjacent ) the Si surface, where 10% carbon excess was found. When investigating the incorporated oxygen 1 the first layers of the SiC film, Medeiros et al. observed the unintentional doping of SiC,Ny thin Ims by oxygen contamination coming from the vacuum environment of the magnetron co-sputtering ystem [35]. In this work, RBS results showed that all samples contained significant amounts of oxygen 1p to 16%). Further, X-ray photoelectron spectroscopy (XPS) results showed that most of this oxygen is ycated in the film surface [35]. These results corroborate with the RBS analysis presented in Figure la 1 addition, Pomaska et al. presented studies on the unintentional doping by oxygen contamination yhere they demonstrated that the oxygen incorporation was influenced the microstructural, electronic nd optical properties of the SiC films [39]. It has been shown that oxygen incorporation during film eposition increases the crystallinity of SiC films, consistent with findings observed in this work.
Figure 1. Experimental and simulated Rutherford backscattering spectrometry (RBS) spectra of the SiC films deposited on (a) Si substrate at 200 W; (b) Si substrate at 400 W; (c) AIN/Si substrate at 200 W and; (d) AIN/Si substrate at 400 W. 1pproximately 400 nm) consisted of SiC with 10% excess carbon. The next layer with a thickness f 250 nm had about 50% carbon excess and a substantial drop in the oxygen content was observed he subsequent layer of 170 nm was fully stoichiometric, followed by the last layer of 145 nm adjacent ) the Si surface, where 10% carbon excess was found. When investigating the incorporated oxygen 1 the first layers of the SiC film, Medeiros et al. observed the unintentional doping of SiC,Ny thin Ims by oxygen contamination coming from the vacuum environment of the magnetron co-sputtering ystem [35]. In this work, RBS results showed that all samples contained significant amounts of oxygen 1p to 16%). Further, X-ray photoelectron spectroscopy (XPS) results showed that most of this oxygen is ycated in the film surface [35]. These results corroborate with the RBS analysis presented in Figure la 1 addition, Pomaska et al. presented studies on the unintentional doping by oxygen contamination yhere they demonstrated that the oxygen incorporation was influenced the microstructural, electronic nd optical properties of the SiC films [39]. It has been shown that oxygen incorporation during film eposition increases the crystallinity of SiC films, consistent with findings observed in this work.
1 Layer 1 refers to the layer at the top of the film. Table 1. Results of the RBS analysis.
1 Layer 1 refers to the layer at the top of the film. Table 1. Results of the RBS analysis.
Table 2. Deposition rate of the SiC films. 3.2. Structural Analysis
Table 2. Deposition rate of the SiC films. 3.2. Structural Analysis
Figure 2. Grazing incidence X-ray diffraction (GIXRD) patterns of the SiC thin films at a grazing angle of 1.0°. Figures 2—4 show the patterns of grazing incidence angles of 1.0°, 1.5°, and 2.0°, respectively. The Bragg reflections suggest the existence of « and B SiC nanocrystalline structures. Although the patterns exhibit the SiC phase, it is not possible to determine which of the SiC phases are present because some diffraction peaks of « and B SiC might overlap [45]. The carbon phase at ~25° was also visible and confirmed the RBS results indicating an excess of C (Table 1). Lastly, two broad peaks at ~47° and 55° were assigned as unidentified. While some studies have attributed these peaks to the SiC polymorph phase [46,47], others often define them as being C or Si phases [48-50]. When comparing the results from the GIXRD with an incidence angle of 2° (Figure 4) with the smaller angle results, the variation of the crystalline phases with the depth of the film was clearly noted.
Figure 2. Grazing incidence X-ray diffraction (GIXRD) patterns of the SiC thin films at a grazing angle of 1.0°. Figures 2—4 show the patterns of grazing incidence angles of 1.0°, 1.5°, and 2.0°, respectively. The Bragg reflections suggest the existence of « and B SiC nanocrystalline structures. Although the patterns exhibit the SiC phase, it is not possible to determine which of the SiC phases are present because some diffraction peaks of « and B SiC might overlap [45]. The carbon phase at ~25° was also visible and confirmed the RBS results indicating an excess of C (Table 1). Lastly, two broad peaks at ~47° and 55° were assigned as unidentified. While some studies have attributed these peaks to the SiC polymorph phase [46,47], others often define them as being C or Si phases [48-50]. When comparing the results from the GIXRD with an incidence angle of 2° (Figure 4) with the smaller angle results, the variation of the crystalline phases with the depth of the film was clearly noted.
Figure 3. GIXRD patterns of the SiC thin films at a grazing angle of 1.5°.
Figure 3. GIXRD patterns of the SiC thin films at a grazing angle of 1.5°.
Figure 4. GIXRD patterns of the SiC thin films at a grazing angle of 2°.
Figure 4. GIXRD patterns of the SiC thin films at a grazing angle of 2°.
Figure 5. Raman spectra of SiC thin films on both substrates: (a) as-deposited at 200 W and (b) as-deposited at 400 W. Figure 5 shows the results of Raman spectroscopy used to identify the bonds present in the films. The Raman spectra for the SiC films deposited at 200 W in both substrates (with and without the AIN layer) are presented in Figure 5a, showing a very visible and well-defined Si peak at 519.41 cm7!. Since the difference in thickness between both films was small, the substrate had an accentuated influence. In addition to Si, the SiC film deposited on the AIN layer showed (i) a peak relative to AIN at ~652.20 cm7!; (ii) peaks for SiC and Si in the regions between 741-894 cm7! and 906-1109 cm~!, respectively; (iii) and a broad carbon band at 1370-1625 cm}. Except for the AIN peak, the SiC/Si spectrum exhibited signals at similar regions to that of the SiC/ AIN/Si spectrum. However, the regions relative to SiC and Si were more visible, and the C band region had a more explicit separation in two peaks (D and G bands), but with a low definition of the disorder band. The D band was attributed to the disorder or polycrystalline carbon and the G band to the graphite-like carbon [19,50].
Figure 5. Raman spectra of SiC thin films on both substrates: (a) as-deposited at 200 W and (b) as-deposited at 400 W. Figure 5 shows the results of Raman spectroscopy used to identify the bonds present in the films. The Raman spectra for the SiC films deposited at 200 W in both substrates (with and without the AIN layer) are presented in Figure 5a, showing a very visible and well-defined Si peak at 519.41 cm7!. Since the difference in thickness between both films was small, the substrate had an accentuated influence. In addition to Si, the SiC film deposited on the AIN layer showed (i) a peak relative to AIN at ~652.20 cm7!; (ii) peaks for SiC and Si in the regions between 741-894 cm7! and 906-1109 cm~!, respectively; (iii) and a broad carbon band at 1370-1625 cm}. Except for the AIN peak, the SiC/Si spectrum exhibited signals at similar regions to that of the SiC/ AIN/Si spectrum. However, the regions relative to SiC and Si were more visible, and the C band region had a more explicit separation in two peaks (D and G bands), but with a low definition of the disorder band. The D band was attributed to the disorder or polycrystalline carbon and the G band to the graphite-like carbon [19,50].
Related topics:
Materials ScienceEpitaxial GrowthMicroelectrode arrayElectrochemical etchingCritical LoadNeural InterfaceBulge Test
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