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TABLE 3. Count of mathematical operations for QR and LU factorization.

Table 3 Count of mathematical operations for QR and LU factorization.

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FIGURE 1. A uniform linear array (ULA) and a single source in the far-field region of the ULA.
FIGURE 1. A uniform linear array (ULA) and a single source in the far-field region of the ULA.
‘ABLE 1. Matrix operations for computing elements of L and U matrices. For hardware implementation of the proposed methods, it is required to compute only the first two rows of U matrix and the first two columns of L since the case of two incident sources (K = 2) is considered. Table | lists the operations for this partial LU factorization.
‘ABLE 1. Matrix operations for computing elements of L and U matrices. For hardware implementation of the proposed methods, it is required to compute only the first two rows of U matrix and the first two columns of L since the case of two incident sources (K = 2) is considered. Table | lists the operations for this partial LU factorization.
To achieve high throughput, a pipelined architecture is used for the FPGA implementation of the proposed DOA estima- tion algorithms, as shown in Fig. 3. The different stages of the pipeline represent the major operations of the algorithm. Data flows from one stage of the pipeline to the next one permitting high throughput implementation for the chosen algorithm. Stage 1: The covariance matrix Rx is estimated based on the data received from the four-antenna array of the ULA. The estimated covariance matrix from a number of snapshots can be calculated as:
To achieve high throughput, a pipelined architecture is used for the FPGA implementation of the proposed DOA estima- tion algorithms, as shown in Fig. 3. The different stages of the pipeline represent the major operations of the algorithm. Data flows from one stage of the pipeline to the next one permitting high throughput implementation for the chosen algorithm. Stage 1: The covariance matrix Rx is estimated based on the data received from the four-antenna array of the ULA. The estimated covariance matrix from a number of snapshots can be calculated as:
The hardware implementation model is as shown in Fig. 2. Signals received from the ULA are down-converted, digi- tized, and stored in a FIFO (first-in first-out queue). These steps are executed on the host (PC) while the DOA estimation algorithm is executed on the FPGA target. Signal data is trans- ferred to the FPGA through the FIFO using direct memory access for speedy transfer.
The hardware implementation model is as shown in Fig. 2. Signals received from the ULA are down-converted, digi- tized, and stored in a FIFO (first-in first-out queue). These steps are executed on the host (PC) while the DOA estimation algorithm is executed on the FPGA target. Signal data is trans- ferred to the FPGA through the FIFO using direct memory access for speedy transfer.
-IGURE 5. Generation of Ls matrix and its partitioning in LabVIEW FPGA. For further processing (in Stage 3), matrix L is partitioned into two submatrices as given by (10), and matrix U is also partitioned into two submatrices as given by (19). The imple- mentation of these steps using LabVIEW FPGA module is shown in Fig. 5 and Fig. 6 below. It is worth pointing out here, that for Stage 3, either Z matrix or U matrix is used but not both at the same time.
-IGURE 5. Generation of Ls matrix and its partitioning in LabVIEW FPGA. For further processing (in Stage 3), matrix L is partitioned into two submatrices as given by (10), and matrix U is also partitioned into two submatrices as given by (19). The imple- mentation of these steps using LabVIEW FPGA module is shown in Fig. 5 and Fig. 6 below. It is worth pointing out here, that for Stage 3, either Z matrix or U matrix is used but not both at the same time.
FIGURE 6. Generation of Us matrix and its partitioning in LabVIEW FPGA
FIGURE 6. Generation of Us matrix and its partitioning in LabVIEW FPGA
FIGURE 7. Generation of Qs matrix and its partitioning in LabVIEW FPGA.
FIGURE 7. Generation of Qs matrix and its partitioning in LabVIEW FPGA.
FIGURE 8. Generation of vector norm operation in LabVIEW FPGA.
FIGURE 8. Generation of vector norm operation in LabVIEW FPGA.
FIGURE 9. Implementation of matrix inverse operation for a 2x2 matrix in LabVIEW FPGA. This stage may present a bottleneck for larger number of antennas (M>4) since matrix inverse and matrix multiplica- tion operations for larger sized matrices will be computation- ally intensive and will consume a significantly large number of FPGA resources and clock cycles.
FIGURE 9. Implementation of matrix inverse operation for a 2x2 matrix in LabVIEW FPGA. This stage may present a bottleneck for larger number of antennas (M>4) since matrix inverse and matrix multiplica- tion operations for larger sized matrices will be computation- ally intensive and will consume a significantly large number of FPGA resources and clock cycles.
FIGURE 11. Implementation of eigen value decomposition in LabVIEW FPGA. FIGURE 10. Computation of square root of a complex number in LabVIEW FPGA.
FIGURE 11. Implementation of eigen value decomposition in LabVIEW FPGA. FIGURE 10. Computation of square root of a complex number in LabVIEW FPGA.
TABLE 2. FPGA Resources Available in Xilinx Virtex-5 SXT FPGA.
TABLE 2. FPGA Resources Available in Xilinx Virtex-5 SXT FPGA.
Fig.13 (a) shows the percentage device utilization for each of QR-Q, QR-R, LU-U, and LU-L decomposition methods
Fig.13 (a) shows the percentage device utilization for each of QR-Q, QR-R, LU-U, and LU-L decomposition methods
TABLE 4. FPGA resources consumed for DOA estimation using QR and LU.
TABLE 4. FPGA resources consumed for DOA estimation using QR and LU.
TABLE 5. Clock cycles consumed for DOA estimation using QR and LU. Fig. 14 (c) below shows the total computation time in terms of clock cycles for DOA estimation employing QR-Q, QR-R, LU-L, and LU-U methods. With the 40 MHz onboard clock, the FPGA is estimated to take 3.925 js for estimating DOA angles using LU-U, which is the fastest time among the four methods.
TABLE 5. Clock cycles consumed for DOA estimation using QR and LU. Fig. 14 (c) below shows the total computation time in terms of clock cycles for DOA estimation employing QR-Q, QR-R, LU-L, and LU-U methods. With the 40 MHz onboard clock, the FPGA is estimated to take 3.925 js for estimating DOA angles using LU-U, which is the fastest time among the four methods.
FIGURE 15. Simulated DOA estimates of the proposed methods (LU-L, LU-U) and (QR-Q, QR-R) method for single source lying at 75° from the array reference. The case of two uncorrelated sources is also considered with direction of arrival angles at 65° and 85° from the array reference. SNR range is set from —5 to 30 dB, and the number of snapshots is 500. Monte-Carlo trials of 300 are used. The combined RMSE values for the two sources is shown in Fig. 16 versus SNR for the proposed methods LU-L and LU-U, and QR-R and QR-Q methods. It can be seen from Fig. 16 that the proposed method has very good estimation accuracy which is indicated through lower RMSE especially at low SNR. The QR-R method has slightly better performance at low SNR but similar performance at higher SNR such as 10 dB. However, QR-R Method has higher complexity and computational time.
FIGURE 15. Simulated DOA estimates of the proposed methods (LU-L, LU-U) and (QR-Q, QR-R) method for single source lying at 75° from the array reference. The case of two uncorrelated sources is also considered with direction of arrival angles at 65° and 85° from the array reference. SNR range is set from —5 to 30 dB, and the number of snapshots is 500. Monte-Carlo trials of 300 are used. The combined RMSE values for the two sources is shown in Fig. 16 versus SNR for the proposed methods LU-L and LU-U, and QR-R and QR-Q methods. It can be seen from Fig. 16 that the proposed method has very good estimation accuracy which is indicated through lower RMSE especially at low SNR. The QR-R method has slightly better performance at low SNR but similar performance at higher SNR such as 10 dB. However, QR-R Method has higher complexity and computational time.
FIGURE 17. LabVIEW FPGA Simulation results for DOA estimates of the proposed methods (LU-L, LU-U) and (QR-Q, QR-R) method for two sources lying at 80 o and 1200 from the array reference.
FIGURE 17. LabVIEW FPGA Simulation results for DOA estimates of the proposed methods (LU-L, LU-U) and (QR-Q, QR-R) method for two sources lying at 80 o and 1200 from the array reference.
FIGURE 18. Performance Comparison of DOA estimation of the proposed methods (LU-L, LU-U) and (QR-Q, QR-R) method for both one and two sources.
FIGURE 18. Performance Comparison of DOA estimation of the proposed methods (LU-L, LU-U) and (QR-Q, QR-R) method for both one and two sources.
FIGURE 19. Experimental setup showing two transmitters (in the foreground) and a 4-element antenna array and PXI system (in the background).
FIGURE 19. Experimental setup showing two transmitters (in the foreground) and a 4-element antenna array and PXI system (in the background).
FIGURE 21. NI PXI transmitter modules in the NI PXI platform chassis. coding, and modulation are used to first generate a signal in the digital domain. This digital signal is then converted to an intermediate frequency (IF) analog signal using an arbitrary waveform generator (AWG) module (NI PXI-5421). Next, the analog signal is converted to a radio frequency (RF) signal using an up-converter module (NI PXIe-5652). Finally, the signal is amplified before transmission using RF amplifier module (NI PXI-5691). All these modules are housed in the PXI chassis as shown in Fig. 21. The transmitter unit acts as a source lying in a far field region of the receiver.
FIGURE 21. NI PXI transmitter modules in the NI PXI platform chassis. coding, and modulation are used to first generate a signal in the digital domain. This digital signal is then converted to an intermediate frequency (IF) analog signal using an arbitrary waveform generator (AWG) module (NI PXI-5421). Next, the analog signal is converted to a radio frequency (RF) signal using an up-converter module (NI PXIe-5652). Finally, the signal is amplified before transmission using RF amplifier module (NI PXI-5691). All these modules are housed in the PXI chassis as shown in Fig. 21. The transmitter unit acts as a source lying in a far field region of the receiver.
FIGURE 22. NI PXI receiver modules in the NI PXI platform chassis.
FIGURE 22. NI PXI receiver modules in the NI PXI platform chassis.
Set up the transmitter and receiver units as mentioned in Section VI-A above. Send a | GHz sine wave signal from the transmitter unit and check signal reception at the receiver unit. This is done to check signals are received at the receiver with acceptable signal strength. Fig. 23 shows signal reception at the four receivers in the NI PXI receiver unit. FIGURE 23. The received signal strength from source 1 (1 GHz sinewave) at the four element ULA at the receiver (seen in NI-RFSA Soft Front Panel on each of the four RF Downconverters (RF DC1 - DC4)). Step 3: Run the DOA FPGA LabVIEW code and config- ire the front panel for real-time data acquisition.
Set up the transmitter and receiver units as mentioned in Section VI-A above. Send a | GHz sine wave signal from the transmitter unit and check signal reception at the receiver unit. This is done to check signals are received at the receiver with acceptable signal strength. Fig. 23 shows signal reception at the four receivers in the NI PXI receiver unit. FIGURE 23. The received signal strength from source 1 (1 GHz sinewave) at the four element ULA at the receiver (seen in NI-RFSA Soft Front Panel on each of the four RF Downconverters (RF DC1 - DC4)). Step 3: Run the DOA FPGA LabVIEW code and config- ire the front panel for real-time data acquisition.
FIGURE 25. Co-phase synchronization of Channel 1 with Channel 0; before (left) and after synchronization (right). The direction of arrival information of the RF source signal impinging on the receiver antennas of the ULA is extracted from the phase-shifted copies of the source signal received at the antennas. The phase shift is due to the time delay of the signal arriving at the other antennas of the ULA with respect to one antenna treated as the reference antenna. Thus, in order to avoid estimation errors, it is extremely important to co-phase the receiver antennas with respect to the reference antenna.
FIGURE 25. Co-phase synchronization of Channel 1 with Channel 0; before (left) and after synchronization (right). The direction of arrival information of the RF source signal impinging on the receiver antennas of the ULA is extracted from the phase-shifted copies of the source signal received at the antennas. The phase shift is due to the time delay of the signal arriving at the other antennas of the ULA with respect to one antenna treated as the reference antenna. Thus, in order to avoid estimation errors, it is extremely important to co-phase the receiver antennas with respect to the reference antenna.
and an SNR of 10 dBm. On the receiver side, RF down- converters for each channel are selected (under NI-RFSA Devices) and IQ carrier frequency and sampling rate are set using the front panel user interface shown in Fig. 24 (left). The figure (right) also shows a snapshot of I and Q signals acquired in real-time on each of the four receive channels.
and an SNR of 10 dBm. On the receiver side, RF down- converters for each channel are selected (under NI-RFSA Devices) and IQ carrier frequency and sampling rate are set using the front panel user interface shown in Fig. 24 (left). The figure (right) also shows a snapshot of I and Q signals acquired in real-time on each of the four receive channels.
FIGURE 26. Real-time FPGA DOA estimates: for a single source located at 80° using LU-L and LU-U methods (top left), for two sources located at 75° and 110° using LU-L and LU-U methods (top right) and using QR-Q and QR-R methods (bottom right). shows the measured mean initial phase difference between the signals received from Channel 0 antenna (reference) and Channel | antenna. This phase-offset value is introduced in the received signals to compensate for this phase dif- ference and make Channel | in co-phase with Channel 0. Fig. 25 shows the phase difference between the two chan- nels before and after introducing the phase offset. The other channels (2 and 3) are co-phased with Channel 0 in the same manner.
FIGURE 26. Real-time FPGA DOA estimates: for a single source located at 80° using LU-L and LU-U methods (top left), for two sources located at 75° and 110° using LU-L and LU-U methods (top right) and using QR-Q and QR-R methods (bottom right). shows the measured mean initial phase difference between the signals received from Channel 0 antenna (reference) and Channel | antenna. This phase-offset value is introduced in the received signals to compensate for this phase dif- ference and make Channel | in co-phase with Channel 0. Fig. 25 shows the phase difference between the two chan- nels before and after introducing the phase offset. The other channels (2 and 3) are co-phased with Channel 0 in the same manner.
ABDEL-HAMID SOLIMAN received the B.Sc. degree in electronic and telecommunications from Arab Academy for Science, Technology and Maritime Transport, the M.Sc. degree in smart data acquisition systems from Alexandria Univer- sity, and the Ph.D. degree in image/video pro- cessing from Staffordshire University. He has over 27 years’ experience of working in Higher Edu- cation Institutes. He is currently an Associate Pro- fessor in telecommunication and signal processing with the Department of Engineering, Staffordshire University. He has a multi-disciplinary academic/research experience in digital signal processing, telecommunications, data acquisition systems, wireless sensor networks, and image/video processing, and is focusing in his research on harnessing these technologies to contribute in the smart cities applications. In addition to his research and teaching/learning activities, he is involved in several enterprise projects and consultancy activities for national and international companies. He is also leading and involved in several European funded projects in education, industry automation, and health care applications.
ABDEL-HAMID SOLIMAN received the B.Sc. degree in electronic and telecommunications from Arab Academy for Science, Technology and Maritime Transport, the M.Sc. degree in smart data acquisition systems from Alexandria Univer- sity, and the Ph.D. degree in image/video pro- cessing from Staffordshire University. He has over 27 years’ experience of working in Higher Edu- cation Institutes. He is currently an Associate Pro- fessor in telecommunication and signal processing with the Department of Engineering, Staffordshire University. He has a multi-disciplinary academic/research experience in digital signal processing, telecommunications, data acquisition systems, wireless sensor networks, and image/video processing, and is focusing in his research on harnessing these technologies to contribute in the smart cities applications. In addition to his research and teaching/learning activities, he is involved in several enterprise projects and consultancy activities for national and international companies. He is also leading and involved in several European funded projects in education, industry automation, and health care applications.
Related topics:
Computer ScienceComputer HardwareField Programmable Gate ArrayMatrix DecompositionQR DecompositionLU decomposition
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