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Table 2. Port structure of xilinx_multiplier module instantiation of this module inside InvSqrt, and this module will perform the final subtraction of NR iteration as shown by Figure 6. Again the module is generated using Xilinx CORE generator wizard, and its block diagram is given in Figure 9. Most port pins carry the same meaning as the one listed in Table 2; however, the RESULT port now gives answer of subtracting B operand from A operand. 3. Results

Table 2 Port structure of xilinx_multiplier module instantiation of this module inside InvSqrt, and this module will perform the final subtraction of NR iteration as shown by Figure 6. Again the module is generated using Xilinx CORE generator wizard, and its block diagram is given in Figure 9. Most port pins carry the same meaning as the one listed in Table 2; however, the RESULT port now gives answer of subtracting B operand from A operand. 3. Results

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Figure 1. Flowchart representation of Fast Inverse Square Root algorithm
Figure 1. Flowchart representation of Fast Inverse Square Root algorithm
The architecture of xhalf calculator unit depends on two registers — one for latching the value on x input wire, and other to latcl the xhalf wire. The xhalf will be calculated using a floating point multiplier that stores its result in the xhalf_reg register. The multiplier also takes the scalar value 0.5 as input for multiplication operation. This scheme is shown in Figure 3 . The bottor branch of Figure 2 corresponds to generation of initial guess, yO, as seed for Newton-Raphson iteration. This branch will firs perform a shift right by one operation and then subtract the result from 0x5f3759df. A shift register is not used for this purpos¢
The architecture of xhalf calculator unit depends on two registers — one for latching the value on x input wire, and other to latcl the xhalf wire. The xhalf will be calculated using a floating point multiplier that stores its result in the xhalf_reg register. The multiplier also takes the scalar value 0.5 as input for multiplication operation. This scheme is shown in Figure 3 . The bottor branch of Figure 2 corresponds to generation of initial guess, yO, as seed for Newton-Raphson iteration. This branch will firs perform a shift right by one operation and then subtract the result from 0x5f3759df. A shift register is not used for this purpos¢
Figure 5. Static shift right and input to subtractor Figure 4. Hardware design of shift and subtract operation in the design because it will waste a clock cycle just for performing a single shift. Instead, a hard-wired approach where a bus originating from x register, and suitably concatenated with zero-padding is fed to the subtractor. This particular design choice will ensure that yO is available almost instantaneously whenever a change in x occurs. The design methodology is captured in the diagram of Figure 4. An expanded view of x_reg >>1 block to demonstrate how hard-wired shift right is carried out is given ir Figure 5. The last design step is to map the Newton-Raphson process in hardware. The equation for this process is:
Figure 5. Static shift right and input to subtractor Figure 4. Hardware design of shift and subtract operation in the design because it will waste a clock cycle just for performing a single shift. Instead, a hard-wired approach where a bus originating from x register, and suitably concatenated with zero-padding is fed to the subtractor. This particular design choice will ensure that yO is available almost instantaneously whenever a change in x occurs. The design methodology is captured in the diagram of Figure 4. An expanded view of x_reg >>1 block to demonstrate how hard-wired shift right is carried out is given ir Figure 5. The last design step is to map the Newton-Raphson process in hardware. The equation for this process is:
Figure 3. Calculating and storing xhalf
Figure 3. Calculating and storing xhalf
Figure 6. Newton raphson equation hardware mapping Unfortunately, it is the slowest and most cycle consuming operation of the entire algorithm. Although xhalf and yO are made available almost instantaneously from previous blocks but they have to be fed into cascaded floating point multipliers which lead to a final floating point subtractor. Each of these multiplication/subtraction operation taxes clock cycles and equation has to be implemented in its original form without much optimization possible. An illustration of this mapping is given in Figure 6.
Figure 6. Newton raphson equation hardware mapping Unfortunately, it is the slowest and most cycle consuming operation of the entire algorithm. Although xhalf and yO are made available almost instantaneously from previous blocks but they have to be fed into cascaded floating point multipliers which lead to a final floating point subtractor. Each of these multiplication/subtraction operation taxes clock cycles and equation has to be implemented in its original form without much optimization possible. An illustration of this mapping is given in Figure 6.
Figure 7. Block diagram of top-module InvSqrt
Figure 7. Block diagram of top-module InvSqrt
Figure 8. Block diagram of generated floating point multiplier Yext step is to include a floating point unit (FPU) in the hierarchy which will carry out the required multiplications a1 ubtraction. There are two implementation choices — first, to write a floating-point unit module from scratch and instantiate vithin the top-level module. However, this effort is not aligned with the paper goals and time-consuming in terms of descripti nd verification. The second choice is to incorporate an already created floating point unit IP core and use it in this settin ‘hese cores are thoroughly verified by their developers and only minor port adjustment/customization is required to meet o equirements. Xilinx CORE Generator System [9] is selected for creating and customizing the floating point modules. The reas eing that it is already included with Xilinx ISE and provides architecture-specific core generation which helps to maximi erformance. While customizing the floating-point multiplier core, full usage of all four MULTI18X18S blocks (embedded <C3SS500E FPGA) is made to enhance the performance of resulting module. The block diagram of generated multiplier core iven in Figure 11 . There are five instantiations of this module inside InvSqrt module — four are consumed in implementi1 Yewton-Raphson equation multiplications and the fifth is used to multiply the value of x by 0.5. Note, that an alternati ramework for highest performance would have been to convert all the floating point values to their fixed point Int32 representatio nd then implement all these arithmetic operations using this form. This approach would have required a float-to-fixed convert efore arithmetic steps and a fixed-to-float converter to return result in IEEE754 format. In this architecture, the algorithm cou e represented in its entirety using behavioral description and then synthesizer can help in performance and area optimizatior 3ut, this approach is not adopted in this paper because of the crucial factor of range. The fixed point representation andicapped by smaller range of values that can be stored and this limits the usefulness of the module. A description of the ports and their properties is summarized in Table 2Port structure of xilinx_multiplier module.
Figure 8. Block diagram of generated floating point multiplier Yext step is to include a floating point unit (FPU) in the hierarchy which will carry out the required multiplications a1 ubtraction. There are two implementation choices — first, to write a floating-point unit module from scratch and instantiate vithin the top-level module. However, this effort is not aligned with the paper goals and time-consuming in terms of descripti nd verification. The second choice is to incorporate an already created floating point unit IP core and use it in this settin ‘hese cores are thoroughly verified by their developers and only minor port adjustment/customization is required to meet o equirements. Xilinx CORE Generator System [9] is selected for creating and customizing the floating point modules. The reas eing that it is already included with Xilinx ISE and provides architecture-specific core generation which helps to maximi erformance. While customizing the floating-point multiplier core, full usage of all four MULTI18X18S blocks (embedded <C3SS500E FPGA) is made to enhance the performance of resulting module. The block diagram of generated multiplier core iven in Figure 11 . There are five instantiations of this module inside InvSqrt module — four are consumed in implementi1 Yewton-Raphson equation multiplications and the fifth is used to multiply the value of x by 0.5. Note, that an alternati ramework for highest performance would have been to convert all the floating point values to their fixed point Int32 representatio nd then implement all these arithmetic operations using this form. This approach would have required a float-to-fixed convert efore arithmetic steps and a fixed-to-float converter to return result in IEEE754 format. In this architecture, the algorithm cou e represented in its entirety using behavioral description and then synthesizer can help in performance and area optimizatior 3ut, this approach is not adopted in this paper because of the crucial factor of range. The fixed point representation andicapped by smaller range of values that can be stored and this limits the usefulness of the module. A description of the ports and their properties is summarized in Table 2Port structure of xilinx_multiplier module.
The Verilog description of module was successfully synthesized using XST tool and mapped on Digilent’s Spartan 3E (XC3S500E) Starter board. The utilization summary is given in Table 3.
The Verilog description of module was successfully synthesized using XST tool and mapped on Digilent’s Spartan 3E (XC3S500E) Starter board. The utilization summary is given in Table 3.
Figure 10. Signal waveform when input at x is 16 (fixed point) The evolution of xhalf and yO signals is depicted in Figure 11 overleaf. Note that yO signal is made available almost instantly afte input port x changes to a new value.
Figure 10. Signal waveform when input at x is 16 (fixed point) The evolution of xhalf and yO signals is depicted in Figure 11 overleaf. Note that yO signal is made available almost instantly afte input port x changes to a new value.
Figure 11. Clock by clock waveform testing of xhalf and yO signals The Inverse Square Root calculator algorithm was successfully designed, described in Verilog, synthesized and finally mapped on the FPGA board. The final result is made available after only 12 clock cycles and offers good accuracy for most practical uses. This performance measure is far superior to the one obtained by pure software-based calculation not utilizing SSE support. This module can be readily included as part of bigger Arithmetic Units for supporting fast inverse square roots. The designed module can be used in FPGA based graphic processing units [10] [11], which require intensive reciprocal square root calculations for lighting and shading of 3D operations especially video games. FPGA based graphic processors are still in infancy and this module can greatly improve their throughput for rendering graphics by offloading other modules. Vertex shader implementation on FPGA as discussed in [12] can also utilize the module. This module can also find use in microprocessors not making use of fast rsqrtss of SSE instruction set, especially some RISC implementations on FPGA architectures.
Figure 11. Clock by clock waveform testing of xhalf and yO signals The Inverse Square Root calculator algorithm was successfully designed, described in Verilog, synthesized and finally mapped on the FPGA board. The final result is made available after only 12 clock cycles and offers good accuracy for most practical uses. This performance measure is far superior to the one obtained by pure software-based calculation not utilizing SSE support. This module can be readily included as part of bigger Arithmetic Units for supporting fast inverse square roots. The designed module can be used in FPGA based graphic processing units [10] [11], which require intensive reciprocal square root calculations for lighting and shading of 3D operations especially video games. FPGA based graphic processors are still in infancy and this module can greatly improve their throughput for rendering graphics by offloading other modules. Vertex shader implementation on FPGA as discussed in [12] can also utilize the module. This module can also find use in microprocessors not making use of fast rsqrtss of SSE instruction set, especially some RISC implementations on FPGA architectures.
Related topics:
Computer ScienceComputer HardwareField Programmable Gate ArrayMultiplicative Inverse
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