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Lars Risbo (M’05) received the M.Sc.E.E. and Ph.D. degrees from the Technical University of Denmark in 1991 and 1994, respectively. Both his thesis works were on stability analysis and loop synthesis of high- order sigma-delta modulators. From 1998 to 2000, he was with ITU ETA Founda- tion ASIC Design Center, Istanbul, Turkey, as a De- sign Engineer. In 2000, he joined Alcatel-Teletas Mi- croelectronic Design Center as an RFIC Design Engi- neer. During the summer of 2004, he worked at Conexant in the System on Chip Group. From 2006 to 2010, he was employed by Texas Instruments, Dallas, as a system design and integration engineer at Wireless Terminal Business Unit. In 2010, he joined the Electrical and Electronics Engineering Department at Okan University, Istanbul, Turkey, where he is currently an Assistant Professor. His current research interests include analog and mixed-signal circuits and systems, wireless communication systems, and high-frequency circuit design.

Figure 12 Lars Risbo (M’05) received the M.Sc.E.E. and Ph.D. degrees from the Technical University of Denmark in 1991 and 1994, respectively. Both his thesis works were on stability analysis and loop synthesis of high- order sigma-delta modulators. From 1998 to 2000, he was with ITU ETA Founda- tion ASIC Design Center, Istanbul, Turkey, as a De- sign Engineer. In 2000, he joined Alcatel-Teletas Mi- croelectronic Design Center as an RFIC Design Engi- neer. During the summer of 2004, he worked at Conexant in the System on Chip Group. From 2006 to 2010, he was employed by Texas Instruments, Dallas, as a system design and integration engineer at Wireless Terminal Business Unit. In 2010, he joined the Electrical and Electronics Engineering Department at Okan University, Istanbul, Turkey, where he is currently an Assistant Professor. His current research interests include analog and mixed-signal circuits and systems, wireless communication systems, and high-frequency circuit design.

Related Figures (12)

Fig. 1. ISI error waveforms for a binary DAC with a memory depth of one symbol. (a) I. ideal DAC waveform, II. actual waveform, and III. ISI error wave- form with error integrals used for a discrete-time ISI signal representation in (1). (b) I. Actual waveform with error only on the falling edge, II. linearized wave- form by addition of a correction to the rising edge, III. linearized waveform by adding a correction to the 0 — 0 transition.
Fig. 1. ISI error waveforms for a binary DAC with a memory depth of one symbol. (a) I. ideal DAC waveform, II. actual waveform, and III. ISI error wave- form with error integrals used for a discrete-time ISI signal representation in (1). (b) I. Actual waveform with error only on the falling edge, II. linearized wave- form by addition of a correction to the rising edge, III. linearized waveform by adding a correction to the 0 — 0 transition.
Fig. 2. Transition rates and tone frequencies versus segment density. (a) The- oretical bounds. (b) Simulated transition densities for various DEMs. (c) Fre- quency modulation of idle tones.
Fig. 2. Transition rates and tone frequencies versus segment density. (a) The- oretical bounds. (b) Simulated transition densities for various DEMs. (c) Fre- quency modulation of idle tones.
Fig. 3. Simulated power spectral densities (PSD) for the DWA with the seg- ment signal in black and ’-sequence (nonlinear ISI) in red: (a) —60 dBFS input and (b) —6 dBFS input.
Fig. 3. Simulated power spectral densities (PSD) for the DWA with the seg- ment signal in black and ’-sequence (nonlinear ISI) in red: (a) —60 dBFS input and (b) —6 dBFS input.
Fig. 4. Impact of dither and DC on the FM tones of DWA and second-order DWA with —60 dBFS input and a combination of 1% static mismatch and 50 ps nonlinear ISI on all segments. (a) No dither and no DC added. (b) Significant dither (4LSB) is needed to start impacting the tones. (c) Tone spectrum shifted 17.3 kHz by adding 0.56% FS DC offset to the noise shaper input.
Fig. 4. Impact of dither and DC on the FM tones of DWA and second-order DWA with —60 dBFS input and a combination of 1% static mismatch and 50 ps nonlinear ISI on all segments. (a) No dither and no DC added. (b) Significant dither (4LSB) is needed to start impacting the tones. (c) Tone spectrum shifted 17.3 kHz by adding 0.56% FS DC offset to the noise shaper input.
Fig. 5. Advanced mismatch shaping loops. (a) Generalized view of a DEM as vectorized sigma-delta modulator. (b) Proposed ISI shaper having a separate ISI- shaping loop filter.
Fig. 5. Advanced mismatch shaping loops. (a) Generalized view of a DEM as vectorized sigma-delta modulator. (b) Proposed ISI shaper having a separate ISI- shaping loop filter.
Fig. 6. Simulated Power Spectral Densities (PSD) for the MMS algorithm with the segment signal in black and ’-sequence (nonlinear ISI) in red: (a) —60 dBFS input and (b) —6 dBFS input.
Fig. 6. Simulated Power Spectral Densities (PSD) for the MMS algorithm with the segment signal in black and ’-sequence (nonlinear ISI) in red: (a) —60 dBFS input and (b) —6 dBFS input.
Fig. 7. Simulated power spectral densities (PSD) for the ISI shaper algorithm (second-order for both loops) with the segment signal in black and ['-sequence (nonlinear ISI) in red: (a) —60 dBFS input and (b) —6 dBFS input.
Fig. 7. Simulated power spectral densities (PSD) for the ISI shaper algorithm (second-order for both loops) with the segment signal in black and ['-sequence (nonlinear ISI) in red: (a) —60 dBFS input and (b) —6 dBFS input.
Fig. 8. Experimental DAC signal chain.
Fig. 8. Experimental DAC signal chain.
Fig. 9. Analog circuit implementation of the DAC in 45 nm CMOS. Two banks of NRZ current steering cells feeding a current-summing I2V op-amp stage.
Fig. 9. Analog circuit implementation of the DAC in 45 nm CMOS. Two banks of NRZ current steering cells feeding a current-summing I2V op-amp stage.
Fig. 10. Measurement output spectrum. (a) Large signal with DWA rotation. (b) Large signal with ISI-shaping. (c) Small signal with DWA rotation. (d) Smal. signal with IS]-shaping.
Fig. 10. Measurement output spectrum. (a) Large signal with DWA rotation. (b) Large signal with ISI-shaping. (c) Small signal with DWA rotation. (d) Smal. signal with IS]-shaping.
PERFORMANCE SUMMARY (1 ch.) OF THE EXPERIMENTAL DAC SYSTEM TABLE I
PERFORMANCE SUMMARY (1 ch.) OF THE EXPERIMENTAL DAC SYSTEM TABLE I
Fig. 11. Amplitude sweep measurements.
Fig. 11. Amplitude sweep measurements.
Related topics:
Harmonic AnalysisNoise ShapingNoise MeasurementDigital to Analog ConverterElectrical and Electronic EngineeringDynamic element matchingData weighted averaging
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