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Figure 2. A cloud computing infrastructure using virtualized system building blocks. allocated to it, these resources are shared at processor and memory architecture level. In this paper, our goal is to quantify the overhead of this level of sharing on VM scalability using four types of interactions mentioned above. Additionally we want to find the cost of virtualization in terms of performance penalty for intra-processor, inter- processor, and across LAN and WAN interactions. We use an Intel dual processor, quad-core processor based system where intra- and inter-processor communication is through a shared bus while LAN is a Gigabit switch. We emulate WAN using DummyNet [13]. We measure CPU, memory, and network I/O performance using micro-benchmarks running across multiple VMs as well as non-virtualized SMP kernel based baseline system. The baseline system employs multiple threads to fully exercise the system and to compare the scalability characteristics with multiple VM cases.

Figure 2 A cloud computing infrastructure using virtualized system building blocks. allocated to it, these resources are shared at processor and memory architecture level. In this paper, our goal is to quantify the overhead of this level of sharing on VM scalability using four types of interactions mentioned above. Additionally we want to find the cost of virtualization in terms of performance penalty for intra-processor, inter- processor, and across LAN and WAN interactions. We use an Intel dual processor, quad-core processor based system where intra- and inter-processor communication is through a shared bus while LAN is a Gigabit switch. We emulate WAN using DummyNet [13]. We measure CPU, memory, and network I/O performance using micro-benchmarks running across multiple VMs as well as non-virtualized SMP kernel based baseline system. The baseline system employs multiple threads to fully exercise the system and to compare the scalability characteristics with multiple VM cases.

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Figure 1. Overview of dual processor, quad-core Intel Xeon E5405 processor architecture and our testbed.
Figure 1. Overview of dual processor, quad-core Intel Xeon E5405 processor architecture and our testbed.
E Il. THROUGHPUT IN MBPS OF MEMORY-TO-MEMORY COPY OF 16 MB FLOATING POINT DATA AND END-TO-END NETWORK DATA TRANSFER THROUGH LOOPBACK ON THE SUT. In this section, we use three micro-benchmarks to characterize the performance of Intel multi-core processors based system. We use a baseline case with SMP system running a non-virtualized image of Linux and compare its CPU, memory, and network I/O scalability with Xen based virtualized kernel image. While the baseline cases exercise non-virtualized SMP kernel using multiple threads, virtualized cases exercise the system through independent and concurrently executing processes in multiple VMs.
E Il. THROUGHPUT IN MBPS OF MEMORY-TO-MEMORY COPY OF 16 MB FLOATING POINT DATA AND END-TO-END NETWORK DATA TRANSFER THROUGH LOOPBACK ON THE SUT. In this section, we use three micro-benchmarks to characterize the performance of Intel multi-core processors based system. We use a baseline case with SMP system running a non-virtualized image of Linux and compare its CPU, memory, and network I/O scalability with Xen based virtualized kernel image. While the baseline cases exercise non-virtualized SMP kernel using multiple threads, virtualized cases exercise the system through independent and concurrently executing processes in multiple VMs.
Figure 3. CPU throughput in MOPS across number of threads and guests, for floating point, integer and logical operations for SUT. mutually exclusive, 16 KB array copy mostly access private LI cache. Similarly, 16 MB array size implies that while accesses from the main memory over shared bus play a dominant role in measuring throughput, L1 and L2 caches enhance spatial locality. Keeping this distinction in mind, we observe three memory throughput characteristics of the system under this workload:
Figure 3. CPU throughput in MOPS across number of threads and guests, for floating point, integer and logical operations for SUT. mutually exclusive, 16 KB array copy mostly access private LI cache. Similarly, 16 MB array size implies that while accesses from the main memory over shared bus play a dominant role in measuring throughput, L1 and L2 caches enhance spatial locality. Keeping this distinction in mind, we observe three memory throughput characteristics of the system under this workload:
Figure 4. Memory throughput in Gbps across number of threads and guests VMs for floating point data for different sizes on SUT.
Figure 4. Memory throughput in Gbps across number of threads and guests VMs for floating point data for different sizes on SUT.
Figure 5. (a) Single Host based VM interactions case (b) Multiple Host based interactions case across GigE LAN. (c) Multiple Host based interactions case across WAN connected through OC-3 emulated link.
Figure 5. (a) Single Host based VM interactions case (b) Multiple Host based interactions case across GigE LAN. (c) Multiple Host based interactions case across WAN connected through OC-3 emulated link.
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