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Figure 7: Code snippet: C-Code of Variant-3, Result is stored in a new variable compared to that of the operands

Figure 7 Code snippet: C-Code of Variant-3, Result is stored in a new variable compared to that of the operands

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Algorithm 1: Dilithium Signature scheme
Algorithm 1: Dilithium Signature scheme
Proof: The algorithm in Figure 2, given below, illustrates this claim. The correctness of the algorithm follows immediately from Lemma 2.1 and Lemma 5.2. Lemma 5.2 ([19]). Letr € Zg andh,h’ € {0,1}. IFUHg(h, 7, @) = UHg(h’,r, a), thenh = h’.
Proof: The algorithm in Figure 2, given below, illustrates this claim. The correctness of the algorithm follows immediately from Lemma 2.1 and Lemma 5.2. Lemma 5.2 ([19]). Letr € Zg andh,h’ € {0,1}. IFUHg(h, 7, @) = UHg(h’,r, a), thenh = h’.
Table 1: Fault simulation results for our skip-addition fault attack on the various recommended parameter sets of Dilithium. Results were obtained over 10° runs of the signing procedure. the knowledge of to. In the following we first show that UHg func- tion could be inverted to produce the correct hint. In particular UHg(h,r, @), given q, a, r € Zg and HBg(u + r, a), is invertible on hif ||ulloo < a/2. Lemma 5.1 summarizes this fact. the failure probability of our forgery signing procedure. We ran our forgery algorithm for a total of 278 times while not obtaining a single invalid signature. This along with its increased signing rate leads us to hypothesize if our forgery algorithm can be used as an alternative signing procedure for Dilithium. Concrete estimation of its error-probability and security of the generated signatures is left for future work.
Table 1: Fault simulation results for our skip-addition fault attack on the various recommended parameter sets of Dilithium. Results were obtained over 10° runs of the signing procedure. the knowledge of to. In the following we first show that UHg func- tion could be inverted to produce the correct hint. In particular UHg(h,r, @), given q, a, r € Zg and HBg(u + r, a), is invertible on hif ||ulloo < a/2. Lemma 5.1 summarizes this fact. the failure probability of our forgery signing procedure. We ran our forgery algorithm for a total of 278 times while not obtaining a single invalid signature. This along with its increased signing rate leads us to hypothesize if our forgery algorithm can be used as an alternative signing procedure for Dilithium. Concrete estimation of its error-probability and security of the generated signatures is left for future work.
4Code is available online on https://github.com/jameshoweee/dilithium_forgery
4Code is available online on https://github.com/jameshoweee/dilithium_forgery
For our experiments, we target the reference implementation of Dilithium taken from the pqm4 library, a benchmarking and testing framework for POC schemes on the ARM Cortex-M4 family of mi- crocontrollers [17]. We ported its reference implementation to the STM32F4DISCOVERY board (DUT) housing the STM32F407, ARM Cortex-M4 microcontroller. Our implementation (compiled with -03 -mthumb -mcpu=cortex-m4 -mf loat-abi=hard -mfpu=fpv4-sp-d16) runs at a clock frequency of 24 MHz. We use the ST-LINK/v2.1 add-on board for USART communication with our DUT. We used the OpenOCD framework for flash configuration and on-chip hardware debugging with the aid of the GNU debug- ger for ARM (arm-none-eabi-gdb). We use Electromagnetic Fault injection (EMFI) to inject faults into our device.
For our experiments, we target the reference implementation of Dilithium taken from the pqm4 library, a benchmarking and testing framework for POC schemes on the ARM Cortex-M4 family of mi- crocontrollers [17]. We ported its reference implementation to the STM32F4DISCOVERY board (DUT) housing the STM32F407, ARM Cortex-M4 microcontroller. Our implementation (compiled with -03 -mthumb -mcpu=cortex-m4 -mf loat-abi=hard -mfpu=fpv4-sp-d16) runs at a clock frequency of 24 MHz. We use the ST-LINK/v2.1 add-on board for USART communication with our DUT. We used the OpenOCD framework for flash configuration and on-chip hardware debugging with the aid of the GNU debug- ger for ARM (arm-none-eabi-gdb). We use Electromagnetic Fault injection (EMFI) to inject faults into our device.
Figure 3: (a) Hand-made probe used for our EMFI setup (b) Probe placed over the DUT
Figure 3: (a) Hand-made probe used for our EMFI setup (b) Probe placed over the DUT
The first two variants are based on the order of the operands within the addition operation while the result of addition in both the variants is overwritten into the same variable as one of the operands. But, the third variant is based on storing the result into a new variable different from the operands. While we demonstrate our attack against all the three variants, it is important to note that Variant-2 and 3 were proposed as concrete countermeasures against the skip-addition attack in a number of works [8, 9].
The first two variants are based on the order of the operands within the addition operation while the result of addition in both the variants is overwritten into the same variable as one of the operands. But, the third variant is based on storing the result into a new variable different from the operands. While we demonstrate our attack against all the three variants, it is important to note that Variant-2 and 3 were proposed as concrete countermeasures against the skip-addition attack in a number of works [8, 9].
Figure 8: First order Pattern Recognition (a) Identification of multiple iterations of signing procedure on EM trace (b) Zoomed in view of multiple iterations (c) Identifying repeat- ing patterns in a single iteration and mapping them to the corresponding operations in the reference implementation
Figure 8: First order Pattern Recognition (a) Identification of multiple iterations of signing procedure on EM trace (b) Zoomed in view of multiple iterations (c) Identifying repeat- ing patterns in a single iteration and mapping them to the corresponding operations in the reference implementation
Rg = Zq{X]/[X” + 1] with n > 1024. Refer Alg.6 for a brief al- gorithmic level description of the qIESLA signature scheme. As stated earlier!, our attacks only apply the deterministic variant of qTESLA and since its updated specification is a probabilistic one and hence is inherently protected against our attacks.
Rg = Zq{X]/[X” + 1] with n > 1024. Refer Alg.6 for a brief al- gorithmic level description of the qIESLA signature scheme. As stated earlier!, our attacks only apply the deterministic variant of qTESLA and since its updated specification is a probabilistic one and hence is inherently protected against our attacks.
Figure 9: NTT operation on a polynomial x with degree 8 dependency between elements of the input and the output of the NTT transform. We leverage over this property, which we refer to as the diffusion property of the NTT operation to ensure that the fault injected in the addition operation for one element is propagated uniformly to all the elements in the signature component z. This further ensures that the resulting faulty signatures are rejected by the signing procedure with very high probability.
Figure 9: NTT operation on a polynomial x with degree 8 dependency between elements of the input and the output of the NTT transform. We leverage over this property, which we refer to as the diffusion property of the NTT operation to ensure that the fault injected in the addition operation for one element is propagated uniformly to all the elements in the signature component z. This further ensures that the resulting faulty signatures are rejected by the signing procedure with very high probability.
Algorithm 6: qTESLA Signature scheme obtained through an inverse NTT operation. The NTT operation in itself is a bijective mapping from one polynomial to another in the same operating ring. An input sequence p with n elements (Po, .--,Pn—1) is mapped to its representation p in the NTT domain as where j € [0, n—1] and w being the n'" root of unity in the operating ring Zg.
Algorithm 6: qTESLA Signature scheme obtained through an inverse NTT operation. The NTT operation in itself is a bijective mapping from one polynomial to another in the same operating ring. An input sequence p with n elements (Po, .--,Pn—1) is mapped to its representation p in the NTT domain as where j € [0, n—1] and w being the n'" root of unity in the operating ring Zg.
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