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Fig. 5. Bidirectional communication while satisfying 48kHz sample rate. Note that for both the main controller and the sub-controller,PLL in the FPGA is configured to generate 4.8MHz clock from LRCK. So, in order to maintain 48 kHz rate, the data

Figure 5 Bidirectional communication while satisfying 48kHz sample rate. Note that for both the main controller and the sub-controller,PLL in the FPGA is configured to generate 4.8MHz clock from LRCK. So, in order to maintain 48 kHz rate, the data

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As another application example is can include improvement in the connection ways of speakers or PA (Public Address) systems within a building, a company, or public facilities. In existing systems, a number of connection wires are required to send out audio signals to speakers from the system. Furthermore simultaneous broadcasting with multiple channels at the same time is difficult because analog audio signals are transmitted to each speaker. To solve these problems, we can build the speaker connection as shown in Figure c,. In this case, it is possible to send different messages to different speakers or to transmit some broadcasting messages to only designated speakers because digital audio signals are serially transmitted.
As another application example is can include improvement in the connection ways of speakers or PA (Public Address) systems within a building, a company, or public facilities. In existing systems, a number of connection wires are required to send out audio signals to speakers from the system. Furthermore simultaneous broadcasting with multiple channels at the same time is difficult because analog audio signals are transmitted to each speaker. To solve these problems, we can build the speaker connection as shown in Figure c,. In this case, it is possible to send different messages to different speakers or to transmit some broadcasting messages to only designated speakers because digital audio signals are serially transmitted.
Fig c. A connection example for a PA system within a building
Fig c. A connection example for a PA system within a building
TABLE 1. DEVELOPMENT SPECIFICATIONS
TABLE 1. DEVELOPMENT SPECIFICATIONS
The block diagram of the connection system Figure d. The left side of the figure converts analog audio data to digital audio data with ADCs (Analog-to-Digital Converters) and synthesizes the converted signals into packets to be sent to speakers serially. In the right of the figure, transmitted signals are identified by signal selection parts and converted into analog signals by NACs (Nicital-to-Analoo Converters). Fig e. Visual diagram of data transformation
The block diagram of the connection system Figure d. The left side of the figure converts analog audio data to digital audio data with ADCs (Analog-to-Digital Converters) and synthesizes the converted signals into packets to be sent to speakers serially. In the right of the figure, transmitted signals are identified by signal selection parts and converted into analog signals by NACs (Nicital-to-Analoo Converters). Fig e. Visual diagram of data transformation
As shown in Figure f, the output of 24-bit effective data begins at the second rising edge of the SCLK signal after the state of the LRCK is changed. According to the value of LRCK (either ‘0’ or ‘1’), different channels are activated. That is, if LRCK is ‘0’, then channels 2, 4, and 6 generate /’S-bus signals at the same time, otherwise channels 1, 3, and 5 do the same task. Packets for three channels are generated every 11.34us. Therefore, each channel generates its packet every 22.68us. In this case, data processing and transmission for three channels should be done for time duration 7.09us (=11.34us — 4.25us), during which there is no effective data on SDATA. Relatively low bandwidth is used for long distance transmission lines. We need to compress data to send audio signals with low bandwidth lines.
As shown in Figure f, the output of 24-bit effective data begins at the second rising edge of the SCLK signal after the state of the LRCK is changed. According to the value of LRCK (either ‘0’ or ‘1’), different channels are activated. That is, if LRCK is ‘0’, then channels 2, 4, and 6 generate /’S-bus signals at the same time, otherwise channels 1, 3, and 5 do the same task. Packets for three channels are generated every 11.34us. Therefore, each channel generates its packet every 22.68us. In this case, data processing and transmission for three channels should be done for time duration 7.09us (=11.34us — 4.25us), during which there is no effective data on SDATA. Relatively low bandwidth is used for long distance transmission lines. We need to compress data to send audio signals with low bandwidth lines.
The fast processing hardware technique is required to deal with data from three channels within at least 7.09us. ?’S-bus data for each channel are processed as shown in Figure 7. We can see the processing of sampled data at times t, t+1, and t+2. Data sampling at a high speed is required to get audio signals with high quality. Since there is no big difference between two sequentially sampled data, if we apply an xor operation to the two data and scan the operation result from MSB to LSB, fast processing is possible because only a small amount of data storage is required. In the example of t+1 xor t2 shown in Figure f, g bits are used to process 24-bit data [6]. 5) Packet formats
The fast processing hardware technique is required to deal with data from three channels within at least 7.09us. ?’S-bus data for each channel are processed as shown in Figure 7. We can see the processing of sampled data at times t, t+1, and t+2. Data sampling at a high speed is required to get audio signals with high quality. Since there is no big difference between two sequentially sampled data, if we apply an xor operation to the two data and scan the operation result from MSB to LSB, fast processing is possible because only a small amount of data storage is required. In the example of t+1 xor t2 shown in Figure f, g bits are used to process 24-bit data [6]. 5) Packet formats
As shown in Figure h, a packet has a header part and a channel data part. The header part is divided into two parts: an I state part (1 bit) to represent either an I packet or a D packet, and a channel number part (3 bits) to indicate the number of the channel which will send data with the use of the packet. The channel data part of an I packet contains the xor operation value between the I point and the first sampled value. In case of a D packet, the part has the xor operation value between two consecutive values. If packet loss happens during the transmission of a D packet, the recovery operation begins from the following I packet. I packets are sent at regular intervals and the frequency of sending I packets can be determined according to transmission conditions. The total size of a packet has the range of 5 bits to 28 bits.
As shown in Figure h, a packet has a header part and a channel data part. The header part is divided into two parts: an I state part (1 bit) to represent either an I packet or a D packet, and a channel number part (3 bits) to indicate the number of the channel which will send data with the use of the packet. The channel data part of an I packet contains the xor operation value between the I point and the first sampled value. In case of a D packet, the part has the xor operation value between two consecutive values. If packet loss happens during the transmission of a D packet, the recovery operation begins from the following I packet. I packets are sent at regular intervals and the frequency of sending I packets can be determined according to transmission conditions. The total size of a packet has the range of 5 bits to 28 bits.
Figure i. Detailed diagram of data ‘generation for serial transmission Let us explain the diagram in detail. Analog signals from each channel are sent to the Channel Separation block after converting into /S-bus data formats with an audio ADC. In this case, digital audio signals (like S/PIDF) are sent to the block directly. The Channel Separation block separates SDATA data of each channel from mixed PS-bus data signals and sends them to Packet Data Generator blocks, which are divided into D and I blocks to generate D packets and I packets respectively. The Traffic Controller block produces packet generation signals to control their transmission rates according to transmission conditions. That is, according to this signal, the generation of I packets or D packets is determined.For example, consider that an I packet is generated every 20 packets in the digital audio signals with 44.1 kHz sampling speed. Signals can be recovered within, at most, 0.41us in case of a packet loss. Since a 5.1-channel audio system needs a smaller amount of data than the transmission bandwidth, and the Traffic Controller block generates many I packets, human beings can not recognize the packet loss.
Figure i. Detailed diagram of data ‘generation for serial transmission Let us explain the diagram in detail. Analog signals from each channel are sent to the Channel Separation block after converting into /S-bus data formats with an audio ADC. In this case, digital audio signals (like S/PIDF) are sent to the block directly. The Channel Separation block separates SDATA data of each channel from mixed PS-bus data signals and sends them to Packet Data Generator blocks, which are divided into D and I blocks to generate D packets and I packets respectively. The Traffic Controller block produces packet generation signals to control their transmission rates according to transmission conditions. That is, according to this signal, the generation of I packets or D packets is determined.For example, consider that an I packet is generated every 20 packets in the digital audio signals with 44.1 kHz sampling speed. Signals can be recovered within, at most, 0.41us in case of a packet loss. Since a 5.1-channel audio system needs a smaller amount of data than the transmission bandwidth, and the Traffic Controller block generates many I packets, human beings can not recognize the packet loss.
Gradually, PCs are moving into living rooms, as most audio sources are becoming digitized and various types of existing digital audio sources are best played back using comprehensive software running on a computer. The digitization of a living room multimedia environment can be more efficiently extended to the entire home environment by replacing the multiple-wired SERIAL SPEAKER WITH SOME MODIFICATIONS AND OVERCOMING ITS DISADVANTAGES WAS USED FC SMART SPEAKER CONTROL OF HOME AUDIO NETWORK. WHICH IS EXPLAINED BELLOW.
Gradually, PCs are moving into living rooms, as most audio sources are becoming digitized and various types of existing digital audio sources are best played back using comprehensive software running on a computer. The digitization of a living room multimedia environment can be more efficiently extended to the entire home environment by replacing the multiple-wired SERIAL SPEAKER WITH SOME MODIFICATIONS AND OVERCOMING ITS DISADVANTAGES WAS USED FC SMART SPEAKER CONTROL OF HOME AUDIO NETWORK. WHICH IS EXPLAINED BELLOW.
Fig. 1. Proposed setup of an intelligent home network audio speaker system. sub-controllers using a serial network cable. The sub-controllers either drive the speakers or monitor the rooms. The control of digital data streams through a centralized PC allows easy management of multiple sound sources at a much lower cost. In addition, a channel can be added simply by linking a sub-controller that controls a speaker with a different channel ID in a daisy chain fashion, instead of rewiring additional line from the analog amplifier to the speaker and upgrading the expensive central analog amplifier channel. The additional channel is activated by programming the main controller to issue audio packets for the particular sub-controller. We have previously developed a serial multi-channel speaker system [1-2] without the USB interface
Fig. 1. Proposed setup of an intelligent home network audio speaker system. sub-controllers using a serial network cable. The sub-controllers either drive the speakers or monitor the rooms. The control of digital data streams through a centralized PC allows easy management of multiple sound sources at a much lower cost. In addition, a channel can be added simply by linking a sub-controller that controls a speaker with a different channel ID in a daisy chain fashion, instead of rewiring additional line from the analog amplifier to the speaker and upgrading the expensive central analog amplifier channel. The additional channel is activated by programming the main controller to issue audio packets for the particular sub-controller. We have previously developed a serial multi-channel speaker system [1-2] without the USB interface
Fig. 2. A simple configuration for intelligent home audio network system The sub-controller through its digital input port can receive a motion detector result and inform the PC whether the room is occupied or not. A more sophisticated interface would use
Fig. 2. A simple configuration for intelligent home audio network system The sub-controller through its digital input port can receive a motion detector result and inform the PC whether the room is occupied or not. A more sophisticated interface would use
The architecture of the proposed hardware framework can be categorized into two parts. The first part is the USB interfac between PC and the main controller and the second part is the serial network interface between the main controller and the sut controllers. Fig.3 shows the detailed interface for the first part. And the digital sources supported are wave files and mp3 files.
The architecture of the proposed hardware framework can be categorized into two parts. The first part is the USB interfac between PC and the main controller and the second part is the serial network interface between the main controller and the sut controllers. Fig.3 shows the detailed interface for the first part. And the digital sources supported are wave files and mp3 files.
Table 1. Development specifications
Table 1. Development specifications
The FPGA operates with data received from the USB controller as shown in Figure m. The flow of audio signals is represented by a solid line, and flow of control signal for channel selection is represented by a dotted line. An addressing controller defines addresses to save sampling data received from USB controller to a dual port RAM. And Channel controller reads saved data from dual port RAM for a sampling interval. Data stream must not be stalled for continuous playback audio signals. Thus, the RAM should be updated and be read at a real time. Data is transmitted to speakers serially after compression and to be packetized by packet generator after data read from RAM is saved to each channel register. The system can transmit control data by using bulk transfer to select the chosen channel. The control data to selected channel set up packet’s ID.
The FPGA operates with data received from the USB controller as shown in Figure m. The flow of audio signals is represented by a solid line, and flow of control signal for channel selection is represented by a dotted line. An addressing controller defines addresses to save sampling data received from USB controller to a dual port RAM. And Channel controller reads saved data from dual port RAM for a sampling interval. Data stream must not be stalled for continuous playback audio signals. Thus, the RAM should be updated and be read at a real time. Data is transmitted to speakers serially after compression and to be packetized by packet generator after data read from RAM is saved to each channel register. The system can transmit control data by using bulk transfer to select the chosen channel. The control data to selected channel set up packet’s ID.
The most important criterion for the system is to play audio signals in a real time. So, channel data received from PC is sent to speaker at 48 kHz sampling frequency without omission. Because 1,024 bytes of data are sent for every 0.125ms, buffers or memories are required to meet the rate of 48 kHz. Because the data is updated and should be read in real-time, dual port RAM is used to continuously support burst writes and 48 kHz reads. The dual port RAM interface is shown in Figure j. An addressing controller chooses address to save data that is received USB controller from 0x0000h on the dual port RAM. And then, data should be read from 0x0000h on a dual port RAM at a sampling rate. It takes one second to read data from 0x0000h to OxBB7F on the dual port RAM, and this process is repeated continuously. The sampling frequency of the audio data is 48 kHz, therefore the PC must send 48,000 x 3 bytes per second for each room. I the case of isochronous transfer in USB 2.0, the host can transfers packets up to 1K bytes at a time with an interval of 0.125m: During one second, the host can send 8000 packets each containing 6 sampled data in a packet. Figure L shows process o isochronous packet transfer in PC applications. The first packet carries 1st-6th sampling data, and the second packet carries 7th 12th sampling data. With this process, 47,995th-48,000th sampling data are sent at the last. This process continues for one seconc and is repeated continuously. Consequently the maximum number of rooms supported is 56. However, the actual supporte number of rooms is less and is more critically dependent upon the number of channels per room. For instance, if there are stere channels for each room, the maximum number of supported rooms will drop down to 28. In order to provide sustained rate of 4 kHz PCM, dual port memory is required within the main controller. This ensures simplified real-time processing of audio data < each of the sub-controllers.
The most important criterion for the system is to play audio signals in a real time. So, channel data received from PC is sent to speaker at 48 kHz sampling frequency without omission. Because 1,024 bytes of data are sent for every 0.125ms, buffers or memories are required to meet the rate of 48 kHz. Because the data is updated and should be read in real-time, dual port RAM is used to continuously support burst writes and 48 kHz reads. The dual port RAM interface is shown in Figure j. An addressing controller chooses address to save data that is received USB controller from 0x0000h on the dual port RAM. And then, data should be read from 0x0000h on a dual port RAM at a sampling rate. It takes one second to read data from 0x0000h to OxBB7F on the dual port RAM, and this process is repeated continuously. The sampling frequency of the audio data is 48 kHz, therefore the PC must send 48,000 x 3 bytes per second for each room. I the case of isochronous transfer in USB 2.0, the host can transfers packets up to 1K bytes at a time with an interval of 0.125m: During one second, the host can send 8000 packets each containing 6 sampled data in a packet. Figure L shows process o isochronous packet transfer in PC applications. The first packet carries 1st-6th sampling data, and the second packet carries 7th 12th sampling data. With this process, 47,995th-48,000th sampling data are sent at the last. This process continues for one seconc and is repeated continuously. Consequently the maximum number of rooms supported is 56. However, the actual supporte number of rooms is less and is more critically dependent upon the number of channels per room. For instance, if there are stere channels for each room, the maximum number of supported rooms will drop down to 28. In order to provide sustained rate of 4 kHz PCM, dual port memory is required within the main controller. This ensures simplified real-time processing of audio data < each of the sub-controllers.
Bandwidth of the network cable side can be maximized using a compression scheme. The compression scheme used is delta coding. The delta codes of each channel were combined with a fixed rate of PCM data to limit the error accumulation. The intermittent PCM (29 bits, including the header) data corrects any noise that affected the channel during delta coding or data or data overflow which depends on the number of bits used for delta coding (4 bits for the difference; 9 bits including the header for this implementation). Fig. 4 shows the detailed description of the serial network transmission controller within the main controller. The PCM data rate can be dynamically adjusted for optimal rate to strike a balance between data compression and
Bandwidth of the network cable side can be maximized using a compression scheme. The compression scheme used is delta coding. The delta codes of each channel were combined with a fixed rate of PCM data to limit the error accumulation. The intermittent PCM (29 bits, including the header) data corrects any noise that affected the channel during delta coding or data or data overflow which depends on the number of bits used for delta coding (4 bits for the difference; 9 bits including the header for this implementation). Fig. 4 shows the detailed description of the serial network transmission controller within the main controller. The PCM data rate can be dynamically adjusted for optimal rate to strike a balance between data compression and
The second part of the framework involves interactions between the main controller and the sub-controllers. This part of the hardware interface is similar to the result we have presented for serial channel speaker system. Before transmitting data serially, sampling data read from dual port RAM is compressed and packetized. Figure f illustrates the process. Data read from RAM is saved in the channel register. And that data is compressed in compression block of packet generator. The channel data and that is sent using bulk transmission sets packet’s ID and a packet is generated with compressed data and the ID. The serial transfer block transmits a packet serially for each channel. Figure n shows a flow of serial transmission. audio quality. In this implementation, however, the PCM data rate was fixed to every 20 packets per channel. Therefore, < average of 10 bits per sample is achieved.
The second part of the framework involves interactions between the main controller and the sub-controllers. This part of the hardware interface is similar to the result we have presented for serial channel speaker system. Before transmitting data serially, sampling data read from dual port RAM is compressed and packetized. Figure f illustrates the process. Data read from RAM is saved in the channel register. And that data is compressed in compression block of packet generator. The channel data and that is sent using bulk transmission sets packet’s ID and a packet is generated with compressed data and the ID. The serial transfer block transmits a packet serially for each channel. Figure n shows a flow of serial transmission. audio quality. In this implementation, however, the PCM data rate was fixed to every 20 packets per channel. Therefore, < average of 10 bits per sample is achieved.
Figure n. Packet transmission process Each channel packet is generated at the rate of 48 kHz and is sent serially and sequentially before a next packet is generated. Because all speakers are connected through a single line, each speaker verifies all packets’ IDs, and chooses and reads a packet that has the corresponding speaker’s ID. Then, the speaker decompresses the compressed data and the DAC is used to reproduce the audio signal. Packet regeneration process is shown in Figure p.
Figure n. Packet transmission process Each channel packet is generated at the rate of 48 kHz and is sent serially and sequentially before a next packet is generated. Because all speakers are connected through a single line, each speaker verifies all packets’ IDs, and chooses and reads a packet that has the corresponding speaker’s ID. Then, the speaker decompresses the compressed data and the DAC is used to reproduce the audio signal. Packet regeneration process is shown in Figure p.
The communication protocol does not use error correction capability since it is operated at a relatively low frequency. The only difference is the digital input provided to the subcontroller for room monitoring function. When a scan is requested by the PC, each sub-controller receives the scan command. As soon as the scan command is sent, the main controller switches to a receive mode and waits for three clock cycles before returning to a transmit mode. The scan command is detected at the sub-controller
The communication protocol does not use error correction capability since it is operated at a relatively low frequency. The only difference is the digital input provided to the subcontroller for room monitoring function. When a scan is requested by the PC, each sub-controller receives the scan command. As soon as the scan command is sent, the main controller switches to a receive mode and waits for three clock cycles before returning to a transmit mode. The scan command is detected at the sub-controller
To demonstrate the intelligent home network audio system, we constructed a simplified configuration where 4 subcontrollers are connected to the main controller. As shown in Fig. 6, the main controller is composed of a processor core with an embedded USB 2.0 controller and an FPGA chip. The processor core performs the enumeration process. For I/O, we constructed pipes with an isochronous OUT endpoint and a
To demonstrate the intelligent home network audio system, we constructed a simplified configuration where 4 subcontrollers are connected to the main controller. As shown in Fig. 6, the main controller is composed of a processor core with an embedded USB 2.0 controller and an FPGA chip. The processor core performs the enumeration process. For I/O, we constructed pipes with an isochronous OUT endpoint and a
assigned to the room is played. The operation of the main controller and sub-controllers are illustrated in Fig. 8. The main controller, which is directly controlled through the USB bus, receives the data frames from the PC. The USB controller within the main controller board and the FPGA are used to extract the channel information, scan commands, and the raw audio data. The bulk transfer mode is used to both send and receive the scan commands and the scan results respectively. As shown in the flowchart, when the main controller receives a frame data, it first checks for a scan command. If there are no scan commands, the audio sources are sent using the channel data and the previously stored occupancy information for each room. Upon detection of the scan command, all channels are sequentially requested for the scan result by issuing a scan command to the sub-controller. Note that individual channel scan information is requested for an audio sample period. Therefore to scan all possible rooms, at least four data sample periods of audio signals are spent, provided that there were no errors during the bulk transfer. During the scanning operation both the main controller and the sub-controller that received the scan command switch between receive and transmit mode within 625ns. Since the length of the cables between the subcontrollers are short in this demonstration, we may actually require slightly higher SCLK rate to provide more spare cycles for the bidirectional transitions. The selected sub- controller simply decodes the headers to determine whether the packet is a PCM data, delta code, or a scan command. If the header indicates that it is a scan command, the data from the external input of the sub-controller is sent back to the main controller. If it is a delta code, it is decompressed back to PCM and it is sent to the DAC. Although scanning operations need not be frequent, we provided scanning command on each of the USB frames, or every 0.125ms. A push button on the FPGA board emulating the motion detectors was used to verify that correct room was identified. Also in this demonstration, we assumed it is a single floor house. The GUI in Fig. 9 indicates that room 3 representing the third sub-controller from the top is provided bulk IN/OUT endpoints. Fig. 7 shows the sub-controller board. The board has an output interface for the speaker. The speaker is driven by the DAC output which converts the decompressed PCM data from the FPGA into analog audio signal. In addition, the digital input is provided directly to an FPGA input pin such that an external motion detector can interface to it. The actual test setup involved 4 sub-controllers driven by a main controller connected through USB with a notebook computer. For the demonstration, the motion detector output is emulated by an FPGA board. The FPGA board outputs 4 digital signals and each of the signals are connected to the digital inputs of the 4 sub-controllers. The notebook scans the data from each of the sub- controllers periodically and updates the occupancy information. If the room is determined to be occupant, then an audio source Bien panterniiios Ok} ew eile
assigned to the room is played. The operation of the main controller and sub-controllers are illustrated in Fig. 8. The main controller, which is directly controlled through the USB bus, receives the data frames from the PC. The USB controller within the main controller board and the FPGA are used to extract the channel information, scan commands, and the raw audio data. The bulk transfer mode is used to both send and receive the scan commands and the scan results respectively. As shown in the flowchart, when the main controller receives a frame data, it first checks for a scan command. If there are no scan commands, the audio sources are sent using the channel data and the previously stored occupancy information for each room. Upon detection of the scan command, all channels are sequentially requested for the scan result by issuing a scan command to the sub-controller. Note that individual channel scan information is requested for an audio sample period. Therefore to scan all possible rooms, at least four data sample periods of audio signals are spent, provided that there were no errors during the bulk transfer. During the scanning operation both the main controller and the sub-controller that received the scan command switch between receive and transmit mode within 625ns. Since the length of the cables between the subcontrollers are short in this demonstration, we may actually require slightly higher SCLK rate to provide more spare cycles for the bidirectional transitions. The selected sub- controller simply decodes the headers to determine whether the packet is a PCM data, delta code, or a scan command. If the header indicates that it is a scan command, the data from the external input of the sub-controller is sent back to the main controller. If it is a delta code, it is decompressed back to PCM and it is sent to the DAC. Although scanning operations need not be frequent, we provided scanning command on each of the USB frames, or every 0.125ms. A push button on the FPGA board emulating the motion detectors was used to verify that correct room was identified. Also in this demonstration, we assumed it is a single floor house. The GUI in Fig. 9 indicates that room 3 representing the third sub-controller from the top is provided bulk IN/OUT endpoints. Fig. 7 shows the sub-controller board. The board has an output interface for the speaker. The speaker is driven by the DAC output which converts the decompressed PCM data from the FPGA into analog audio signal. In addition, the digital input is provided directly to an FPGA input pin such that an external motion detector can interface to it. The actual test setup involved 4 sub-controllers driven by a main controller connected through USB with a notebook computer. For the demonstration, the motion detector output is emulated by an FPGA board. The FPGA board outputs 4 digital signals and each of the signals are connected to the digital inputs of the 4 sub-controllers. The notebook scans the data from each of the sub- controllers periodically and updates the occupancy information. If the room is determined to be occupant, then an audio source Bien panterniiios Ok} ew eile
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