Fig. 1. Basic principle of the delay measurement method. Fig. 3. Timing diagram of the test circuit showing 3 cycles of operations. tetk.s is the clock to Q delay between the the clock edge and the output (S) of the Launch Toggle Flip-flop. tg is the propagation delay of the XOR gate. lsetup-Q and t)old_Q are the setup and hold time of the sampling register SR. tsetup.c and tpotd_c are the setup and hold time of the capture register CR. Fig. 4. Detailed FRD on a Cyclone-Il FPGA. ‘ig. 5. An array of FRDs on an Cyclone-II EP2C35, where tyetay max aNd tdelay-min are the delays of the slowest and fastest CUT respectively. The required test clock frequency range, finin and finar ate dependent on the delay of the CUT and they are given by the following inequalities: Fig. 6. Test Clock Generator using a Virtex-4 and a Cyclone-IL. The signal “ReProgram Data & Control” from the DE2 is a 22 bit bus containing the 20 bit M and D data for both DCMs, ReProgram enable and reset signals. The Clk locked signal informs the DE2 that the Clock is ready and it can begin testing with it. Fig. 7. Frequency steps size from 128 to 840MHz. Fig. 9. The plot shows the dynamic resolution of timing measurements. Fig. 10. (a) The scattered plot of half clock cycle (7'/2) at 25 % failure rate with exponential best fit. (b) Histogram of residuals of the failure rate measurements around the exponential best fit. Fig. 8. (a) The failure rate obtained from a PUT containing 2 LUTs. (b) A timing diagram showing the conditions resulting in region A,B and C in th failure rate plot. teik_s—p and totk_s—n are the clock to Q delay on the Launch Toggle Flop-flop corresponding to positive and negative edge respectivel) tDetay-p and tpetayn are the delay of positive and negative edge through the PUT. Where tpos = teik_s—p + tDelay_p and tneg = tetk.s—n + tDelayn Fig. 12. (a) Modified first-fail detector (FFD) circuit; (b) Sector based parallel BIST system schematic. Fig. 13. An array of sectors on the Cyclone-II EP2C35, each sector contains an array of 16 FFD test blocks. Fig. 14. (a-g) Progressive failure maps of FFDs.
