Academia.eduAcademia.edu

Figure 5 – uploaded by Foram Shingala

See full PDFdownloadDownload figure
Figure 5: Plot recording the outcome of the Monte Carlo simulations for QBER from the range of {7% to 30%} on various block sizes (in bits) with corresponding code rate as the primary axis. maximum of 50 decoder iterations. The primary objective of rate-adaptive LDPC codes in this design is to take a full- capacity LDPC code and dynamically adjust the code rate based on the QBER. This is done to optimize the code’s performance. Figure 5 provides an illustration of this rate adaptation process.

Figure 5 Plot recording the outcome of the Monte Carlo simulations for QBER from the range of {7% to 30%} on various block sizes (in bits) with corresponding code rate as the primary axis. maximum of 50 decoder iterations. The primary objective of rate-adaptive LDPC codes in this design is to take a full- capacity LDPC code and dynamically adjust the code rate based on the QBER. This is done to optimize the code’s performance. Figure 5 provides an illustration of this rate adaptation process.

Related Figures (11)

Figure 2: FPGA block design for the classical post-processing engine describing all the modules and their interconnects. Author et a/.: Preparation of Papers for IEEE Transactions on Quantum Engineering
Figure 2: FPGA block design for the classical post-processing engine describing all the modules and their interconnects. Author et a/.: Preparation of Papers for IEEE Transactions on Quantum Engineering
Figure 3: MapReduce programming model-based framework for Information Reconciliation.
Figure 3: MapReduce programming model-based framework for Information Reconciliation.
Algorithm 2 Error Verification Algorithm
Algorithm 2 Error Verification Algorithm
The approach described in Andrew Thangaraj et al.’s work [22] is followed for deriving the LDPC codes in the proposed design. This reference likely provides detailed insights into constructing LDPC codes tailored for quantum communica- tion systems. Figure 4 illustrates the algorithmic flow of the LDPC code implementation, which involves steps such as code construction, threshold determination, and LDPC code adaptation based on the measured QBER.
The approach described in Andrew Thangaraj et al.’s work [22] is followed for deriving the LDPC codes in the proposed design. This reference likely provides detailed insights into constructing LDPC codes tailored for quantum communica- tion systems. Figure 4 illustrates the algorithmic flow of the LDPC code implementation, which involves steps such as code construction, threshold determination, and LDPC code adaptation based on the measured QBER.
Figure 6: Experimental scheme of (a) BB84 protocol and (b) BBM92 protocol, that includes both optical and electronic arrangements. EPS: entangled photon source, FM: flip mirror, PM: prism mirror, M: mirror, F: filter, FC: fiber coupler, BS: balanced beam splitter, PBS: polarization beam splitter, DPBS: duel wavelength PBS, HWP: half-wave plate, SMF: single-mode fiber, MMF: multi-mode fiber, SPCM: single-photon counting modules, PPKTP: Periodically poled potassium titanyl phosphate. LD: laser driver, BD: beam dumper. Author et al.: Preparation of Papers for IEEE Transactions on Quantum Engineering
Figure 6: Experimental scheme of (a) BB84 protocol and (b) BBM92 protocol, that includes both optical and electronic arrangements. EPS: entangled photon source, FM: flip mirror, PM: prism mirror, M: mirror, F: filter, FC: fiber coupler, BS: balanced beam splitter, PBS: polarization beam splitter, DPBS: duel wavelength PBS, HWP: half-wave plate, SMF: single-mode fiber, MMF: multi-mode fiber, SPCM: single-photon counting modules, PPKTP: Periodically poled potassium titanyl phosphate. LD: laser driver, BD: beam dumper. Author et al.: Preparation of Papers for IEEE Transactions on Quantum Engineering
Table 3: Implementation results for multiple parallel instances of the mapper. protocol, collecting and processing 1OMB of raw key bits. The variations in QBER recorded in the experiments are used to validate the effectiveness of rate-adaptive LDPC codes with a threshold error correction capacity of 25% at 90% effi- ciency. Table 4 summarizes the average performance of both
Table 3: Implementation results for multiple parallel instances of the mapper. protocol, collecting and processing 1OMB of raw key bits. The variations in QBER recorded in the experiments are used to validate the effectiveness of rate-adaptive LDPC codes with a threshold error correction capacity of 25% at 90% effi- ciency. Table 4 summarizes the average performance of both
Table 1: Performance metrics of each KDE module imple- mented on hardware including both Alice’s and Bob’s design. Table 2: Utilization report of the Alice (transmitter) and Bob (receiver) KDE designs without MapReduce framework (WOMF), and with MapReduce framework (WMF; 3 parallel in- stances).
Table 1: Performance metrics of each KDE module imple- mented on hardware including both Alice’s and Bob’s design. Table 2: Utilization report of the Alice (transmitter) and Bob (receiver) KDE designs without MapReduce framework (WOMF), and with MapReduce framework (WMF; 3 parallel in- stances).
Figure 7: Plot of (a) Number of parallel instances of mapper in the Hadoop framework vs execution time in seconds, and {), Execution time, in seconds, vs Key rate in Kbps, for W, BB84, and BBM92 QKD protocols at varying QBER (measured during the quantum experiment). the FPGA implementation and CPU core implementation. Table 3 presents the performance of our implemented design across various QKD experimental settings and compares performance at different QBER values. It’s worth noting that while increasing the number of parallel instances, there is a significant increase in key rate and subsequently a decrease in utilization time due to the parallel post-processing system implementation. Performance-wise, Figure. 7 illustrates that as QBER increases, execution time or latency also increases, inversely affecting the secret key extraction rate. However, leveraging more parallel instances in the design can reduce latency, thereby increasing the key rate.
Figure 7: Plot of (a) Number of parallel instances of mapper in the Hadoop framework vs execution time in seconds, and {), Execution time, in seconds, vs Key rate in Kbps, for W, BB84, and BBM92 QKD protocols at varying QBER (measured during the quantum experiment). the FPGA implementation and CPU core implementation. Table 3 presents the performance of our implemented design across various QKD experimental settings and compares performance at different QBER values. It’s worth noting that while increasing the number of parallel instances, there is a significant increase in key rate and subsequently a decrease in utilization time due to the parallel post-processing system implementation. Performance-wise, Figure. 7 illustrates that as QBER increases, execution time or latency also increases, inversely affecting the secret key extraction rate. However, leveraging more parallel instances in the design can reduce latency, thereby increasing the key rate.
Table 4: MapReduce-based Information Reconciliation; Implementation validation on Intel CPU Core for {1,3,4} number of parallel instances using Python’s inbuilt functional programming feature, running same algorithms. r.
Table 4: MapReduce-based Information Reconciliation; Implementation validation on Intel CPU Core for {1,3,4} number of parallel instances using Python’s inbuilt functional programming feature, running same algorithms. r.
580 California St., Suite 400
San Francisco, CA, 94104
© 2025 Academia. All rights reserved