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Figure 7: Twiddle factors expressed as complex vectors.

Figure 7 Twiddle factors expressed as complex vectors.

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A design pattern is the description of a general solution to a recurring problem|8]. Although design patterns were originally introduced for Object- Oriented software problems, their application is also adopted for parallel programming. Parallel programming patterns mainly differ in their classifi- cation. We propose a layered structure for parallel embedded software based on Our Pattern Language (OPL)[10], which is used for high-performance computing applications. A number of families of patterns are further ex- plained, namely first patterns which decompose the problem into parallel execution units. This is called the Finding Concurrency Design Space[11]. ext there are patterns which describe the overall parallel architecture and software structure. Then there are patterns which introduce typical paral- el algorithm structures. Finally we elaborate one patterns which describe the parallel implementation mechanisms [11]. Each level in this hierarchi- cal structure can interact with the so called Optimization Design Space|16]. This is a collection of application specific optimizations in order to obtain optimal parallel execution. The lowest level in the hierarchy, the implemen- tation strategy patterns, can use additional supporting structures, such as mutexes or semaphores. The layered design is illustrated in Figure 1 Figure 1: Parallel Design Pattern hierarchy.
A design pattern is the description of a general solution to a recurring problem|8]. Although design patterns were originally introduced for Object- Oriented software problems, their application is also adopted for parallel programming. Parallel programming patterns mainly differ in their classifi- cation. We propose a layered structure for parallel embedded software based on Our Pattern Language (OPL)[10], which is used for high-performance computing applications. A number of families of patterns are further ex- plained, namely first patterns which decompose the problem into parallel execution units. This is called the Finding Concurrency Design Space[11]. ext there are patterns which describe the overall parallel architecture and software structure. Then there are patterns which introduce typical paral- el algorithm structures. Finally we elaborate one patterns which describe the parallel implementation mechanisms [11]. Each level in this hierarchi- cal structure can interact with the so called Optimization Design Space|16]. This is a collection of application specific optimizations in order to obtain optimal parallel execution. The lowest level in the hierarchy, the implemen- tation strategy patterns, can use additional supporting structures, such as mutexes or semaphores. The layered design is illustrated in Figure 1 Figure 1: Parallel Design Pattern hierarchy.
Figure 2: Thread Pool pattern. This formula indicates that finding larger prime numbers will require mor trial divisions. The implementation on a multicore system of the trial divisio1 algorithm is based on the Thread Pool pattern as shown in figure 2.
Figure 2: Thread Pool pattern. This formula indicates that finding larger prime numbers will require mor trial divisions. The implementation on a multicore system of the trial divisio1 algorithm is based on the Thread Pool pattern as shown in figure 2.
Table 1: Execution time comparison on different CPU0 load.
Table 1: Execution time comparison on different CPU0 load.
By manipulating the load balance between both cores we managed to achieve a speedup close to the theoretical maximum stated by Amdahl as illustrated in figure 3. Figure 3: Performance comparison between Amdahl’s theoretical maximum and measured values.
By manipulating the load balance between both cores we managed to achieve a speedup close to the theoretical maximum stated by Amdahl as illustrated in figure 3. Figure 3: Performance comparison between Amdahl’s theoretical maximum and measured values.
Figure 4: Radix-2 Cooley-Tukey decomposition [14]. bination of bit reversed pairs of input number indices the general DFT can be calculated. Calculation pairs are represented in a butterfly diagram as shown in Figure 5[3]. In the first stage a pair of chunks forms the input of the first-stage calculation. The output of the first-stage calculation forms
Figure 4: Radix-2 Cooley-Tukey decomposition [14]. bination of bit reversed pairs of input number indices the general DFT can be calculated. Calculation pairs are represented in a butterfly diagram as shown in Figure 5[3]. In the first stage a pair of chunks forms the input of the first-stage calculation. The output of the first-stage calculation forms
Figure 5: Butterfly diagram [3]. the input of the second stage calculation. This is repeated until the full data set has been calculated. The number of calculation stages required is determined by log2N operations.
Figure 5: Butterfly diagram [3]. the input of the second stage calculation. This is repeated until the full data set has been calculated. The number of calculation stages required is determined by log2N operations.
Figure 6: Singlecore implementation with N=8.
Figure 6: Singlecore implementation with N=8.
Figure 8: Map-reduce design pattern in case of a 8-point FFT.
Figure 8: Map-reduce design pattern in case of a 8-point FFT.
Figure 9: Devide-and-Conquer design pattern.
Figure 9: Devide-and-Conquer design pattern.
Figure 10: Fork/Join design pattern.
Figure 10: Fork/Join design pattern.
Figure 11: Achieved parallel speedup for different values of N.
Figure 11: Achieved parallel speedup for different values of N.
Figure 12: Calculated frequency spectrum of a 15kHz sine wave.
Figure 12: Calculated frequency spectrum of a 15kHz sine wave.
Figure 13: Calculated frequency spectrum of an EEG scan.
Figure 13: Calculated frequency spectrum of an EEG scan.
Related topics:
RoboticsComputer ScienceParallel ComputingImage ProcessingEmbedded SystemsDesign PatternsMultiprocessor SchedulingHybrid ComputingParallel design patternsMulti-Core Processor
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