Academia.eduAcademia.edu

Figure 14 – uploaded by Vratislav Michal

See full PDFdownloadDownload figure
Depending on the process parameters and on the value of Ros, this method can yield an improvement of dVos/dT, attributed to the improved matching of Vj1n/t1p. However, this improvement is not always achieved, and Ros may also result in the degradation of the temperature drift. In this case, a small value of Ros << 1/gnya,n) may be required to preserve original temperature characteristic of gman(T). However, using a low Ros value implies an increase in the trimming current JauxL.r). A method for reducing this trimming current is presented in section IX. Fig.15. Example of the characteristic obtained with the single resistance tail offset voltage generator, variant from Fig. /4. b).

Figure 15 Depending on the process parameters and on the value of Ros, this method can yield an improvement of dVos/dT, attributed to the improved matching of Vj1n/t1p. However, this improvement is not always achieved, and Ros may also result in the degradation of the temperature drift. In this case, a small value of Ros << 1/gnya,n) may be required to preserve original temperature characteristic of gman(T). However, using a low Ros value implies an increase in the trimming current JauxL.r). A method for reducing this trimming current is presented in section IX. Fig.15. Example of the characteristic obtained with the single resistance tail offset voltage generator, variant from Fig. /4. b).

Related Figures (20)

Fig. 1. Basic OTA structures used as the basis for operational amplifiers and comparators [1], [2]: a) two gain stages Miller OTA, 5) single gain stage symmetrical OTA and c) folded cascode OTA with single gain stage. namely threshold voltage Vry and_ transconductance parameter f = tnpCox(W/L). The parameter / depends on the electron/hole mobility “np, gate oxide capacitance per unit area Cox, and channel aspect ratio W/L. In saturation, the gate source voltage, Vas, can be expressed from (1) as:
Fig. 1. Basic OTA structures used as the basis for operational amplifiers and comparators [1], [2]: a) two gain stages Miller OTA, 5) single gain stage symmetrical OTA and c) folded cascode OTA with single gain stage. namely threshold voltage Vry and_ transconductance parameter f = tnpCox(W/L). The parameter / depends on the electron/hole mobility “np, gate oxide capacitance per unit area Cox, and channel aspect ratio W/L. In saturation, the gate source voltage, Vas, can be expressed from (1) as:
Fig. 2. Structure of NMOS Miller OTA from Fig. 7 a) with programmable auxiliary offset generators allowing to compensate static offset voltage Vos. The remainder of this paper is organized as follows: In section IT a list of methods allowing the offset compensation is introduced. Section ITI presents the general offset equations and fundamental thermal characteristics of the MOS transistor. The following sections, IV— IX, present, one by one, the methods listed in section IJ and also describe the resulting thermal behavior of Vos. The primary emphasis is placed on the description of the new methods presented in sections IV. B, V.B, VI. B, VIII, and IX, which offer significant improvement in temperature drift and reliable improvements in offset voltage trimming.
Fig. 2. Structure of NMOS Miller OTA from Fig. 7 a) with programmable auxiliary offset generators allowing to compensate static offset voltage Vos. The remainder of this paper is organized as follows: In section IT a list of methods allowing the offset compensation is introduced. Section ITI presents the general offset equations and fundamental thermal characteristics of the MOS transistor. The following sections, IV— IX, present, one by one, the methods listed in section IJ and also describe the resulting thermal behavior of Vos. The primary emphasis is placed on the description of the new methods presented in sections IV. B, V.B, VI. B, VIII, and IX, which offer significant improvement in temperature drift and reliable improvements in offset voltage trimming.
Fig. 4. Simulated temperature characteristic of uncompensated offset voltage Vos of the OTA with PMOS differential pair. Simulation parameters were: W/Li2 = 160p/1p, W/Ls.6 = 40p/2u, W/Ls,6 = 20/2, fo = 30pA. An example simulation of the input offset voltage Vos originating from random process parameters variation (Monte-Carlo simulation) is shown in Fig. 4. The figure shows Vos vs. temperature characteristic revealing offset peak values ranging from -—3.5mV to +3.5mV (¢=950pV). Compared to this, the temperature drift dVos/dT of the offset voltage is relatively small due to stable AV Han). The simulation was conducted using the folded cascode OTA illustrated in Fig. / c). This folded cascode includes 2 gain stage based on the current mirror Ms,6 with the same channel polarity as the input differential pair (i.e. PMOS in Fig. 1 c). This ensures temperature stable term Jucu/miy and thus a stable contribution of AVrHcms,) in (10), which is
Fig. 4. Simulated temperature characteristic of uncompensated offset voltage Vos of the OTA with PMOS differential pair. Simulation parameters were: W/Li2 = 160p/1p, W/Ls.6 = 40p/2u, W/Ls,6 = 20/2, fo = 30pA. An example simulation of the input offset voltage Vos originating from random process parameters variation (Monte-Carlo simulation) is shown in Fig. 4. The figure shows Vos vs. temperature characteristic revealing offset peak values ranging from -—3.5mV to +3.5mV (¢=950pV). Compared to this, the temperature drift dVos/dT of the offset voltage is relatively small due to stable AV Han). The simulation was conducted using the folded cascode OTA illustrated in Fig. / c). This folded cascode includes 2 gain stage based on the current mirror Ms,6 with the same channel polarity as the input differential pair (i.e. PMOS in Fig. 1 c). This ensures temperature stable term Jucu/miy and thus a stable contribution of AVrHcms,) in (10), which is
Fig. 3. Parameters of a PMOS differential pair vs. temperature for zero differential input voltage. A mismatch between M, and Mb) was introduced by a Monte-Carlo simulation. On the other hand, both Vrami) and Vra2) exhibit thermal dependency described by identical (12). As a result, changes in ambient temperature do not significantly affect their difference AVryany. Generally, transistor statistical models ignore this parameter, as shown in Fig. 3, where the temperature drift of AVrany is only 76nV. Consequently, the differential pair with a low Vov exhibits low temperature drift of the uncompensated offset voltage Vos, when compared to the overall range of Vos (see Fig. 4 in the next section).
Fig. 3. Parameters of a PMOS differential pair vs. temperature for zero differential input voltage. A mismatch between M, and Mb) was introduced by a Monte-Carlo simulation. On the other hand, both Vrami) and Vra2) exhibit thermal dependency described by identical (12). As a result, changes in ambient temperature do not significantly affect their difference AVryany. Generally, transistor statistical models ignore this parameter, as shown in Fig. 3, where the temperature drift of AVrany is only 76nV. Consequently, the differential pair with a low Vov exhibits low temperature drift of the uncompensated offset voltage Vos, when compared to the overall range of Vos (see Fig. 4 in the next section).
Fig. 5 illustrates an example of the trimming outcome realized by the constant current injection trimming, using identical OTA as the simulation shown in Fig. 4. The offset is reduced down to pV level at the trimming temperature but increases rapidly at other temperatures. Consequently, compensating thermally stable offset AVryan) through thermally unstable transconductance gman) leads to a significant thermal drift dVos/dT compared to the initial uncompensated Vos shown in Fig. 4. In practical applications, automatic trimming by constant current injection should be performed periodically, or in response to changes in IC temperature. Fig. 5. Example of the compensated Vos versus temperature obtained with constant current injection method. Simulation done with the identical OTA as the example from Fig. 4.
Fig. 5 illustrates an example of the trimming outcome realized by the constant current injection trimming, using identical OTA as the simulation shown in Fig. 4. The offset is reduced down to pV level at the trimming temperature but increases rapidly at other temperatures. Consequently, compensating thermally stable offset AVryan) through thermally unstable transconductance gman) leads to a significant thermal drift dVos/dT compared to the initial uncompensated Vos shown in Fig. 4. In practical applications, automatic trimming by constant current injection should be performed periodically, or in response to changes in IC temperature. Fig. 5. Example of the compensated Vos versus temperature obtained with constant current injection method. Simulation done with the identical OTA as the example from Fig. 4.
Fig. 6. Temperature pre-compensated current source generating Jos(T) compensating 1/gman) temperature variation of PMOS differential pair. Method introduced in this section relies on the generation of the temperature pre-compensated currents Jaux(.r(T) generated by a supplementary current mirror Mr — Ms. This current mirror contains an auxiliary offset Vosicm, applied between the gates of the reference and source transistors Mr and Ms. As shown in Fig. 6, the drain current of each of Ms (Ma or Mg in Fig. 7) will experience a shift with respect to the reference current denoted as Jos(T) = per — Js(T). The shift in Jos for a given temperature can be determined using the drain current formula (1) re-written for JpEr as:
Fig. 6. Temperature pre-compensated current source generating Jos(T) compensating 1/gman) temperature variation of PMOS differential pair. Method introduced in this section relies on the generation of the temperature pre-compensated currents Jaux(.r(T) generated by a supplementary current mirror Mr — Ms. This current mirror contains an auxiliary offset Vosicm, applied between the gates of the reference and source transistors Mr and Ms. As shown in Fig. 6, the drain current of each of Ms (Ma or Mg in Fig. 7) will experience a shift with respect to the reference current denoted as Jos(T) = per — Js(T). The shift in Jos for a given temperature can be determined using the drain current formula (1) re-written for JpEr as:
Fig. 7. Compensation by /auxw.x(T) current injection implemented by current source Mr, Ma and Mg. Ma., correspond to Msg in previous equations. Ros << 1/gma.p allows to preserve desired Vj1p temperature dependency of Jos (see section IX). Bulk terminals of Ma. are tied to the sources to eliminate the substrate effect.
Fig. 7. Compensation by /auxw.x(T) current injection implemented by current source Mr, Ma and Mg. Ma., correspond to Msg in previous equations. Ros << 1/gma.p allows to preserve desired Vj1p temperature dependency of Jos (see section IX). Bulk terminals of Ma. are tied to the sources to eliminate the substrate effect.
As shown in ref. [13] addressing a different application, the implementation of Vosicm) between the current mirror gates is inconvenient and requires a significant number of additional biasing circuits. To address this limitation, Fig. 7 introduces a current mirror Mra with additional source resistances Rog and programmable current sources Jpacc.p). These current sources adjust the voltages Vauxc.r). For unipolar current sources Jpacc,r), Vaux(L.r) is adjusted on either the left or right Ros, depending on the initial polarity of Vos. Similarly to the structure shown in Fig. 6, the value of Ios (18) is determined by the difference Jauxit) — Jauxe). Fig. 8. Outcome of the offset compensation by Jauxa,x(T) temperature compensated current source Mr, Ma and Mp. As described in the upcoming Section IX, the additional source resistances Ros produce transconductance temperature dumping, which may result in degradation, but in some cases also contribute to the improvement of the temperature offset compensation effectiveness. In order to accurately reproduce the temperature behavior of gmanT), a small value of Ros
As shown in ref. [13] addressing a different application, the implementation of Vosicm) between the current mirror gates is inconvenient and requires a significant number of additional biasing circuits. To address this limitation, Fig. 7 introduces a current mirror Mra with additional source resistances Rog and programmable current sources Jpacc.p). These current sources adjust the voltages Vauxc.r). For unipolar current sources Jpacc,r), Vaux(L.r) is adjusted on either the left or right Ros, depending on the initial polarity of Vos. Similarly to the structure shown in Fig. 6, the value of Ios (18) is determined by the difference Jauxit) — Jauxe). Fig. 8. Outcome of the offset compensation by Jauxa,x(T) temperature compensated current source Mr, Ma and Mp. As described in the upcoming Section IX, the additional source resistances Ros produce transconductance temperature dumping, which may result in degradation, but in some cases also contribute to the improvement of the temperature offset compensation effectiveness. In order to accurately reproduce the temperature behavior of gmanT), a small value of Ros
As mentioned earlier, the input differential pair transconductance gman) exhibits strong temperature dependency. The temperature drift obtained by the current mirror width adjustment is therefore similar to the temperature drift obtained by the constant current injection method presented in section IV. A. In practical application, offset trimming is to be performed periodically or with the temperature change of the integrated circuit. Fig. 9. Adjustment of the active load current mirror: a) adjusting the physical size (W) [13], and b) by adjusting the gate offset voltage Voscw. Ros << 1/gm3,4 iS required to preserve Vip temperature dependency of Jos. Bulk terminals in b) are tied to sources to eliminate the substrate effect of M34.
As mentioned earlier, the input differential pair transconductance gman) exhibits strong temperature dependency. The temperature drift obtained by the current mirror width adjustment is therefore similar to the temperature drift obtained by the constant current injection method presented in section IV. A. In practical application, offset trimming is to be performed periodically or with the temperature change of the integrated circuit. Fig. 9. Adjustment of the active load current mirror: a) adjusting the physical size (W) [13], and b) by adjusting the gate offset voltage Voscw. Ros << 1/gm3,4 iS required to preserve Vip temperature dependency of Jos. Bulk terminals in b) are tied to sources to eliminate the substrate effect of M34.
Fig. 11. Outcome of the offset compensation by the trimming of the active- load gate voltage Vosicm); based on OTA from Fig. 10. In the OTA from Fig. 2, Vosccm is generated between the gates of the current mirror M3,4. Similarly, as depicted in Fig. 7, a more convenient implementation relies on the use of additional source resistances Ros, and unipolar current sources Jpacc,r). An example of this implementation is detailed in Fig. 9 b). Here, Vosccw results from the difference between voltage drop on the left and right resistances Rog, i.e. Voscomy= Vauxi)— Vauxey. For Ipacc.ry= 0, Vauxcir) are solely determined by DC bias currents of Ms, and are equals.
Fig. 11. Outcome of the offset compensation by the trimming of the active- load gate voltage Vosicm); based on OTA from Fig. 10. In the OTA from Fig. 2, Vosccm is generated between the gates of the current mirror M3,4. Similarly, as depicted in Fig. 7, a more convenient implementation relies on the use of additional source resistances Ros, and unipolar current sources Jpacc,r). An example of this implementation is detailed in Fig. 9 b). Here, Vosccw results from the difference between voltage drop on the left and right resistances Rog, i.e. Voscomy= Vauxi)— Vauxey. For Ipacc.ry= 0, Vauxcir) are solely determined by DC bias currents of Ms, and are equals.
Fig. 10. Offset trimming setup for Vosicw(T) temperature-compensated active load current mirror adjustment method, based on the folded cascode.
Fig. 10. Offset trimming setup for Vosicw(T) temperature-compensated active load current mirror adjustment method, based on the folded cascode.
Tail offset voltage trimming is usually implemented by a programmable series resistive network shown in Fig. /2, or by a laser adjustable resistance [15]. The resistive network shown in Fig. 12 is composed of small elements Ros and is biased by the current source Jo. Current mirror voltage Vy is connected to one or more junctions of adjacent resistors via analog switches SWx. The offset trimming is typically driven by a binary, or a bi-directional thermometric search algorithm represented by a trimming sequences example in Fig. /3. Fig. 12. Tail offset voltage generation implemented by series resistances segments Ros and analog multiplexer SW, [15]. Capacitor Cran can be added to increase degenerated gman) at higher frequencies .
Tail offset voltage trimming is usually implemented by a programmable series resistive network shown in Fig. /2, or by a laser adjustable resistance [15]. The resistive network shown in Fig. 12 is composed of small elements Ros and is biased by the current source Jo. Current mirror voltage Vy is connected to one or more junctions of adjacent resistors via analog switches SWx. The offset trimming is typically driven by a binary, or a bi-directional thermometric search algorithm represented by a trimming sequences example in Fig. /3. Fig. 12. Tail offset voltage generation implemented by series resistances segments Ros and analog multiplexer SW, [15]. Capacitor Cran can be added to increase degenerated gman) at higher frequencies .
Fig. 13. Comparison of the trimming sequences of a) binary search and 5) bi-directional thermometric search algorithm. “1” and “0”, correspond to the conducting and non-conducting switches SWx. The difference between both methods is that for the binary algorithm, both Vauxc_p) are simultaneously added to the terminals S_.z), whereas for bi-directional thermometric search, only one of Vauxt) or Vauxcr) is added between Vem and one of the source terminal Sip), depending on Vos polarity. While the resistance between Si) and S,ry remains independent on the trimming code for binary search, gman) is lower, but constant over the trimming range. Trimming by bi- directional thermometric search algorithm improves the transconductance for small offset correction, but decreases gman) for larger corrections. Additionally, the bi-directional thermometric search improves the common-mode range for moderate offset correction by reducing the drop between Scr) and Vem. For extreme cases where only SWo or SW, are conducting, both methods yield the same results (see Fig. 13).
Fig. 13. Comparison of the trimming sequences of a) binary search and 5) bi-directional thermometric search algorithm. “1” and “0”, correspond to the conducting and non-conducting switches SWx. The difference between both methods is that for the binary algorithm, both Vauxc_p) are simultaneously added to the terminals S_.z), whereas for bi-directional thermometric search, only one of Vauxt) or Vauxcr) is added between Vem and one of the source terminal Sip), depending on Vos polarity. While the resistance between Si) and S,ry remains independent on the trimming code for binary search, gman) is lower, but constant over the trimming range. Trimming by bi- directional thermometric search algorithm improves the transconductance for small offset correction, but decreases gman) for larger corrections. Additionally, the bi-directional thermometric search improves the common-mode range for moderate offset correction by reducing the drop between Scr) and Vem. For extreme cases where only SWo or SW, are conducting, both methods yield the same results (see Fig. 13).
Fig. 14. Implementation of the constant resistance tail offset voltage generator. The OTA bias current J is a) split into two //2 current sources which improves the dynamic range, or b) is connected to spit Ros, reducing additional offset originating from the mismatch of 2/) current sources from Fig. a). Capacitor Cran can be added to improve gman) at higher frequencies.
Fig. 14. Implementation of the constant resistance tail offset voltage generator. The OTA bias current J is a) split into two //2 current sources which improves the dynamic range, or b) is connected to spit Ros, reducing additional offset originating from the mismatch of 2/) current sources from Fig. a). Capacitor Cran can be added to improve gman) at higher frequencies.
The requirements of the voltage source low output resistance limit the application scale to, for example, voltage sources realized by an voltage feedback operational amplifier, or to applications in power electronics, where a small offset current does not alter the measured value. Fig.16. Compensation by gate shunt resistor and current source ,uxq).
The requirements of the voltage source low output resistance limit the application scale to, for example, voltage sources realized by an voltage feedback operational amplifier, or to applications in power electronics, where a small offset current does not alter the measured value. Fig.16. Compensation by gate shunt resistor and current source ,uxq).
Fig. 17. a) Transconductances of PMOS transistor with various source resistance Rp, and NMOS transconductance gmn, 5) Zmn/Zmp ratio for various Rp, corresponding to the gain AVrycw/AVin. Simulation parameters: Jp = 2.5uA (NMOS and PMOS), W/Ln = 10.m/2um, W/Lp = 200um/1 um. The adjustment of gncmm/gman) temperature stability, achieved via temperature transconductance damping, is demonstrated in Fig. 17. This figure shows a comparison between an NMOS transistor in saturation without series resistance and a PMOS transistor operating in the subthreshold regime with variable source series resistance Rp. It can be observed that the temperature slope of the gmny/gm) term exhibits an increasing tendency as the value of Rp increases. When Rp= 4kQ, temperature compensation of Zmny/Zmr) is achieved, resulting in AVrycmy in (10) being referred to the OTA input terminal with a temperature- constant gain. This is obtained at the cost of an acceptable degradation of gmp for Rp = 0 > 4kQ by —18% at 27°C.
Fig. 17. a) Transconductances of PMOS transistor with various source resistance Rp, and NMOS transconductance gmn, 5) Zmn/Zmp ratio for various Rp, corresponding to the gain AVrycw/AVin. Simulation parameters: Jp = 2.5uA (NMOS and PMOS), W/Ln = 10.m/2um, W/Lp = 200um/1 um. The adjustment of gncmm/gman) temperature stability, achieved via temperature transconductance damping, is demonstrated in Fig. 17. This figure shows a comparison between an NMOS transistor in saturation without series resistance and a PMOS transistor operating in the subthreshold regime with variable source series resistance Rp. It can be observed that the temperature slope of the gmny/gm) term exhibits an increasing tendency as the value of Rp increases. When Rp= 4kQ, temperature compensation of Zmny/Zmr) is achieved, resulting in AVrycmy in (10) being referred to the OTA input terminal with a temperature- constant gain. This is obtained at the cost of an acceptable degradation of gmp for Rp = 0 > 4kQ by —18% at 27°C.
Fig. 18. PMOS Miller OTA allowing temperature transconductance damping of both differential pair and active load. Temperature characteristics of gman) and gacm) are modified by Rp, Rn, respectively, allowing to align with dumped temperature characteristic of Jos(T) current source. Fig. 18. shows a Miller OTA that is configured for trimming through the temperature-compensated current injection method. In order to minimize the trimming current from Jpaci..r), a source resistance Ros = 5kQ of Mra, was utilized (Fig. 7). However, as mentioned earlier, this value alters the temperature characteristic of Jos(T).
Fig. 18. PMOS Miller OTA allowing temperature transconductance damping of both differential pair and active load. Temperature characteristics of gman) and gacm) are modified by Rp, Rn, respectively, allowing to align with dumped temperature characteristic of Jos(T) current source. Fig. 18. shows a Miller OTA that is configured for trimming through the temperature-compensated current injection method. In order to minimize the trimming current from Jpaci..r), a source resistance Ros = 5kQ of Mra, was utilized (Fig. 7). However, as mentioned earlier, this value alters the temperature characteristic of Jos(T).
Tab. 1. Comparison of the methods presented in this paper. * - require either accurate Ros or Ros identical to the resistance used in bandgap to generate Tgux or Ipac. This allows to ensure temperature stability of Vaux.
Tab. 1. Comparison of the methods presented in this paper. * - require either accurate Ros or Ros identical to the resistance used in bandgap to generate Tgux or Ipac. This allows to ensure temperature stability of Vaux.
The improvement of the temperature drift is demonstrated for this particular case by using the Miller OTA from Fig. /8, implemented without trimming circuit and with identical transistor sizes and bias current as the example from Fig. 17. In Fig. 17, temperature stability is achieved for single transistors with Rp = 4kQ and Rn = 0. By incorporating these values into the OTA from Fig. /8, the temperature drift of Vos can be reduced by more than 50%. This improvement is demonstrated in Fig. 20, comparing the statistical distribution of the temperature drift averaged over 40°C to +120°C temperature range. Fig. 20. Comparison of the temperature drift of the uncompensated OTA from Fig. /8. Improvement is achieved by adding 2 x 4Rp=4kQ, corresponding to the results presented in Fig. 17 inset.
The improvement of the temperature drift is demonstrated for this particular case by using the Miller OTA from Fig. /8, implemented without trimming circuit and with identical transistor sizes and bias current as the example from Fig. 17. In Fig. 17, temperature stability is achieved for single transistors with Rp = 4kQ and Rn = 0. By incorporating these values into the OTA from Fig. /8, the temperature drift of Vos can be reduced by more than 50%. This improvement is demonstrated in Fig. 20, comparing the statistical distribution of the temperature drift averaged over 40°C to +120°C temperature range. Fig. 20. Comparison of the temperature drift of the uncompensated OTA from Fig. /8. Improvement is achieved by adding 2 x 4Rp=4kQ, corresponding to the results presented in Fig. 17 inset.
Fig.19. Example of the performances obtained with Fig. 18 OTA and temperature compensated current injection from Fig. 7 with increased Ros. OTA was implemented with W/Li,2 = 160p.m/1pm, W/L3,4,our = 20.m/2um, Ip = 30pA, and Jger = SpA. In order to align the modified characteristic of Jos(T) with the temperature characteristic of the differential pair and active load, resistances Rp = 2kQ and Rn = 2kQ were employed in the OTA from Fig. 78. It is worth noting that reducing the transconductance of the differential pair increases the range of Vos (10). However, this degradation is compensated through the trimming process. Fig. 19 shows an example of simulated performances based on the temperature transconductance damping with similar results as shown in the original characteristic from Fig. 8. However, the maximal magnitude of Jpacct.ry was reduced from 17pA to 2uA.
Fig.19. Example of the performances obtained with Fig. 18 OTA and temperature compensated current injection from Fig. 7 with increased Ros. OTA was implemented with W/Li,2 = 160p.m/1pm, W/L3,4,our = 20.m/2um, Ip = 30pA, and Jger = SpA. In order to align the modified characteristic of Jos(T) with the temperature characteristic of the differential pair and active load, resistances Rp = 2kQ and Rn = 2kQ were employed in the OTA from Fig. 78. It is worth noting that reducing the transconductance of the differential pair increases the range of Vos (10). However, this degradation is compensated through the trimming process. Fig. 19 shows an example of simulated performances based on the temperature transconductance damping with similar results as shown in the original characteristic from Fig. 8. However, the maximal magnitude of Jpacct.ry was reduced from 17pA to 2uA.
Related topics:
CMOS Integrated Circuit DesignOperational Amplifiers
580 California St., Suite 400
San Francisco, CA, 94104
© 2025 Academia. All rights reserved