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Figure 3. Decade counter connected with 555 timer triggering outputs, while pin 5 was chosen to act as a reset signal and connected to the reset input itself. This 3-5-7 combination introduces a delay in between the trigger signals, which will be very useful in achieving a pure sine wave output later on in the circuit. It is the main part of our circuit that would convert DC into AC. An H-bridge inverter consists of four switching devices (BJT in this case) connected in the form of an H bridge. The two clock pulses from 4017-decade counter will control the switching of BJTs connected in the H-bridge. The circuit of H-bridge is shown in Figure 4.

Figure 3 Decade counter connected with 555 timer triggering outputs, while pin 5 was chosen to act as a reset signal and connected to the reset input itself. This 3-5-7 combination introduces a delay in between the trigger signals, which will be very useful in achieving a pure sine wave output later on in the circuit. It is the main part of our circuit that would convert DC into AC. An H-bridge inverter consists of four switching devices (BJT in this case) connected in the form of an H bridge. The two clock pulses from 4017-decade counter will control the switching of BJTs connected in the H-bridge. The circuit of H-bridge is shown in Figure 4.

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Figure 1. Block diagram of proposed circuit function is discussed in details below. Pure Sine inverter may be a series of modular design and must be able to work together with competitive efficiency, cost, ease of implementation and use. The 555-timer stage is responsible for generating the required clock pulse needed for the entire circuit. The clock pulse frequency should be higher than the frequency of outputs required because we will also use 4017-decade counter in the next stage. The pulse frequency of the clock is controlled through the resistor and capacitor values that will be connected with the timer. In order to produce a square wave of desired frequency the timer 555 is used in astable mode in this circuit. The 555-timer section of the circuit is shown in Figure 2.
Figure 1. Block diagram of proposed circuit function is discussed in details below. Pure Sine inverter may be a series of modular design and must be able to work together with competitive efficiency, cost, ease of implementation and use. The 555-timer stage is responsible for generating the required clock pulse needed for the entire circuit. The clock pulse frequency should be higher than the frequency of outputs required because we will also use 4017-decade counter in the next stage. The pulse frequency of the clock is controlled through the resistor and capacitor values that will be connected with the timer. In order to produce a square wave of desired frequency the timer 555 is used in astable mode in this circuit. The 555-timer section of the circuit is shown in Figure 2.
Figure 2. 555-timer connected in Astabe mode Figure 4. H-bridge circuit The frequency of the output square wave can be found by using the formula given below 4017-decade counter is a decimal counter that can count from 0 to 9. It has ten output pins that goes high one after another. It also has a clock input which determines the frequency of count pulses. The purpose of using 4017-decade counter in this paper is to get two separate clock pulses with a delay between them from a single clock pulse coming from 555 timer. The 4017-decade counter connected with 555 timer is shown in Figure 3. Pins 3 and 7 were chosen to act as
Figure 2. 555-timer connected in Astabe mode Figure 4. H-bridge circuit The frequency of the output square wave can be found by using the formula given below 4017-decade counter is a decimal counter that can count from 0 to 9. It has ten output pins that goes high one after another. It also has a clock input which determines the frequency of count pulses. The purpose of using 4017-decade counter in this paper is to get two separate clock pulses with a delay between them from a single clock pulse coming from 555 timer. The 4017-decade counter connected with 555 timer is shown in Figure 3. Pins 3 and 7 were chosen to act as
The clock pulse coming from pin3 of 4017-decade counter is given to the common point of Q2 and Q5. The clock pulse coming from pin7 is given to the common point of Q3 and Q4. As there is delay between the two clock pulses hence the two pairs of transistors are switched on one after another for equal half interval of time. This creates an AC signal with an average value of zero that resembles a square wave, which makes the signal much easier to filter and turn into a pure sine wave signal.
The clock pulse coming from pin3 of 4017-decade counter is given to the common point of Q2 and Q5. The clock pulse coming from pin7 is given to the common point of Q3 and Q4. As there is delay between the two clock pulses hence the two pairs of transistors are switched on one after another for equal half interval of time. This creates an AC signal with an average value of zero that resembles a square wave, which makes the signal much easier to filter and turn into a pure sine wave signal.
The square wave coming from H-bridge contains a large amount of harmonics that needs to be filtered out. For this purpose, we use filter connected in series with the H-bridge inverter. The filter stage was chosen to be a passive filter because an active filter would involve the use of op-amps, consuming more power and lowering efficiency. Since the H- bridge circuit has a two-ended output, the 4th order low pass filter consisted of 8 resistors and 4 capacitors. The transfer function of this complicated of a circuit is very difficult to calculate, so the values of the components were found through trial and error by seeing which combination produced the best output signal. The circuit of filter stage is shown in Figure 5. The last stage of our circuit is the transformer stage. The peak value of the voltage at the at the filter output is very low. In order to step up it to the required value we need to connect a step-up transformer. Hence the output coming from the filter is given to a step-up transformer.
The square wave coming from H-bridge contains a large amount of harmonics that needs to be filtered out. For this purpose, we use filter connected in series with the H-bridge inverter. The filter stage was chosen to be a passive filter because an active filter would involve the use of op-amps, consuming more power and lowering efficiency. Since the H- bridge circuit has a two-ended output, the 4th order low pass filter consisted of 8 resistors and 4 capacitors. The transfer function of this complicated of a circuit is very difficult to calculate, so the values of the components were found through trial and error by seeing which combination produced the best output signal. The circuit of filter stage is shown in Figure 5. The last stage of our circuit is the transformer stage. The peak value of the voltage at the at the filter output is very low. In order to step up it to the required value we need to connect a step-up transformer. Hence the output coming from the filter is given to a step-up transformer.
Figure 6. Complete circuit diagram The simulation results of different stages are given below. Figure 7 shows a clock pulse of frequency 250Hz. Figure 8 shows two similar waveforms each of frequency 25Hz. Figure 9 shows a square waveform of frequency 50Hz containing harmonics. Finally, in Figure 10 a pure sin wave of frequency 50Hz is shown after filtration and voltage rise through transformer of ratio 1:861 to produce a voltage of 220V RMS.
Figure 6. Complete circuit diagram The simulation results of different stages are given below. Figure 7 shows a clock pulse of frequency 250Hz. Figure 8 shows two similar waveforms each of frequency 25Hz. Figure 9 shows a square waveform of frequency 50Hz containing harmonics. Finally, in Figure 10 a pure sin wave of frequency 50Hz is shown after filtration and voltage rise through transformer of ratio 1:861 to produce a voltage of 220V RMS.
Figure 7. Simulation result of 555 timer stage
Figure 7. Simulation result of 555 timer stage
Figure 8. Simulation result of Decade counter
Figure 8. Simulation result of Decade counter
Figure 9. Simulation result of H-bridge cicuit
Figure 9. Simulation result of H-bridge cicuit
Figure 10. Final waveform
Figure 10. Final waveform
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EngineeringElectrical EngineeringPhysicsSine Wave
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