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Title
Abstract
Introduction
Previous and Related Work
Previous Work
Related Work
NTP Server Core Overview
Results and Discussion
Implementation Results
Conclusions
References
All Topics
Computer Science
Hardware and Architecture

High-Performance Time Server Core for FPGA System-on-Chip

Profile image of Manuel J. BellidoManuel J. Bellido

2019, Electronics

https://doi.org/10.3390/ELECTRONICS8050528
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28 pages

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Abstract

This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core for field programmable gate arrays. The core uses a carefully designed modular architecture, which is fully implemented in hardware using digital circuits and systems. Most remarkable novelties introduced are a hardware-optimized timekeeping algorithm implementation, and a full-hardware protocol stack and automatic network configuration. As a result, the core is able to achieve similar accuracy and performance to typical high-performance network time protocol server equipment. The core uses a standard global positioning system receiver as time reference, has a small footprint and can easily fit in a low-range field-programmable chip, greatly scaling down from previous system-on-chip time synchronization systems. Accuracy and performance results show that the core can serve hundreds of thousands of network time clients with negligible accuracy degradation, in con...

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