On the hardware design of an elliptic curve cryptosystem

ijser.org

An explosi ve acceptance of Elliptic Curve Cryptography (ECC) has been attained in the industry and academics. Elliptic Curve cryptography i s an approach to public-key cryptography based on the algebrai c structure of elliptic curves over finite fields. The ECC is advantageous due to the provision of high level of security and the usage of small keys. In the field of Mobile, Wireless and Network servers, to sustain the high throughput the implementations of high speed crypto-systems are needed. ECC has been extensivel y used for hardware implementation of FPGA and DedicatedASIC. This paper attempts to conduct a detailed survey on di fferent techniques for implementing FPGA using ECC to achieve high speed and flexibility.

Journal of Systems and Software, 2004

trations (E-Government) give rise to the important question, how to reliably exchange confidential data via public communication networks such as the Internet. Any data transfer must be protected from a fraudulent access by third parties in the sense that it has to be ensured that exchanged documents are neither read nor modified during the data transfer. Furthermore, the author-document relationships have to be known and unique at any point in time. The fundamental technology for document protection during public data transfer is known as public key cryptography. Digital signature schemes are probably the most common occurrence of public key cryptosystems. This paper addresses public key cryptosystems based on elliptic curves, which are aimed to high-performance digital signature schemes. Elliptic curve (EC) algorithms are characterized by the fact that one can work with considerably shorter keys compared to the RSA approach at the same level of security. A general and highly efficient method for mapping the most time-critical operations to a configurable co-processor is proposed. By means of real-time measurements the resulting performance values are compared to previously published state of the art hardware im-

2004

This paper describes a hardware implementation of an arithmetic processor which is efficient for elliptic curve (EC) cryptosystems, which are becoming increasingly popular as an alternative for public key cryptosystems based on factoring. The modular multiplication is implemented using a Montgomery modular multiplication in a systolic array architecture, which has the advantage that the clock frequency becomes independent of the bit length m.

2011

The rapid advances in communication networks impose the fact of transferring big amounts of information worldwide every second. Considerable part of this information might need protection against fraud, modification and different types of intrusion. Both, the symmetric and asymmetric encryption algorithms provide different types of security services to protect sensitive information. Lately, the National Institute of Standards and Technology issued Federal Information Processing Standards to direct the researcher’s attention to the asymmetric cryptographic algorithms based on elliptic curves. In this paper, algorithms and design issues related to two new curves: Doubling Oriented, and Jacobi-Quartics, are proposed and analyzed. Then, different implementation approaches are studied and applied for the different curves. Experimental results are provided to show the enhancements on the execution delay and the total design area of the proposed FPGA realizations.

Information Technology Journal, 2009

This paper presents a survey of hardware/software co-design implementations of elliptic curve cryptosystems. A critical study of the underlying finite field, the representation basis, and the partitioning schemes of these implementations is conducted. The study shows that all implementations are implemented over binary fields GF(2 m ) and the implementations that use polynomial basis are more than implementations that use normal basis for finite field arithmetic. The study also shows that the best partitioning scheme, among the surveyed implementations,

International Journal of Network Security & Its Applications, 2010

In this paper, we propose an elliptic curve key generation processor over GF scheme based on the Montgomery scalar multiplication algorithm. The new architecture is performed using polynomial basis. The Finite Field operations use a cellular automata multiplier and Fermat algorithm for inversion. For real time implementation, the architecture has been tested on an ISE 9.1 Software using Xilinx Virtex II Pro FPGA and on an ASIC CMOS 45 nm technology as well. The proposed implementation provides a time of 2.07 ms and 38 percent of Slices in Xilinx Virtex II Pro FPGA. Such features reveal the high efficiently of this implementation design.

Journal of Sensor and Actuator Networks

Cryptography is considered indispensable among security measures applied to data concerning insecure means of transmission. Among various existent algorithms on asymmetric cryptography, we may cite Elliptic Curve Cryptography (ECC), which has been widely used due to its security level and reduced key sizes. When compared to Rivest, Shamir and Adleman (RSA), for example, ECC can maintain security levels with a shorter key. Elliptic Curve Point Multiplication (ECPM) is the main function in ECC, and is the component with the highest hardware cost. Lots of ECPM implementations have been applied on hardware targeting the acceleration of its calculus. This article presents a systematic review of literature on ECPM implementations on both Field-Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC). The obtained results show which methods and technologies have been used to implement ECPM on hardware and present some findings of the choices available to the hardwa...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002

The implementation of a microcoded elliptic curve processor using field-programmable gate array technology is described. This processor implements optimal normal basis field operations in 2. The design is synthesized by a parameterized module generator, which can accommodate arbitrary and also produce field multipliers with different speed/area tradeoffs. The control part of the processor is microcoded, enabling curve operations to be incorporated into the processor and hence reducing the chip's I/O requirements. The microcoded approach also facilitates rapid development and algorithmic optimization: for example, projective and affine coordinates were supported using different microcode. The design was successfully tested on a Xilinx Virtex XCV1000-6 device and could perform an elliptic curve multiplication over the field 2 using affine and projective coordinates for = 113 155 and 173.

Elliptic Curve Discrete Logarithm (ECDL) are most popular choice Elliptic Curve Cryptography (ECC),which gives provision for shorter key lengths as compared to as compared to its counterpart public key cryptosystems, and it can be used for security in embedded systems,wirless communications and personal communication systems. In this paper Elliptic Curve Discrete Logarithm code has been written in Verilog Hardware Description Language (HDL) and implemented on Xilinx Spartan3E Field Programmable Gate Array (FPGA),has taken 403 encoders, decoders with minimum period of 5.043 ns,maximum frequency 198.295 MHz and with a total memory usage of 269824 Kilobytes respectively. The performance of the crypto system is much faster than the software implementation of the same system. Keywords: Elliptic Curve Discrete Logarithm (ECDL),VerilogHardware Description Language (HDL), Elliptic Curve Cryptography (ECC),Field Programmable Gate Array (FPGA),Finite Fields.

IEEE Access

Along with the rapid development in security technology, the efficient implementation of a large field-size elliptic curve cryptosystem (ECC) is becoming demanding in many critical applications as small-sized cryptosystems are gradually becoming obsolete. Based on this consideration, this paper proposes a series of novel coherent interdependence efforts to propose a novel implementation of ECC hardware cryptoprocessor: (i) We firstly propose a new Montgomery point multiplication (PM) algorithm to optimize and balance the signal flow and resource utilization efficiency; (ii) Then, we have efficiently constructed a new ECC processor over GF (2 m) (with the support of a series of algorithm-architecture coimplementation techniques); (iii) Finally, we have given detailed comparison and performance analysis to show that the proposed cryptographic processor has superior performance than the competing designs, i.e., smaller area-delay product (ADP) than the competing designs. The proposed large field-size ECC processor (and the proposed design strategy) can be extended and applied in many security-demanding applications. INDEX TERMS Elliptic curve cryptography, FPGA, hardware design, large field-size, low-complexity, point multiplication.