CLASSIC: A cortex-inspired hardware accelerator

Frontiers in neuroscience, 2018

Embedded, continual learning for autonomous and adaptive behavior is a key application of neuromorphic hardware. However, neuromorphic implementations of embedded learning at large scales that are both flexible and efficient have been hindered by a lack of a suitable algorithmic framework. As a result, most neuromorphic hardware are trained off-line on large clusters of dedicated processors or GPUs and transferred to the device. We address this by introducing the neural and synaptic array transceiver (NSAT), a neuromorphic computational framework facilitating flexible and efficient embedded learning by matching algorithmic requirements and neural and synaptic dynamics. NSAT supports event-driven supervised, unsupervised and reinforcement learning algorithms including deep learning. We demonstrate the NSAT in a wide range of tasks, including the simulation of Mihalas-Niebur neuron, dynamic neural fields, event-driven random back-propagation for event-based deep learning, event-based ...

2020

Traditional von Neumann architecture based processors become inefficient in terms of energy and throughput as they involve separate processing and memory units, also known as~\textit{memory wall}. The memory wall problem is further exacerbated when massive parallelism and frequent data movement are required between processing and memory units for real-time implementation of artificial neural network (ANN) that enables many intelligent applications. One of the most promising approach to address the memory wall problem is to carry out computations inside the memory core itself that enhances the memory bandwidth and energy efficiency for extensive computations. This paper presents an in-memory computing architecture for ANN enabling artificial intelligence (AI) and machine learning (ML) applications. The proposed architecture utilizes deep in-memory architecture based on standard six transistor (6T) static random access memory (SRAM) core for the implementation of a multi-layered perce...

Nature Machine Intelligence

In spite of intensive efforts it has remained an open problem to what extent current Artificial Intelligence (AI) methods that employ Deep Neural Networks (DNNs) can be implemented more energy-efficiently on spike-based neuromorphic hardware. This holds in particular for AI methods that solve sequence processing tasks, a primary application target for spike-based neuromorphic hardware. One difficulty is that DNNs for such tasks typically employ Long Short-Term Memory (LSTM) units. Yet an efficient emulation of these units in spike-based hardware has been missing. We present a biologically inspired solution that solves this problem. This solution enables us to implement a major class of DNNs for sequence processing tasks such as time series classification and question answering with substantial energy savings on neuromorphic hardware. In fact, the Relational Network for reasoning about relations between objects that we use for question answering is the first example of a large DNN that carries out a sequence processing task with substantial energy-saving on neuromorphic hardware. Energy consumption is a major impediment for more widespread applications of new AI-methods that use DNNs, especially in edge devices. Spike-based neuromorphic hardware is one direction that promises to alleviate this problem. This research direction is partially motivated by the method that brains use to run even more complex and larger neural networks than those DNNs that are used in current AI, with a total energy consumption of just 20W: Neurons in the brain only rarely emit spikes which mostly triggers energy consumption in neurons and synapses. But it has remained an open problem as to how DNNs that are needed for modern AI solutions could be implemented in neuromorphic hardware in such a sparse firing mode. Another open problem is how the LSTM units of such DNNs, that are needed for providing a working memory for sequence processing tasks, could be implemented in spike-based neuromorphic hardware. We present a biologically inspired solution to the second problem, that simultaneously provides a step towards also solving the first problem, since it reduces the firing activity of neurons that hold working memory content. We combine this method with a brain-inspired technique called membrane voltage regularization for enforcing sparse firing activity during the training of the DNN. We have tested the impact of these two innovations on computational performance and energy consumption for two benchmark tasks in an implementation on a representative spike-based chip: Intel's neuromorphic research chip Loihi [Davies et al., 2018]. We find significant reductions in the energy-delay product (EDP). In contrast to power, EDP accounts for the true energy and time cost per task/workload/computation. Simultaneously, these implementations demonstrate that two hallmarks of cognitive computations, both in brains and in machine intelligence, working memory and reasoning about relations between concepts or objects, can in fact be implemented more efficiently in spike-based neuromorphic hardware than in GPUs, the standard computing hardware for implementing DNNs. Implementing a long short-term memory in spike-based neuromorphic hardware Working memory is maintained in an LSTM unit in a special memory cell, to which read-and write-access is gated by trained neurons with sigmoidal activation function [Hochreiter and Schmidhuber, 1997]. Such an LSTM unit is difficult to realize efficiently in spike-based hardware. However, it turns out that by simply adding a standard feature of some biological neurons, slow after-hyperpolarizing (AHP) currents, a spiking neural network (SNN) acquires similar working memory capabilities as LSTM units over the time scale of the AHP currents. These AHP currents lower the membrane potential of a neuron after each of its spikes (see Fig. 1). Furthermore, these AHP currents can easily be implemented on Loihi with the desirable side benefit of reducing firing activity, and therefore

2006

The real-time modeling of large systems of spiking neurons is computationally very demanding in terms of processing power, synaptic weight memory requirements and communication throughput. We propose to build a highperformance computer for this purpose with a multicast communications infrastructure inspired by neurobiology. The core component will be a chip multiprocessor incorporating some tens of small embedded processors, interconnected by an NoC that carries spike events between processors on the same or different chips. The design emphasizes modeling flexibility, power-efficiency, and fault-tolerance, and is intended to yield a general-purpose platform for the real-time simulation of largescale spiking neural systems.

IEEE Micro

Loihi is a 60-mm 2 chip fabricated in Intel's 14-nm process that advances the state-of-the-art modeling of spiking neural networks in silicon. It integrates a wide range of novel features for the field, such as hierarchical connectivity, dendritic compartments, synaptic delays, and, most importantly, programmable synaptic learning rules. Running a spiking convolutional form of the Locally Competitive Algorithm, Loihi can solve LASSO optimization problems with over three orders of magnitude superior energy-delay product compared to conventional solvers running on a CPU isoprocess/voltage/area. This provides an unambiguous example of spike-based computation, outperforming all known conventional solutions. Neuroscience offers a bountiful source of inspiration for novel hardware architectures and algorithms. Through their complex interactions at large scales, biological neurons exhibit an impressive range of behaviors and properties that we currently struggle to model with modern analytical tools, let alone replicate with our design and manufacturing technology. Some of the magic that we see in the brain undoubtedly stems from exotic device and material properties that will remain out of our fabs' reach for

2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2020

Although artificial Spiking Neural Networks provide numerous advantages versus the traditional non spiking ones, their high complexity is limiting the use to server computers or dedicated ASIC implementations. As an alternative, the recently proposed Spike-by-Spike (SbS) Neural Networks provide reduced complexity while adding noise-robustness. In this work we propose an accelerator framework for inference and incremental learning targeting resource-constrained devices. The proposed architecture automatically distributes computational tasks to multiple accelerator units. This is the first SbS neural network implementation for embedded systems. Demonstration on a Xilinx Zynq-7020 achieves 99% of accuracy on MNIST dataset classification and a 5x latency enhancement compared to a Core-i7 computer running equivalent network topologies. To facilitate the research in this domain, the entire SbS accelerator framework is available as an open-source project.

2017

Memristors promise higher device density and design flexibility. Besides utilizing memristors for digital memory, another promising avenue for adoption is the advancement of neural network circuits capable of learning. Neural network implementations with memristors have been proposed, including memristor synaptic training methodologies. This work highlights applications of a neural learning methodology inspired by Q-learning. Memristors are used as analog storage elements to store a large Q-table. The method is qualified with a maze problem in order to show that the proposed network can be used to learn to approximate an optimal path to solving the maze problem. Brief results highlighting the methodology on a maze problem and discussion on generating random keys are provided. This work combines model-free reinforcement learning with neural networks.

2023

Neural networks have been commonly used in different domains. Hardware implementation of the neural networks is challenging to fit different applications' requirements. This often necessitates realizing different neural network FPGA configurations from the very scratch specific to a given application. This paper proposes a flexible method that can be reconfigured in a self-supervised way to fit several applications' requirements, by providing only maximum available computational nodes a prior. The proposed method is based on reconfiguring the required number of hidden layers and hidden nodes of that layer based on a given application. Reconfigurability also allows to decide and update the number of active nodes, at layer (l +1), which receives computational results of l th layer nodes. A configuration block is used to send a signal to the control block which follows each node output. The control block decides which following nodes receive the output according to the corresponding signal value from the configuration block. Each node receives a signal to be enabled or disabled from the configuration block. Therefore, the number of inputs of each node and nodes in each layer is determined according to the desired performance. The goal here is to automatically propose the optimal NN configuration through reconfigurability to fit different applications, to achieve the maximum accuracy possible. The optimality can be demonstrated in terms of minimum average power, average delay, and area overhead as well as maximum throughput and accuracy. The main advantage of the proposed approach is the reusability of the optimized architecture (which is self-learned online) for the very first application/dataset, as the initial configuration for any new/next dataset/application rather than starting from scratch. We have demonstrated with experimental results, the proposed approach helps primarily to significantly reduce optimized architecture search cost (the number of online training iterations) as well as associated average power consumption for successive datasets/applications. Our proposed method demonstrates its effectiveness both quantitatively and qualitatively. The proposed method is verified against two different classification problems, MNIST and CIFAR-10. Our proposed reconfigurable method demonstrates stable accuracy of 98.97% and 98.95% against the state-of-the-art neural network with two different fixed configurations as (98.85% and 73.0%) for MNIST and (93.47% and 70.21%) for CIFAR-10, respectively. The proposed method also demonstrates a 20.9% reduction in average power dissipation against the state-of-the-art method. The proposed method is implemented and tested using VHDL and Altera FPGA. The results show resource utilization is comparable with the state-of-the-art method. INDEX TERMS Artificial Neural Network, Reconfiguration, FPGA, Hardware Accelerator. I. INTRODUCTION T HE digital design of an Artificial Neural Networks (ANNs) and its complex variants are inspired from the study of neuroscience and human brain, considered to be the epitome of intelligence. Countless research and efforts are involved, over past few decades, to understand, model and map the algorithms, architectures, functions and representations of the biological brain to digital circuit design [1], [2]. There

2013

A Chip Multiprocessor for a Large-scale Neural SimulatorEustace PainkrasA thesis submitted to The University of Manchesterfor the degree of Doctor of Philosophy, 17 December 2012The modelling and simulation of large-scale spiking neural networks in biologicalreal-time places very high demands on computational processing capabilities andcommunications infrastructure. These demands are difficult to satisfy even with powerfulgeneral-purpose high-performance computers. Taking advantage of the remarkableprogress in semiconductor technologies it is now possible to design and buildan application-driven platform to support large-scale spiking neural network simulations.This research investigates the design and implementation of a power-efficientchip multiprocessor (CMP) which constitutes the basic building block of a spikingneural network modelling and simulation platform. The neural modelling requirementsof many processing elements, high-fanout communications and local memoryare addressed ...

IEEE Transactions on Computers

Neuromorphic systems that learn and predict from streaming inputs hold significant promise in pervasive edge computing and its applications. In this paper, a neuromorphic system that processes spatio-temporal information on the edge is proposed. Algorithmically, the system is based on hierarchical temporal memory that inherently offers online learning, resiliency, and fault tolerance. Architecturally, it is a full custom mixed-signal design with an underlying digital communication scheme and analog computational modules. Therefore, the proposed system features reconfigurability, real-time processing, low power consumption, and low-latency processing. The proposed architecture is benchmarked to predict on real-world streaming data. The network's mean absolute percentage error on the mixed-signal system is 1.129X lower compared to its baseline algorithm model. This reduction can be attributed to device non-idealities and probabilistic formation of synaptic connections. We demonstrate that the combined effect of Hebbian learning and network sparsity also plays a major role in extending the overall network lifespan. We also illustrate that the system offers 3.46X reduction in latency and 77.02X reduction in power consumption when compared to a custom CMOS digital design implemented at the same technology node. By employing specific low power techniques, such as clock gating, we observe 161.37X reduction in power consumption.