TAM: A Front-End to an Auto-Parallelizing Compiler

The procedure of parallelising a sequential task can be very difficult and even with considerable experience in the area of parallelisation, it can still be quite monotonous. Automation of parallelisation through using a parallelising compiler is often an advantageous path to pursue due to the savings in both time and effort. A major component of automatic parallelisation is loop parallelisation. This report discusses the methods used in enhancing the simple parallelising compiler to take advantage of loop parallelisation. Our simple parallelising compiler has been designed to exploit any chosen execution environment to its fullest; currently the RHODOS distributed system is being used. RHODOS provides both a distributed operating system with parallel process management control as well as a suite of parallel execution library calls, that can be used to manipulate the various components of parallel programs. The combination of loop parallelisation and the RHODOS distributed system have proved to be a positive combination.

The process of writing parallel programs is not as simple or common as traditional sequential programming. A programmer must have an in-depth knowledge of the program at hand, as well as the resources available when the program is executed. By designing a compiler that can automatically parallelise sequentially written programs, is obviously of great benefit. The current efforts concentrate mainly on fine grained parallelism. With the move towards using clusters of workstations as platforms for parallel processing, coarse grained parallelism is becoming a very important research issue. This paper reports on the development of a simple parallelising compiler exploiting course grained parallelism in sequential programs. In particular, the use of three structured algorithms used to divide the parallelisation process into manageable phases is presented.

Journal of Research and Practice in Information Technology - ACJ, 1995

We present the linear loop transformation framework which is the formal basisfor state of the art optimization techniques in restructuring compilers for parallelmachines. The framework unifies most existing transformations and provides asystematic set of code generation techniques for arbitrary compound loop transformations.The algebraic representation of the loop structure and its transformationgive way to quantitative techniques for optimizing performance on parallelmachines. We discuss ...

Instruction Level Parallelism (ILP) is not the new idea. Unfortunately ILP architecture not well suited to for all conventional high level language compilers and compiles optimization technique. Instruction Level Parallelism is the technique that allows a sequence of instructions derived from a sequential program (without rewriting) to be parallelized for its execution on multiple pipelining functional units. As a result, the performance is increased while working with current softwares. At implicit level it initiates by modifying the compiler and at explicit level it is done by exploiting the parallelism available with the hardware. To achieve high degree of instruction level parallelism, it is necessary to analyze and evaluate the technique of speculative execution control dependence analysis and to follow multiple flows of control. The researchers are continuously discovering the ways to increase parallelism by an order of magnitude beyond the current approaches. In this paper we present impact of control flow support on highly parallel architecture with 2- core and 4-core. We also investigated the scope of parallelism explicitly and implicitly. For our experiments we used trimaran simulator. The benchmarks are tested on abstract machine models created through trimaran simulator.

Parallel Architectures and Compilation Techniques, 1994

Multithreaded architectures hold many promises: the exploitation of intra-thread locality and the latency tolerance of multithreaded synchronization can result in a more e cient processor utilization and higher scalability. The challenge for a code generation scheme is to make e ective use of the underlying hardware by generating large threads with a large degree of internal locality without limiting the program level parallelism. Top-down code generation, where threads are created directly from the compiler's intermediate form, is e ective at creating a relatively large thread. However, having only a limited view of the code at any one time limits the thread size. These top-down generated threads can therefore be optimized by global, bottom-up optimization techniques. In this paper, we present such bottom-up optimizations and evaluate their e ectiveness in terms of overall performance and speci c thread characteristics such as size, length, instruction level parallelism, number of inputs and synchronization costs.

2009

Recent advances in polyhedral compilation technology have made it feasible to automatically transform affine sequential loop nests for tiled parallel execution on multi-core processors. However, for multi-statement input programs with statements of different dimensionalities, such as Cholesky or LU decomposition, the parallel tiled code generated by existing automatic parallelization approaches may suffer from significant load imbalance, resulting in poor scalability on multi-core systems. In this paper, we develop a completely automatic parallelization approach for transforming input affine sequential codes into efficient parallel codes that can be executed on a multi-core system in a load-balanced manner. In our approach, we employ a compile-time technique that enables dynamic extraction of inter-tile dependences at run-time, and dynamic scheduling of the parallel tiles on the processor cores for improved scalable execution. Our approach obviates the need for programmer intervention and re-writing of existing algorithms for efficient parallel execution on multi-cores. We demonstrate the usefulness of our approach through comparisons using linear algebra computations: LU and Cholesky decomposition.

In this paper, we propose a compilation tool-chain supporting the effective exploitation of multi-core architectures offering hundreds of cores. The tool-chain leverages on both the application requirements and the platform-specific features to provide developers with a powerful parallel-programming environment able to generate efficient parallel code.

2011

The efficient development of multi-threaded software has, for many years, been an unsolved problem in computer science. Finding a solution to this problem has become urgent with the advent of multi-core processors. Furthermore, the problem has become more complicated because multi-cores are everywhere (desktop, laptop, embedded system). As such, they execute generic programs which exhibit very different characteristics than the scientific applications that have been the focus of parallel computing in the past.

ACM Sigplan …, 1994

Compiler infrastructures that support experimental research are crucial to the advancement of high-performance computing. New compiler technology must be implemented and evaluated in the context of a complete compiler, but developing such an infrastructure requires a huge investment in time and resources. We have spent a number of years building the SUIF compiler into a powerful, flexible system, and we would now like to share the results of our efforts.

… of the 2002 ACM symposium on …, 2002

This paper presents a novel approach for the problem of generating tiled code for nested for-loops using a tiling transformation. Tiling or supernode transformation has been widely used to improve locality in multi-level memory hierarchies as well as to efficiently execute loops onto non-uniform memory access architectures. However, automatic code generation for tiled loops can be a very complex compiler work due to non-rectangular tile shapes and iteration space bounds. Our method considerably enhances previous work on rewriting tiled loops by considering parallelepiped tiles and arbitrary iteration space shapes. The complexity of code generation for tiling transformation is now reduced to the complexity of code generation for any linear transformation. Experimental results which compare all so far presented approaches, show that the proposed approach for generating tiled code is significantly accelerated.