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Outline

Title
Abstract
Chapter 1 Introduction
Background
Worst-Case Execution Time
Literature Review
Cache Analysis
Memory Hierarchy Design Exploration
Worst-Case Optimizations in Other Fields
Worst-Case Execution Time Analysis
Overview
Flow Analysis
Wcet Analysis with Infeasible Path Detection
Discussion
Introduction
Method Overview
Task Analysis
WCRT Analysis
Post-Allocation Analysis
Allocation Methods
Method Scalability
Objective Function
Experimental Evaluation
Chapter Summary
Chapter 9 Conclusion 9.1 Thesis Contributions
References
All Topics
Computer Science
Software

Memory Optimizations for Time-Predictable Embedded Software

Profile image of Phúc HữuPhúc Hữu

2009

Abstract

Real-time constraints place a requirement on systems to accomplish their assigned functionality in a certain timeframe. This requirement is critical for hard real-time applications, such as safety device controllers, where the system behavior in the worst case determines the system feasibility with respect to timing specifications. There is often a need to improve this worst-case performance to realize the system with efficient use of system resources. The rule remains, however, that all impacts of performance enhancement done to the system should not compromise its timing predictability-the property that its performance can be bounded and guaranteed to meet its timing constraints under all possible scenarios. Due to the yet-to-be-resolved gap between the performance of processor and memory technology, memory accesses remain the reigning performance bottleneck of most applications today. Embedded systems generally include fast memory on-chip to speed up execution time. To utilize this resource for optimal performance gain, it is crucial to design a suitable management scheme. Popular approaches targeted at enhancing average-case performance, typically done via profiling, cannot be directly adapted to effectively improve worst-case performance, due to the inherent possibility of worst-case execution path shift. There is thus a need for new approaches specifically targeted at optimizing worst-case performance in a time-predictable manner.

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In this paper we propose a new hardware data cache (FAFB, fully-associative FIFO tagged buffers) to complement the data cache in processors. It provides predictability when exploiting temporal reuse in array data structures, i.e. it allows an accurate WCET analysis, which is required in real-time systems. With our hardware proposal, compiler transformations that exploit such reuse (essentially tiling) can be safely applied. Moreover, our proposal has other features of particular interest to embedded systems, where a set of welltuned applications run in a hardware platform which may be constrained in size, complexity and energy consumption. In order to test the most uncommon features of the FAFBs (predictability and effectiveness with a small size), we perform a worst-case analysis on several kernel algorithms for embedded and real-time computing, showing the interaction between tiling and our hardware architecture. Our results show that the number of data cache misses is reduced between 1.3 and 19 times on such algorithms.

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Thesis advisors Precise and Adaptable Worst-Case Execution Time Estimation in Hard Real-Time Systems
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