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Computer Science
Hardware and Architecture

Accelerating Deep Neural Networks Using FPGA

Profile image of Esraa AdelEsraa Adel

2018, 2018 30th International Conference on Microelectronics (ICM)

Abstract

Deep Convolutional Neural Networks (CNNs) are the state-of-the-art systems for image classification and scene understating. They are widely used for their superior accuracy but at the cost of high computational complexity. The target in this field nowadays is its acceleration to be used in real time applications. The solution is to use Graphics Processing Units (GPU) but many problems arise due to the GPU high-power consumption which prevents its utilization in daily-used equipment. The Field Programmable Gate Array (FPGA) is a new solution for CNN implementations due to its low power consumption and flexible architecture. This work discusses this problem and provides a solution that compromises between the speed of the CNN and the power consumption of the FPGA. This solution depends on two main techniques for speeding up: parallelism of layers resources and pipelining inside some layers

Figures (5)
Fig. 2. Alex-Net neural network architecture. D. Local Response Normalization (LRN)
Fig. 2. Alex-Net neural network architecture. D. Local Response Normalization (LRN)
each PE is responsible for one weight filter operations as discussed before. This parallel structure speeds up the Conv] execution by 96 times (number of filters). This will be further explained in the results sections showing the time reduction resulted from this parallelism.
each PE is responsible for one weight filter operations as discussed before. This parallel structure speeds up the Conv] execution by 96 times (number of filters). This will be further explained in the results sections showing the time reduction resulted from this parallelism.
Convl output are completed, that can produce the first row of Pooll output. For the second row of the Pooll can be executed after the fourth and fifth rows of Conv! are completed. Fig.4 shows the pipelining flow in time. After Pooll generates complete row output, Conv! can over-write its output that would reduce the memory storage for the convolution output to store only four rows.
Convl output are completed, that can produce the first row of Pooll output. For the second row of the Pooll can be executed after the fourth and fifth rows of Conv! are completed. Fig.4 shows the pipelining flow in time. After Pooll generates complete row output, Conv! can over-write its output that would reduce the memory storage for the convolution output to store only four rows.
Afi iyv SIMULATION TIME OF Alex-Net ON DIFFERENT GPUs next step is to compromise between the time required for the image prediction and the number of resources. In addition, some techniques can be used to reduce the power consumption as pruning and partial dynamic reconfiguration (PDR).
Afi iyv SIMULATION TIME OF Alex-Net ON DIFFERENT GPUs next step is to compromise between the time required for the image prediction and the number of resources. In addition, some techniques can be used to reduce the power consumption as pruning and partial dynamic reconfiguration (PDR).

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