An FPGA-Based Implementation of the Pomaranch Stream Cipher

In this paper, the hardware implementations of five representative stream ciphers are compared in terms of performance and consumed area. The ciphers used for the comparison are the A5/1, W7, E0, RC4 and Helix. The first three ones have been used for the security part of wellknown standards. The Helix cipher is a recently introduced fast, word oriented, stream cipher. W7 algorithm has been recently proposed as a more trustworthy solution for GSM, due to the security problems that occurred concerning A5/1 strength. The designs were coded using VHDL language. For the hardware implementation of the designs, an FPGA device was used. The implementation results illustrate the hardware performance of each cipher in terms of throughput-to-area ratio. This ratio equals to: 5.88 for the A5/1, 1.26 for the W7, 0.21 for the E0, 2.45 for the Helix and 0.86 for the RC4.

The number of internet of things (IoT) applications has increased, which has increased the demand for low-resource gadgets. The data produced by these devices must be protected to guarantee security. The devices operate in conditions with limited space, computational power, memory, and energy. High-security standards are difficult to achieve with limited resources. The detailed analysis of various stream ciphers and their performance metrics is reviewed in this manuscript. The functionality of the stream ciphers is categorized and thoroughly discussed based on both the hardware and software viewpoints. The security attacks and their countermeasure methods using stream ciphers are discussed. The performance metrics of most hardware-based stream ciphers, including the ECRYPT stream cipher project (eSTREAM) ciphers, are discussed. Each hardware stream cipher design highlights the hardware constraints such as chip area, frequency, throughput, and hardware efficiency. The work also highlights the various applications using these stream ciphers. The current trends using these stream ciphers are discussed with futuristic goals.

2015

RC4 is a popular stream cipher, which is widely used in many security protocols and standards due to its speed and flexibility. Several hardware implementations were previously suggested in the literature with the goal of improving the performance, area, or both. In this paper, a new hardware implementation of the RC4 algorithm using FPGA is proposed. The main idea of this design is the use of a dual-port block RAM in the FPGA in order to better utilize the available logic and memory resources. Combined with a new pipelined hardware implementation, the new design achieves better performance. The design is described using Verilog HDL and synthesized and implemented using Xilinx ISE suite for different FPGA devices. Synthesis results show that the proposed design achieves higher efficiency than previous implementations by reducing area while maintaining a good throughput/LUT ratio. The proposed design is also more efficient in terms of power consumption. © 2014 The Authors. Published ...

proc. of CCCT

Proceedings Apsipa Asc 2009 Asia Pacific Signal and Information Processing Association 2009 Annual Summit and Conference, 2009

Considering the overall characteristics of ubiquitous environment, a practical solution of ubiquitous security is not to achieve ideally strong strength but to achieve temporary strength without relying on permanent network infrastructure. According to this concept, the authors have exploited a multimedia stream cipher engine. This is a safety aware, high-performed single chip processor. In order to keep security, usability, speed, and power consciousness, the stream cipher engine takes a compact multicore architecture. Each core implements a double cipher scheme that covers RAC (random addressing cryptography) and data sealing. The double cipher is microarchitecture-based, software-transparent hardware cryptography that offers the protection of the whole data with negligible hardware cost and moderate performance overhead. The double cipher increases cipher strength as the expansion of key length or the cycle of random numbers. Although the hardware implementation of longer cycle random number generation is very easy, it surely involves the power consuming increase of the size of a stream buffer or register file. Based on the previous implementation of the stream cipher engine chip by using 0.18-m standard cell CMOS technology, this paper explores the tradeoff between cipher strength and buffer size. From the logic synthesis by using Synopsys Design Compiler, power dissipation, clock speed, running time, and throughput are studied. The cipher streaming buffer size dependency of these speculative factors achieves the guideline of optimum buffer size in view of cipher strength, power dissipation and throughput for ubiquitous computing. I.

eSTREAM, ECRYPT Stream Cipher Project, Report, 2006

IET Circuits, Devices & Systems, 2019

Data security is essential for the proliferation of the Internet of things and cyber-physical system technologies. Data security can be efficiently achieved by incorporating lightweight cryptography techniques. In this study, a set of highperformance hardware architectures for PRESENT lightweight block cipher are proposed that perform encryption, decryption and integrated encryption/decryption operations. Datapath of the architectures is of 64 bit width that supports standard 80 and 128 bits key lengths. The architectures are synthesised on Xilinx Virtex-5 XC5VLX110T (ff1136-1) field-programmable gate array device of ML-505 platform. To perform functional verification, a large number of test vectors are used. Performance measurement is performed by evaluating maximum frequency, throughput, power dissipation and energy consumption. Experimentally, it is found that the proposed architectures are resource-efficient, high-performance and suitable for lightweight, latency-critical and low-power applications in comparison with existing architectures.

2009

VEST hardware-dedicated stream ciphers are based on bijective nonlinear parallel feedback shift registers assisted by non-linear Remainder Number System (RNS) based counters. Three VEST cipher family trees are introduced: VEST-4, VEST-16 and VEST-32. VEST-4 returning 4 bits of output per clock cycle occupying ~4K ASIC gates offers 80-bit security, perfect for low-area low-cost applications such as RFID and smartcards. VEST-16 returning 16 bits of output per clock cycle occupying ~12K ASIC gates offers 160-bit security, perfect for high-speed low-area low cost applications. VEST-32 returning 32 bits of output per clock cycle occupying ~20K ASIC gates offers 256-bit security, perfect for high-speed high security applications such as processor-bus encryption. All VEST ciphers support variable key sizes and instant re-keying, and all VEST ciphers release output on every clock cycle.

International Journal of Engineering Research and Technology (IJERT), 2013

https://www.ijert.org/an-fpga-implementation-of-zuc-stream-cipher https://www.ijert.org/research/an-fpga-implementation-of-zuc-stream-cipher-IJERTV2IS120902.pdf In this paper a hardware implementation of ZUC stream cipher is presented. ZUC is a stream cipher that forms the heart to the 3 GPP confidentiality algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3, offer in reliable security services in Long Term Evolution networks (LTE). A detailed hardware implementation is presented in order to reach satisfactory performance results in LTE systems. The design was coded using VHDL language and for the hardware implementation, a XILINX Spartan-3FPGAwasused. Experimental results in terms of performance and hardware resources are presented.

International Journal of Computer Theory and Engineering, 2017