Academia.eduAcademia.edu

Outline

Title
Abstract
Figures
Introduction
Experimental Results and Comparisons
References
All Topics
Computer Science
Cryptography

An FPGA Implementation of the ZUC Stream Cipher

Profile image of Paris KitsosParis Kitsos

2011, 2011 14th Euromicro Conference on Digital System Design

https://doi.org/10.1109/DSD.2011.109
visibility

…

description

4 pages

link

1 file

Abstract

In this paper a hardware implementation of ZUC stream cipher is presented. ZUC is a stream cipher that forms the heart of the 3GPP confidentiality algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3, offering reliable security services in Long Term Evolution networks (LTE). A detailed hardware implementation is presented in order to reach satisfactory performance results in LTE systems. The design was coded using VHDL language and for the hardware implementation, a XILINX Virtex-5 FPGA was used. Experimental results in terms of performance and hardware resources are presented.

Figures (5)
Fig. 1. Proposed architecture of the ZUC stream cipher where S is a 32 X 32 S-box and L,, L» are linear transformations.
Fig. 1. Proposed architecture of the ZUC stream cipher where S is a 32 X 32 S-box and L,, L» are linear transformations.
The Key Loading part use a 240-bit D constant, D = do \|d; ||...|ldis (where 0 < d; < 15 are predefined) and together with Key and IV, produce 16 substrings of 31-bit according to the following rule s; = k; || d; || ivi (O S i S 15). The k; and iv; are considered the 16 bytes of the Key and IV respectively where kp and ivo are the most significant ones. Those substrings are used as initial values of the 31-bit LFSR cells sO, sl, ..., s15 respectively. The substrings s; are parallel loaded as the LFSR initial values through the OR- gates as in Fig. 2. When the values are fetched the OR-gates are forced by zeros.
The Key Loading part use a 240-bit D constant, D = do \|d; ||...|ldis (where 0 < d; < 15 are predefined) and together with Key and IV, produce 16 substrings of 31-bit according to the following rule s; = k; || d; || ivi (O S i S 15). The k; and iv; are considered the 16 bytes of the Key and IV respectively where kp and ivo are the most significant ones. Those substrings are used as initial values of the 31-bit LFSR cells sO, sl, ..., s15 respectively. The substrings s; are parallel loaded as the LFSR initial values through the OR- gates as in Fig. 2. When the values are fetched the OR-gates are forced by zeros.
The circuit that executes the Feedback Logic is illustrated in Fig. 4. The operation of the proposed ZUC design (see Fig. 1) starts with the initial parallel loading of the LFSR initial values. Also, the values of R; and R, registers are set equal to zero. Then, during the initialization stage, the LFSR receives a 31-bit word as input through the multiplexer MUX (input 1 of the multiplexer is selected). This input is produced by the addition mod (27-1) between the 31-bit output of the function F called W (the rightmost bit of the output W is removed, W>>1) and the output of the feedback ogic. During this operation the cipher is clocked without producing output. For this reason a 32-bit output register is ocated at the output of the cipher that holds the produced data. In addition, during the working mode, the LFSR does not receive any new input and input 2 of the multiplexer is selected. The cipher is executed once, and the output W is discarded. After that, the cipher produces a 32-bit keystream, Z, each clock cycle. The keystream produced by bit-by-bit XOR between the W and X; word that is output of BR layer. In this stage of operation the 32-bit output register latches its input to the output.
The circuit that executes the Feedback Logic is illustrated in Fig. 4. The operation of the proposed ZUC design (see Fig. 1) starts with the initial parallel loading of the LFSR initial values. Also, the values of R; and R, registers are set equal to zero. Then, during the initialization stage, the LFSR receives a 31-bit word as input through the multiplexer MUX (input 1 of the multiplexer is selected). This input is produced by the addition mod (27-1) between the 31-bit output of the function F called W (the rightmost bit of the output W is removed, W>>1) and the output of the feedback ogic. During this operation the cipher is clocked without producing output. For this reason a 32-bit output register is ocated at the output of the cipher that holds the produced data. In addition, during the working mode, the LFSR does not receive any new input and input 2 of the multiplexer is selected. The cipher is executed once, and the output W is discarded. After that, the cipher produces a 32-bit keystream, Z, each clock cycle. The keystream produced by bit-by-bit XOR between the W and X; word that is output of BR layer. In this stage of operation the 32-bit output register latches its input to the output.
The synthesis results of the proposed ZUC implementation are shown in Table I. Comparisons with the previous version of ZUC cipher and other similar stream ciphers are also given.
The synthesis results of the proposed ZUC implementation are shown in Table I. Comparisons with the previous version of ZUC cipher and other similar stream ciphers are also given.

Related papers

Comparison of the Hardware Implementation of Stream Ciphers
Giorgos Kostopoulos

The International Arab Journal of Information Technology, 2005

In this paper, the hardware implementations of five representative stream ciphers are compared in terms of performance and consumed area. The ciphers used for the comparison are the A5/1, W7, E0, RC4 and Helix. The first three ones have been used for the security part of wellknown standards. The Helix cipher is a recently introduced fast, word oriented, stream cipher. W7 algorithm has been recently proposed as a more trustworthy solution for GSM, due to the security problems that occurred concerning A5/1 strength. The designs were coded using VHDL language. For the hardware implementation of the designs, an FPGA device was used. The implementation results illustrate the hardware performance of each cipher in terms of throughput-to-area ratio. This ratio equals to: 5.88 for the A5/1, 1.26 for the W7, 0.21 for the E0, 2.45 for the Helix and 0.86 for the RC4.

View PDFchevron_right
Hardware Implementations for the ISO/IEC 18033-4: 2005 Standard for Stream Ciphers
Paris Kitsos

International journal of signal processing, 2006

View PDFchevron_right
Comparison of the hardware architectures and FPGA implementations of stream ciphers
Paris Kitsos

2004

Abstract In this paper, the hardware implementations of five representative stream ciphers are compared in terms of performance and consumed area. The ciphers used for the comparison are the A5/1, W7, E0, RC4 and Helix. The first three ones have been used for the security part of well-known standards. The Helix cipher is a recently introduced fast, word oriented, stream cipher.

View PDFchevron_right
The New LTE Cryptographic Algorithms EEA3 and EIA3 Verification, Implementation and Analytical Evaluation
Ghizlane Orhanou

Applied Mathematics & Information Sciences, 2013

A new set of cryptographic algorithms is being proposed for inclusion in the "4G" mobile standard called LTE (Long Term Evolution), and the algorithms are open for public evaluation. The new set of confidentiality and integrity algorithms EEA3/EIA3 is based on the new stream cipher ZUC. In the present paper, we are interested in making the verification and the implementation as well as performing the analytical analysis of the two algorithms, as we have done, in previous works, with the first two sets of the LTE cryptographic algorithms EEA1/EIA1 and EEA2/EIA2. The verification of the confidentiality algorithm results on a correction of the proposed 3GPP algorithm code to meet the specifications requirements.

View PDFchevron_right
An Fpga Implementation of the Gprs Encryption Algorithm 3 (Gea3)
Paris Kitsos

JOURNAL OF CIRCUITS …, 2005

View PDFchevron_right
EFFICIENT VLSI ARCHITECTURE FOR 4G CRYPTO PROCESSOR USING MILENAGE AND ZUC ALGORITHM
Dr.Latha Rajagopalan

The whole security architecture of LTE (long term evolution) consists of two main cryptographic algorithms: MILENAGE algorithm and ZUC algorithm. This paper shows a security architecture crypto processors for 4G LTE consists of two ciphers algorithm enables each one on demand which is based on novel design principles .The crypto processor reduce the covered area and increase the speed better than the other crypto processors.

View PDFchevron_right
An FPGA-Based Implementation of the Pomaranch Stream Cipher
Paris Kitsos
View PDFchevron_right
Comparison of the Hardware Implementation of Stream Ciphers, The International Arab
Paris Kitsos

In this paper, the hardware implementations of five representative stream ciphers are compared in terms of performance and consumed area. The ciphers used for the comparison are the A5/1, W7, E0, RC4 and Helix. The first three ones have been used for the security part of wellknown standards. The Helix cipher is a recently introduced fast, word oriented, stream cipher. W7 algorithm has been recently proposed as a more trustworthy solution for GSM, due to the security problems that occurred concerning A5/1 strength. The designs were coded using VHDL language. For the hardware implementation of the designs, an FPGA device was used. The implementation results illustrate the hardware performance of each cipher in terms of throughput-to-area ratio. This ratio equals to: 5.88 for the A5/1, 1.26 for the W7, 0.21 for the E0, 2.45 for the Helix and 0.86 for the RC4.

View PDFchevron_right
FPGA implementation of an optimized A5/3 encryption algorithm
Mahdi Madani

Microprocessors and Microsystems, 2020

A radio link connecting users to network services is one of the most sensitive parts of mobile networks. This wireless channel is not protected physically to prevent unauthorized access to the carried information. Therefore, network providers use a security mechanism mainly based on cryptographic algorithms. For example, data protection (confidentiality) in the second and third generations of mobile networks is ensured using the A5/3 encryption algorithm (f8 function) standardized by the Third Generation Partnership Project (3GPP). In this work, we defined two main objectives for obtaining an optimized architecture of the A5/3 algorithm. The first one focuses on the optimization of the algorithm's kernel (the KASUMI block cipher) by simplifying its internal architecture. The second one aims at the optimization of the A5/3 algorithm using a single block of the simplified KASUMI, unlike the standard A5/3 algorithm based on five blocks of the basic KASUMI. As a result, good performance has been achieved by considering the tradeoff between high throughput and required hardware logic resources compared to previous works. The proposed architecture was implemented on several Xilinx Virtex Field Programmable Gate Arrays (FPGA) technology devices. The synthesis results obtained after place and route have demonstrated the feasibility and efficiency of our solution. This promising technique can be applied to provide real-time data protection on embedded applications of mobile networks.

View PDFchevron_right
FPGA Implementation of International Data Encryption Algorithm.
Ijesrt Journal

International Journal of Engineering Sciences & Research Technology, 2014

Cryptography is the art of keeping data secure from unauthorized access so as to guarantee that only the intended users can access it.Data security is an important issue in computer networks and cryptographic algorithms are essential parts in networksecurity.This paper covers the implementation of theInternational Data Encryption Algorithm (IDEA) using Very Large Scale Integrated Circuits Hardware Description Language (VHDL) with the help of Xilinx – ISE 9.1. In terms of security, this algorithm is very much superior. In IDEA, the plaintext and the ciphertext are 64 bit blocks, while the secret key is 128 bit long. The cipher is based on the design concept of mixing operations from different algebraic groups.

View PDFchevron_right

References (13)

  1. 3G TS 33.401 V 9.3.1 (2010-04) 3rd Generation Partnership Project; Technical Specification Group Services and System Aspects; 3GPP System Architecture Evolution (SAE); Security architecture (Release 9).
  2. Specification of the 3GPP Confidentiality and Integrity Algorithms UEA2 & UIA2. Document 1: UEA2 and UIA2 Specification, ETSI/SAGE Specification, Version: 1.1Date: 6th September 2006.
  3. Specification of the 3GPP Confidentiality and Integrity Algorithms UEA2 & UIA2. Document 2: SNOW 3G Specification, ETSI/SAGE Specification, Version: 1.1Date: 6th September 2006.
  4. 3GPP System Architecture Evolution (SAE): Security Architecture, 3GPP Std. TS 33.401, Rev. 8.2.1, Dec. 2008.
  5. Specification for the Advanced Encryption Standard (AES), Federal Information Processing Standards (FIPS) Publication 197, US Nat'l Inst. Standards and Technology, 2001.
  6. N. Sklavos, X. Zhang, "Wireless Security & Cryptography: Specifications and Implementations", CRC-Press, A Taylor and Francis Group, ISBN: 084938771X, 2007.
  7. ETSI/SAGE Specification. Specification of the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3. Document 1: 128- EEA3 and 128-EIA3 Specification; Version: 1.5; Date: 4th January 2011.
  8. ETSI/SAGE Specification. Specification of the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3. Document 2: ZUC Specification; Version: 1.5; Date: 4th January 2011.
  9. XILINX INC. 2006. UG190: Virtex-5 user guide. http://www.xilinx.com/support/documentation/user guides/ug190.pdf.
  10. Z. Liu, L. Zhang, J. Jing and W. Pan, "Efficient Pipelined Stream Cipher ZUC Algorithm in FPGA", The First International Workshop on ZUC Algorithm, December 2-3, Beijing, China, 2010.
  11. P. Kitsos, G. Selimis, O. Koufopavlou, "High Performance ASIC Implementation of the SNOW 3G Stream Cipher", IFIP/IEEE VLSI- SOC 2008 -International Conference on Very Large Scale Integration (VLSI SOC), Rhodes Island, Greece, October 13-15, 2008.
  12. P. Kitsos and A. N. Skodras, "On the Hardware Implementation of the MUGI Pseudorandom Number Generator", Fifth International Symposium on Communications Systems, Networks and Digital Signal Processing, (CSNDSP'2006), Patras, Greece, 19-21 July, 2006.
  13. International Organization for Standardization, "ISO/IEC 18033- 4:2005: Information Technology -Security Techniques -Encryption Algorithms -Part 4: Stream ciphers", 2005.

Related papers

IJERT-An FPGA Implementation of ZUC Stream Cipher
IJERT Journal

International Journal of Engineering Research and Technology (IJERT), 2013

https://www.ijert.org/an-fpga-implementation-of-zuc-stream-cipher https://www.ijert.org/research/an-fpga-implementation-of-zuc-stream-cipher-IJERTV2IS120902.pdf In this paper a hardware implementation of ZUC stream cipher is presented. ZUC is a stream cipher that forms the heart to the 3 GPP confidentiality algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3, offer in reliable security services in Long Term Evolution networks (LTE). A detailed hardware implementation is presented in order to reach satisfactory performance results in LTE systems. The design was coded using VHDL language and for the hardware implementation, a XILINX Spartan-3FPGAwasused. Experimental results in terms of performance and hardware resources are presented.

View PDFchevron_right
Reconfigurable Hardware for ZUC Stream Cipher
Dr. Sanjay Badhe

International Journal of Advance Research and Innovative Ideas in Education, 2015

In the world of cryptography, stream ciphers are known as primitives used to ensure privacy over a communication channel. One common way to build a stream cipher is to use a keystream generator to produce a pseudorandom sequence of symbols. ZUC is a stream cipher that forms the heart of the 3GPP confidentiality algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3, offering reliable security services in Long Term Evolution networks (LTE), which is a candidate standard for the 4G network. A detailed hardware implementation is presented in order to reach satisfactory performance results in LTE systems. Stream ciphers are more efficient when implemented in hardware environment, like Field Programmable Gate Array (FPGA). The design is coded using VHDL language and for the hardware implementation, a XILINX Virtex-5 FPGA is used. In this paper a reconfigurable implementation of ZUC stream cipher using Carry Look Ahead Adder is presented. This achieved a throughput of 3.2180 Gbps.

View PDFchevron_right
A High Performance ASIC Implementation of the SNOW 3G Stream Cipher
Paris Kitsos

In this paper a hardware implementation of SNOW 3G stream cipher is presented. SNOW 3G is a stream cipher that forms the heart of the 3GPP confidentiality algorithm UEA2 and the 3GPP integrity algorithm UIA2, offering reliable security services in Universal Mobile Telecommunication System (UMTS). A detailed hardware implementation is presented in order to reach satisfactory performance results in systems such as mobile devices. The design was coded using VHDL language and for the hardware implementation, an ASIC synthesis approach was used. Experimental results in terms of performance and covered area are presented.

View PDFchevron_right
High Performance ASIC Implementation of the SNOW 3G Stream Cipher
Paris Kitsos
View PDFchevron_right
FPGA-based performance analysis of stream ciphers ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0
Athanassios Skodras

Microprocessors and Microsystems, 2013

In this paper, the hardware implementations of six representative stream ciphers are compared in terms of performance, consumed area and the throughput-to-area ratio. The stream ciphers used for the comparison are ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0. ZUC, Snow3g and E0 have been used for the security part of well known standards, especially wireless communication protocols. In addition, Grain V1, Mickey V2 and Trivium are currently selected as the final portfolio of stream ciphers for Profile 2 (Hardware) by the eStream project. The designs were implemented by using VHDL language and for the hardware implementations a FPGA device was used. The highest throughput has been achieved by Snow3g with 3330 Mbps at 104 MHz and the lowest throughput has been achieved by E0 with 187 Mbps at 187 MHz. Also, the most efficient cipher for hardware implementation in terms of throughput-to-area ratio is Mickey V2 cipher while the worst cipher for hardware implementation is Grain V1.

View PDFchevron_right

Related topics

  • Computer Science
  • Signal Processing
  • Cryptography
  • Hardware Description Languages
  • Field-Programmable Gate Arrays
  • Digital System Design
  • Algorithm Design
  • Field Programmable Gate Array
  • Stream Cipher
    • 580 California St., Suite 400
    San Francisco, CA, 94104
    © 2025 Academia. All rights reserved