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Title
Abstract
FAQs
Figures
Introduction
Evaluation Results
Hardware Cost Analysis
References

RISC-V2: A Scalable RISC-V Vector Processor

Profile image of Karyofyllis PatsidisKaryofyllis Patsidis

2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS)

https://doi.org/10.1109/ISCAS45731.2020.9181071
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5 pages

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Abstract

Machine learning adoption has seen a widespread bloom in recent years, with neural network implementations being at the forefront. In light of these developments, vector processors are currently experiencing a resurgence of interest, due to their inherent amenability to accelerate data-parallel algorithms required in machine learning environments. In this paper, we propose a scalable and high-performance RISC-V vector processor core. The presented processor employs a triptych of novel mechanisms that work synergistically to achieve the desired goals. An enhanced vector-specific incarnation of register renaming is proposed to facilitate dynamic hardware loop unrolling and alleviate instruction dependencies. Moreover, a cost-efficient decoupled execution scheme splits instructions into execution and memory-access streams, while hardware support for reductions accelerates the execution of key instructions in the RISC-V ISA. Extensive performance evaluation and hardware synthesis analysis validate the efficiency of the new architecture.

FAQs

sparkles

AI

What performance gains does the register remapping technique achieve in vector processors?add

The proposed design achieves a 2.1× increase in average throughput, measured in Elements Per Cycle, due to enhanced instruction scheduling from register remapping and dynamic allocation.

How does the decoupling of execution and memory access improve vector processor efficiency?add

This technique allows independent execution and memory flows, minimizing stalls and optimizing resource utilization, thus significantly enhancing overall performance.

What unique reduction operation acceleration method is used in the proposed architecture?add

The architecture employs a dynamically generated reduction tree, resulting in latency improvements calculated as log2 of vector length for NN algorithm execution.

How does vector processor scalability compare to traditional architectures under testing?add

The scalable architecture demonstrated almost linear throughput gains with increasing execution lanes for linear algebra and DSP algorithms, although NN algorithms showed limited scaling due to complex memory patterns.

What are the hardware cost implications of integrating a vector core with a superscalar processor?add

While area and power consumption increase with the addition of the vector core, the architecture achieves significantly better power efficiency, measured in EPC/Watt, suitable for high-demand applications.

Figures (8)
THE EXECUTION LATENCIES OF THE VARIOUS INSTRUCTION TYPES. is variable, and it depends on the operation being executed. Table When Stage t is vari lists the latencies for the various classes of instructions. a result is generated, it becomes available to the issue hrough the forwarding paths. Since the execution latency able, the orchestration of instruction progress is per- formed by the scoreboard, which notifies stalled instructions in the ready. issue stage whenever their pending operand values are The stalled instructions “wake up” and proceed to the next pipeline stage. During execution, vector jzops may trigger the same operation in multiple execution lanes, based on the vector ength. TABLE I
THE EXECUTION LATENCIES OF THE VARIOUS INSTRUCTION TYPES. is variable, and it depends on the operation being executed. Table When Stage t is vari lists the latencies for the various classes of instructions. a result is generated, it becomes available to the issue hrough the forwarding paths. Since the execution latency able, the orchestration of instruction progress is per- formed by the scoreboard, which notifies stalled instructions in the ready. issue stage whenever their pending operand values are The stalled instructions “wake up” and proceed to the next pipeline stage. During execution, vector jzops may trigger the same operation in multiple execution lanes, based on the vector ength. TABLE I
Fig. 1. A high-level overview of the micro-architecture of the proposed vector processor. All vector instructions are diverted to the vector execution path upon completion of the scalar Issue Stage (sIS).
Fig. 1. A high-level overview of the micro-architecture of the proposed vector processor. All vector instructions are diverted to the vector execution path upon completion of the scalar Issue Stage (sIS).
Traditionally, synchronization in decoupled processor schemes is achieved by employing so called synchronization queues and special move operations [24]. However, such schemes are not amenable to vector processors, where hun- dreds of elements have to be moved from/to the memory. The synchronization queues incur a significant hardware overhead, while the inserted move instructions block the computation stream until all the data has been transfered. Fig. 2. The three-phase process of remapping the registers and dynamically allocating the register file. The software initially requests a number of logical registers, which dictates the number of groups the vector register file is going to be split into. Each instruction dispatches multiple jzops to cover the full size of the allocated group.
Traditionally, synchronization in decoupled processor schemes is achieved by employing so called synchronization queues and special move operations [24]. However, such schemes are not amenable to vector processors, where hun- dreds of elements have to be moved from/to the memory. The synchronization queues incur a significant hardware overhead, while the inserted move instructions block the computation stream until all the data has been transfered. Fig. 2. The three-phase process of remapping the registers and dynamically allocating the register file. The software initially requests a number of logical registers, which dictates the number of groups the vector register file is going to be split into. Each instruction dispatches multiple jzops to cover the full size of the allocated group.
Fig. 3. The deployment of the dynamically generated hardware reduction tree in a setup with 4 execution lanes. Each cycle the length of the vector is reduced in half by computing the neighboring partial results, until the final result is ready.
Fig. 3. The deployment of the dynamically generated hardware reduction tree in a setup with 4 execution lanes. Each cycle the length of the vector is reduced in half by computing the neighboring partial results, until the final result is ready.
Finally, we evaluate the scalability of the overall vector processor design. We compare three different vector config- urations using 4, 8, and 16 execution lanes and a baseline IMPACT OF THE HARDWARE-BASED REDUCTION TREE ON THE THROUGHPUT (EPC) OF NN ALGORITHMS IN VARIOUS CONFIGURATIONS.
Finally, we evaluate the scalability of the overall vector processor design. We compare three different vector config- urations using 4, 8, and 16 execution lanes and a baseline IMPACT OF THE HARDWARE-BASED REDUCTION TREE ON THE THROUGHPUT (EPC) OF NN ALGORITHMS IN VARIOUS CONFIGURATIONS.
HARDWARE IMPLEMENTATION RESULTS OF FOUR INVESTIGATED DESIGNS (CACHES ARE EXCLUDED) AT 45 NM/ 0.8 V AT | GHZ. As expected, the area increases significantly when augment- ing the superscalar processor with a vector core. The area overhead of the vector core scales almost linearly with the increase in the number of execution lanes. The same trends are also followed by the power consumption. Nevertheless, modern systems (and especially resource-constrained ones) demand increasingly higher computational power implemented in a cost-effective manner. Therefore, a key metric is that of power efficiency (EPC/Watt). Clearly, the proposed architec- ture achieves a markedly better overall power efficiency that scales well with bigger vector configurations.
HARDWARE IMPLEMENTATION RESULTS OF FOUR INVESTIGATED DESIGNS (CACHES ARE EXCLUDED) AT 45 NM/ 0.8 V AT | GHZ. As expected, the area increases significantly when augment- ing the superscalar processor with a vector core. The area overhead of the vector core scales almost linearly with the increase in the number of execution lanes. The same trends are also followed by the power consumption. Nevertheless, modern systems (and especially resource-constrained ones) demand increasingly higher computational power implemented in a cost-effective manner. Therefore, a key metric is that of power efficiency (EPC/Watt). Clearly, the proposed architec- ture achieves a markedly better overall power efficiency that scales well with bigger vector configurations.
Fig. 4. The performance improvement obtained when using the novel registet remapping mechanism and the dynamic allocation of the register file. Both vector cores feature 8 execution lanes. We first examine the impact of the novel register remapping scheme discussed in Section I-A. We compare the proposed design with a simpler baseline vector processor [22] that does not have the register remapping mechanism and operates with a shorter pipeline (i.e., one without the VRRM stage). Figure 4 depicts the results, normalized to the throughput of the base- ine design. The average throughput — calculated as Elements Per Cycle (EPC), the ratio of total elements over the execution time — increases by 2.1x. This significant improvement is primarily attributed to the enhanced instruction scheduling resulting from the synergistic effect of register remapping, instruction expansion, and the dynamically allocated register file.
Fig. 4. The performance improvement obtained when using the novel registet remapping mechanism and the dynamic allocation of the register file. Both vector cores feature 8 execution lanes. We first examine the impact of the novel register remapping scheme discussed in Section I-A. We compare the proposed design with a simpler baseline vector processor [22] that does not have the register remapping mechanism and operates with a shorter pipeline (i.e., one without the VRRM stage). Figure 4 depicts the results, normalized to the throughput of the base- ine design. The average throughput — calculated as Elements Per Cycle (EPC), the ratio of total elements over the execution time — increases by 2.1x. This significant improvement is primarily attributed to the enhanced instruction scheduling resulting from the synergistic effect of register remapping, instruction expansion, and the dynamically allocated register file.
Fig. 5. Performance scaling for 3 different vector configurations, as compared to a baseline dual-issue superscalar core.
Fig. 5. Performance scaling for 3 different vector configurations, as compared to a baseline dual-issue superscalar core.

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