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Outline

A QFHD 30fps HEVC Decoder Design

2016, IEEE Transactions on Circuits and Systems for Video Technology

https://doi.org/10.1109/TCSVT.2015.2409019

Abstract
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This paper presents an innovative design for a QFHD 30fps HEVC decoder, addressing the challenges posed by ultra high definition video processing. By leveraging HEVC's advanced coding techniques, such as large hierarchical units and complex prediction modes, the design aims to enhance coding efficiency while minimizing computational complexity and memory bandwidth requirements. The proposed solution integrates a simplified structure for real-time performance, demonstrating significant potential to meet the growing demand for high-efficiency video coding.

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  28. Pai-Tse Chiang received the B.S and M.S degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2011 and 2013, respectively. His current research interests include digital signal processing, video coding and system- on-chip design.