Analysis of Performance of Switched Capacitor Circuits

2007 Internatonal Conference on Microelectronics, 2007

A biasing technique that minimizes the process and temperature variations of the slew rate and the gain bandwidth product of the amplifiers at the core of any switched capacitor circuit is presented. It is based on using a switched capacitor current reference coupled with weak inversion biasing of the input differential pair of the amplifier. A minimum value for the inversion coefficient that maximizes the transconductance efficiency without compromising the parasitic capacitance at the amplifier's input is analytically derived. The proposed biasing circuit is analyzed and designed using a 130nm CMOS process. The performance was verified by simulations with a high speed telescopic OTA.

Active and Passive Electronic Components, 1994

A chronological list of 440 references on switched capacitor (SC) networks from 1939 to May 1981 was published in this Journal by J. Vandewalle. In this communication, we present a compilation of 1357 references covering the period from May 1981-1992 (along with a supplementary list of 43 missing references for the period before May 1981). The present compilation and the earlier one by Vandewalle put together, thus, constitute an exhaustive bibliography of 1797 references on SC-networks and techniques till 1992.

2016

Nowadays, with the increasing demand for smaller and lighte r power converters in commercial electronics, there is an increasing popularity in b oth the research and the development of switched-capacitor (SC) converters. With the abs ence of inductors and bulky transformers, the power density of SC converters is improve d as compared to traditional switching mode power supplies. Moreover, the possibility o f fabricating an entire SC converter into an integrated circuit (IC) chip has resulted in many companies producing SC converter ICs and many portable electronic products adop ting such ICs. The purpose of the thesis is to summarize the previous resear ch works and report the accomplished works. A literature review is included to summ arize the research efforts of SC converters. Converter topologies, modeling works, co ntrol methodologies, practical applications, and the industrial market development of SC converters are discussed. Limitations of previous works are highlighted and ...

1992

Two design techniques are described for decreasing and possibly eliminating the effects of element imperfections in switched-capacitor (SC) circuits. The first technique is devoted to the operational amplifier non-idealities. It is centered on decreasing the number of amplifiers in the circuits by multiplexing their use. The second approach is based on the minimization of the sum of the square of the differences between the time (or the frequency) response of the circuit with and without non-idealities. This technique can be used to control over the effects of finite switch resistances, finite gain-bandwidth product of the amplifiers as well as parasitic capacitances. Computer results have revealed that the responses of the optimized circuits are nearly the same as that of the ideal ones. Illustrative examples are given illustrating the efficiency of the proposed techniques.

2019

This paper reports on a theoretical study of the efficiency of a switched capacitor converter for autonomous sensors. The sensor is composed of an energy harvester (Solar cell), the electronic system (micro-controller, radio, temperature sensor, MEMS. . . ) and a battery. Based on our theory, we calculate this efficiency with respect to: the switching frequency, the capacitance value s and the battery voltage. We present this using 3-D graphs. This theory is based on Ultra-Low-Power embedded systems such as wireless sensors with photovoltaic harvesters operating in low-light conditions. In this case, the harvested energy from PV do not exceed a few tens of micro-watts, which forbids the use of "power-hungry" coil-based power converters. On the contrary, using switched capacitors converter is a better alternative for this kind of application. We here present a theoretical framework deriving the maximum efficiency achieved by a switched capacitor converter with respect to: t...

IEEE Journal of Solid-State Circuits, 1999

Design techniques are described for the realization of precision high-linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFET's for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology.

The contribution of the rise and fall times of switches to the losses of Switched Capacitors Converters was evaluated by an approximate analysis applying the equivalent resistance concept. It was found that switch turn-on and turn-off durations increase the equivalent resistance of the converter and, consequently, the losses, except in the case of complete charge/discharge of the flying capacitors within the switching phase. Loss increase is related to the fact that during the current rise/fall state, the instantaneous losses are much higher than when the switch is in a constant 'on' state. Theoretical predictions were validated by full circuit simulations and experimental results. The present study integrates the switching losses into the generic equivalent resistance loss model, enabling the calculation and/or simulation of the total losses in switched capacitor converters.

International Journal of Advance Engineering and Research Development, 2014

Switched capacitor techniques are very popular forimplementation of Mixed Signal blocks in CMOS VLSI. Non-OverlappingClock (NOC) generator is one of the key blocksin the implementation of switched capacitor circuits. StandardNOC generator circuits available in the literature uses delaycircuits realized using simple inverters connected in a chain. By using inverter chain delay generated is very small so to generate larger delay it requires larger numbers of inverters. This affects the area and powerbudget of the design. In this work it is proposed to use invertersin inverted form to realize significant delay with less number oftransistors. Simulation results suggest that the proposed circuitwill be area and power efficient as compared to the conventionalNOC circuits.

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems

discussions, patience, support, and encouragement. I learned lots of technical things from him, and also his great personality gave a big influence to my life. I am grateful to Professor Jack Kenney and Professor Richard Schreier for technical discussions and the review of the dissertation. I would like to thank to Professor Shih-Lien Lu for help with the fabrication process and for the review of the dissertation. I thank to Professor Kiaei for serving as a committe member. I also thank to Professor Vikram Saletore of the Computer Science Department for serving as a graduate respresentative. I would like to thank to Orbit Semiconductor Inc. for the courtesy of fabrication of chips. I acknowledge the support of Dr. George Lewicky. I would like to express my special thanks to Paul Ferguson of Analog Devices Inc. for helpful discussions and suggestions and sharing his knowledge on practical experimental issues. My fellow graduate students in the analog IC group have been very helpful. Special thanks are due to Ayse Yesilyurt for sharing her folded-cascode op-amp; Yunteng Huang and Yuming Cao for helpful discussions; Charlie Chairatanatrai for layout support. Special thanks go to Seiko Instruments Inc. for supporting me under their sponsorship program. I would like to express my deep thanks to Mr. Yasunori Ebihara for giving me this great chance to study in the U.S. I would also like to thank to Mr. Kiyohiko

IEICE Electronics Express, 2010

Thermal noise is one of the most important limiting factors on the performance of switched-capacitor (SC) circuit due to the aliasing effect of wide-band thermal noise. In this paper a new simple method for estimating the effect of thermal noise is presented. In the proposed technique only the discrete sampled noise is considered. HSPICE simulator and analytical analysis are used to estimate the sampled noise specification on each clock state. Next, using difference equations of the circuit, time domain simulation is done by MATLAB. Based on this method, a SC integrator is analyzed and results compared to the measured noise response.