Chaff: Engineering An Efficient SAT Solver

2003

We present a new approach to SAT solvers, supporting efficient implementation of highly sophisticated search heuristics over a range of propositional inputs, including CNF formulas, but particularly sets of arbitrary boolean constraints, represented as BDDs. The approach preprocesses the BDDs into state machines to allow for fast inferences based upon any single input constraint. It also simplifies the set of constraints, using a tool set similar to standard BDD engines. And it memoizes search information during an extensive preprocessing phase, allowing for a new form of lookahead, called local-function-complete lookahead. This approach has been incorporated, along with existing tools such as lemmas, to build a SAT tool we call SBSAT. Because of its memoization of constraint-by-constraint lookahead information, besides incorporation of standard lemmas, SBSAT also provides a convenient platform for experimentation with search heuristics. This experimentation is ongoing. We show the feasibility of SBSAT by comparing it to zChaff on several of the benchmarks. We also show an interesting dependence of some standard benchmarks upon simply the independent/dependent variable distinction.

Many decision procedures for Boolean Satisfiability problems solve a instance by searching assignments to its variables. They repeatedly select a free (unassigned) variable based on some heuristics, and assign a truth value to it. Such algorithms are highly dependent on the order of selecting variables. In this work, we propose a method for a variable ordering reflecting dependencies among variables, which gives priority to independent variables, rather than dependent variables of which values can be indirectly determined by assigning truth values to other variables. Our method calculates the order of variables statically, and can be given as a hint to existing state-of-the-art SAT solvers easily. Our method captures structured properties of instances which are derived from state transition models, and experimental results show that the fast SAT solver "zChaff" which incorporates our decision strategy runs about 200 times faster than the original version on the instance derived from 8-bit integer multiplier.

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1999

IX. CONCLUSIONS We have described a novel DFT scheme of controlling clock lines. CLC divides the test generation problem into small segments by selectively clocking sequential modules. A new conflict solving technique, time frame split is implemented in a test generator. Time frames are expanded in the unit of CCB during test generation. So it can be easily extended to high-level test generation. Sequential test generation using clock control showed an improvement in CPU time for test generation and test efficiency.

Journal on Satisfiability, Boolean Modeling and Computation

Due to the widespread demands for efficient SAT solvers in Electronic Design Automation applications, methods to boost the performance of the SAT solver are highly desired. We propose a Hybrid Solution to boost SAT solver performance in this paper, via an integration of local and DPLL-based search approaches. A local search is used to identify a subset of clauses from the original formula to be passed to a DPLL SAT solver incrementally until all the clauses have been passed. In addition, the solution obtained by the DPLL solver on the subset of clauses is fed back to the local search solver to jump over any locally optimal points. The proposed solution is highly portable to the existing SAT solvers. For satisfiable instances, up to an order of magnitude speedup was obtained via the proposed hybrid solver. For unsatisfiable instances, the speedup was smaller due to the overhead.

2001

This paper is devoted to the experimental evaluation of several state-of-the-art search heuristics and optimization techniques in propositional satisFIability (SAT). The test set consists of random 3CNF formulas as well as real world instances from planning, scheduling, circuit analysis, bounded model checking, and security protocols. All the heuristics and techniques have been implemented in a new library for SAT, called SIM. The comparison is fair because in sim the selected heuristics and techniques are realized on a common platform. The comparison is significative because sim as a solver performs very well when compared to other state- of-the-art solvers.

Proc. of IJCAI-09, 2009

Journal of Artificial Intelligence Research

This is the third of three papers describing ZAP, a satisfiability engine that substantially generalizes existing tools while retaining the performance characteristics of modern high-performance solvers. The fundamental idea underlying ZAP is that many problems passed to such engines contain rich internal structure that is obscured by the Boolean representation used; our goal has been to define a representation in which this structure is apparent and can be exploited to improve computational performance. The first paper surveyed existing work that (knowingly or not) exploited problem structure to improve the performance of satisfiability engines, and the second paper showed that this structure could be understood in terms of groups of permutations acting on individual clauses in any particular Boolean theory. We conclude the series by discussing the techniques needed to implement our ideas, and by reporting on their performance on a variety of problem instances.

Lecture Notes in Computer Science, 2005

We propose a new decision heuristic for DPLL-based propositional SAT solvers. Its essence is that both the initial and the conflict clauses are arranged in a list and the next decision variable is chosen from the top -most unsatisfied clause. Various methods of initially organizing the list and moving the clauses within it are studied. Our approach is an extension of one used in Berkmin, and adopted by other modern solvers, according to which only conflict clauses are organized in a list, and a literal-scoring-based secondary heuristic is used when there are no more unsatisfied conflict clauses. Our approach, implemented in the 2004 version of zChaff solver and in a generic Chaff-based SAT solver, results in a significant performance boost on hard industrial benchmarks.

… on Very Large Scale Integration (VLSI …, 2004

Design, Automation, and Test in Europe, 2002

In this paper we propose a novel approach for solving the Boolean satisfiability problem by combining software and reconfigurable hardware. The suggested technique avoids instance-specific hardware compilation and, as a result, achieves a higher performance than pure software approaches. Moreover, it permits problems that exceed the resources of the available reconfigurable hardware to be solved.