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Data Science

Efficient stream compaction on wide SIMD many-core architectures

Profile image of Ulf AssarssonUlf Assarsson

2009, Proceedings of the 1st ACM conference on High Performance Graphics - HPG '09

https://doi.org/10.1145/1572769.1572795
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8 pages

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Abstract

Stream compaction is a common parallel primitive used to remove unwanted elements in sparse data. This allows highly parallel algorithms to maintain performance over several processing steps and reduces overall memory usage. For wide SIMD many-core architectures, we present a novel stream compaction algorithm and explore several variations thereof. Our algorithm is designed to maximize concurrent execution, with minimal use of synchronization. Bandwidth and auxiliary storage requirements are reduced significantly, which allows for substantially better performance. We have tested our algorithms using CUDA on a PC with an NVIDIA GeForce GTX280 GPU. On this hardware, our reference implementation provides a 3× speedup over previous published algorithms.

Figures (11)
Figure 1: Main steps of performing compaction with a prefix sum. First a prefix sur of the valid element flags is computed. Then a gather or scatter step is used to move the valid input elements into the output vector.
Figure 1: Main steps of performing compaction with a prefix sum. First a prefix sur of the valid element flags is computed. Then a gather or scatter step is used to move the valid input elements into the output vector.
Listing 2: Basic parallel algorithm. The number of elements processed by a processo is denoted Kp, and inputp is the associated range of input elements. The notatior [@. .P) is used to describe the range of elements from 0 (inclusive) to P (exclusive) We therefore develop an algorithm that is more suited to actual GPU architecture. In the next sections, we will first describe a model for how modern GPUs operate, which will allow us to design several flavors of efficient compaction algorithms, in the sections follow- ing.
Listing 2: Basic parallel algorithm. The number of elements processed by a processo is denoted Kp, and inputp is the associated range of input elements. The notatior [@. .P) is used to describe the range of elements from 0 (inclusive) to P (exclusive) We therefore develop an algorithm that is more suited to actual GPU architecture. In the next sections, we will first describe a model for how modern GPUs operate, which will allow us to design several flavors of efficient compaction algorithms, in the sections follow- ing.
Listing 3: The first phase, extended to make use of the SIMD capabilities to count the number of valid elements. After reducing the count from S' individual SIMD lanes, the resulting total is stored in the vector processorCounts. We use a parallel reduction to sum the values in COUNTS, .s), as shown on line 9. However, this reduction is performed only once per processor, and is thus not time critical. In the first phase, each SIMD lane is used to count the valid elements it encounters, independently. After processing the en- tire range, the processor performs a parallel sum-reduction, which yields the total number of valid elements in the range inputp. Pseudo code describing these modifications is provided in Listing 3.
Listing 3: The first phase, extended to make use of the SIMD capabilities to count the number of valid elements. After reducing the count from S' individual SIMD lanes, the resulting total is stored in the vector processorCounts. We use a parallel reduction to sum the values in COUNTS, .s), as shown on line 9. However, this reduction is performed only once per processor, and is thus not time critical. In the first phase, each SIMD lane is used to count the valid elements it encounters, independently. After processing the en- tire range, the processor performs a parallel sum-reduction, which yields the total number of valid elements in the range inputp. Pseudo code describing these modifications is provided in Listing 3.
Figure 2: Illustration of the compactSIMD procedure. Here, the SIMD width is S = 16, and the number of valid elements is Q = 8. The element A moves from s = 0 tos’ = 0, whereas the element B moves from s = 3 to s’ = 1. The output is compact in the sense that the @ valid elements occupy lanes 0 through Q — 1.
Figure 2: Illustration of the compactSIMD procedure. Here, the SIMD width is S = 16, and the number of valid elements is Q = 8. The element A moves from s = 0 tos’ = 0, whereas the element B moves from s = 3 to s’ = 1. The output is compact in the sense that the @ valid elements occupy lanes 0 through Q — 1.
Listing 6: Implementation of compactSIMD using a population count. The variable m must be large enough to store S bits. Setting m, on line 5, assumes that the architec- ture allows simultaneous setting of bits. This is not always the case, and a workaround is described in Section 4.2. Assuming POPC is present in the native SIMD instruction set, the log S steps required by the SIMD prefix sum can be avoided. The architecture must also support a word size of S bits. Listing 6 shows the new compactSIMD procedure.
Listing 6: Implementation of compactSIMD using a population count. The variable m must be large enough to store S bits. Setting m, on line 5, assumes that the architec- ture allows simultaneous setting of bits. This is not always the case, and a workaround is described in Section 4.2. Assuming POPC is present in the native SIMD instruction set, the log S steps required by the SIMD prefix sum can be avoided. The architecture must also support a word size of S bits. Listing 6 shows the new compactSIMD procedure.
Listing 7: The buffered implementation of the third phase. The buffer is flushed when it is full, and the overflowing elements are then written to the buffer. The alignOutput procedure moves enough elements to align j to the next multiple of S, and initializes the buffer and counters. There are many short branches in the inner loop, however, they can be compiled into efficient predicated instructions. As the alignment phase will write at most S — 1 elements, these writes will not contribute significantly to the run time of the al- gorithm and can therefore be unbuffered, as long as the buffer is correctly initialized.
Listing 7: The buffered implementation of the third phase. The buffer is flushed when it is full, and the overflowing elements are then written to the buffer. The alignOutput procedure moves enough elements to align j to the next multiple of S, and initializes the buffer and counters. There are many short branches in the inner loop, however, they can be compiled into efficient predicated instructions. As the alignment phase will write at most S — 1 elements, these writes will not contribute significantly to the run time of the al- gorithm and can therefore be unbuffered, as long as the buffer is correctly initialized.
Figure 4: Time (in milliseconds) required to compact a varying number of elements. We compare our best implementation with the CUDPP implementation and geometry shaders. The geometry shader plot is cut off to provide a better view of CUDPP and our implementation. The error bars in the left figure display variations in time as the proportion of valid elements is changed. The graphs represent the average time for varying proportions of valid elements. Also shown are curves for compaction of 64 bit and 128 bit elements. The scattered version shows a near-linear performance scaling. Since we cannot use 64 bit writes, but must resort to several scat- tered 32 bit writes, the number of write transactions quickly in- creases.
Figure 4: Time (in milliseconds) required to compact a varying number of elements. We compare our best implementation with the CUDPP implementation and geometry shaders. The geometry shader plot is cut off to provide a better view of CUDPP and our implementation. The error bars in the left figure display variations in time as the proportion of valid elements is changed. The graphs represent the average time for varying proportions of valid elements. Also shown are curves for compaction of 64 bit and 128 bit elements. The scattered version shows a near-linear performance scaling. Since we cannot use 64 bit writes, but must resort to several scat- tered 32 bit writes, the number of write transactions quickly in- creases.
Figure 3: Time (in milliseconds) required to compact 4M (27? ) 32 bit elements with a varying ratio of valid elements. We have compared our implementations, using both the prefix sum and the POPC based compactSIMD implementations, as well as staged, scattered and buffered variations. In addition, our selective implementation, which automatically switches between staged and scattered output on a warp level, is shown.
Figure 3: Time (in milliseconds) required to compact 4M (27? ) 32 bit elements with a varying ratio of valid elements. We have compared our implementations, using both the prefix sum and the POPC based compactSIMD implementations, as well as staged, scattered and buffered variations. In addition, our selective implementation, which automatically switches between staged and scattered output on a warp level, is shown.
Results from some earlier works [Horn 2005; Sengupta et al. 2006] are not included in Table 3. This is because the publicly available CUDPP implementation uses the same basic strategy, and offers higher performance. Table 3: Comparison of compaction performance with competing techniques. If avail- able, we have used reference implementations for measurements on our hardware. We have created our own CUDA implementation of the algorithm presented in Ziegler et al. The reported times are averages over uniform distributions with 0% to 100% valid elements.
Results from some earlier works [Horn 2005; Sengupta et al. 2006] are not included in Table 3. This is because the publicly available CUDPP implementation uses the same basic strategy, and offers higher performance. Table 3: Comparison of compaction performance with competing techniques. If avail- able, we have used reference implementations for measurements on our hardware. We have created our own CUDA implementation of the algorithm presented in Ziegler et al. The reported times are averages over uniform distributions with 0% to 100% valid elements.
Our performance is comparable with that of Satish et al. [2008], and outperforms the CUDPP library [CUDPP 2008]. The imple- mentation is very simple, we did not perform any in-depth analysis or special optimization. We simply invoke the stream split opera- tion once for each bit in the radix sort key. The simplicity makes it very flexible, allowing any data type and number of bits as radix keys. Table 5: Comparison of our stream split based radix-sort and the currently fastest pub- lished implementation. Our implementation shows almost identical performance, but is more flexible. Our implementation operates on interleaved key-value pairs; Satish et al. have separate arrays for keys and values. We can handle separate keys and values by a pre- and postprocessing step that transforms the separate arrays into interleaved data and back.
Our performance is comparable with that of Satish et al. [2008], and outperforms the CUDPP library [CUDPP 2008]. The imple- mentation is very simple, we did not perform any in-depth analysis or special optimization. We simply invoke the stream split opera- tion once for each bit in the radix sort key. The simplicity makes it very flexible, allowing any data type and number of bits as radix keys. Table 5: Comparison of our stream split based radix-sort and the currently fastest pub- lished implementation. Our implementation shows almost identical performance, but is more flexible. Our implementation operates on interleaved key-value pairs; Satish et al. have separate arrays for keys and values. We can handle separate keys and values by a pre- and postprocessing step that transforms the separate arrays into interleaved data and back.

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    Ik Soo Lim

    Computer Graphics Forum, 2013

    Stream compaction is an important parallel computing primitive that produces a reduced (compacted) output stream consisting of only valid elements from an input stream containing both invalid and valid elements. Computing on this compacted stream rather than the mixed input stream leads to improvements in performance, load balancing, and memory footprint. Stream compaction has numerous applications in a wide range of domains: e.g., deferred shading, isosurface extraction, and surface voxelization in computer graphics and visualization. We present a novel In-Kernel stream compaction method, where compaction is completed before leaving an operating kernel. This contrasts with conventional parallel compaction methods that require leaving the kernel and running a prefix sum kernel followed by a scatter kernel. We apply our compaction methods to ray-tracing-based visualization of volumetric data. We demonstrate that the proposed In-Kernel Compaction outperforms the standard out-of-kernel Thrust parallel-scan method for performing stream compaction in this real-world application. For the data visualization, we also propose a novel multi-kernel ray-tracing pipeline for increased thread coherency and show that it outperforms a conventional single-kernel approach.

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    Neural Prefiltering for Correlation-Aware Levels of Detail
    Philippe Weier

    ACM Transactions on Graphics

    We introduce a practical general-purpose neural appearance filtering pipeline for physically-based rendering. We tackle the previously difficult challenge of aggregating visibility across many levels of detail from local information only, without relying on learning visibility for the entire scene. The high adaptivity of neural representations allows us to retain geometric correlations along rays and thus avoid light leaks. Common approaches to prefiltering decompose the appearance of a scene into volumetric representations with physically-motivated parameters, where the inflexibility of the fitted models limits rendering accuracy. We avoid assumptions on particular types of geometry or materials, bypassing any special-case decompositions. Instead, we directly learn a compressed representation of the intra-voxel light transport. For such high-dimensional functions, neural networks have proven to be useful representations. To satisfy the opposing constraints of prefiltered appearance...

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