Carbon nanotube transistors and logic circuits

International Journal of High Speed Electronics and Systems, 2006

This paper discusses the device physics of carbon nanotube field-effect transistors (CNTFETs). After reviewing the status of device technology, we use results of our numerical simulations to discuss the physics of CNTFETs emphasizing the similarities and differences with traditional FETs. The discussion shows that our understanding of CNTFET device physics has matured to the point where experiments can be explained and device designs optimized. The paper concludes with some thoughts on challenges and opportunities for CNTFET electronics.

International Journal of Modern Physics B, 2009

A carbon nanotube field effect transistor (CNTFET) has been studied based on the Schrödinger–Poisson formalism. To improve the saturation range in the output characteristics, new structures for CNTFETs are proposed. These structures are simulated and compared with the conventional structure. Simulations show that these structures have a wider output saturation range. With this, larger drain-source voltage (Vds) can be used, which results in higher output power. In the digital circuits, higher Vds increases noise immunity.

2013

An overview of the different types of CNTFET which have large potential to semiconductor industry and microelectronic systems is presented. The present paper is focused on the structure of the various types of CNTFET and their technology characteristics depending on the specific CNT used: single-walled or

IEEE Transactions On Nanotechnology, 2005

The performance of Schottky-barrier carbon-nanotube field-effect transistors (CNTFETs) critically depends on the device geometry. Asymmetric gate contacts, the drain and source contact thickness, and inhomogenous dielectrics above and below the nanotube influence the device operation. An optimizer has been used to extract geometries with steep subthreshold slope and high on o ratio. It is found that the best performance improvements can be achieved using asymmetric gates centered above the source contact, where the optimum position and length of the gate contact varies with the oxide thickness. The main advantages of geometries with asymmetric gate contacts are the increased on o ratio and the fact that the gate voltage required to attain minimum drain current is shifted toward zero, whereas symmetric geometries require = 2. Our results suggest that the subthreshold slope of single-gate CNTFETs scales linearly with the gate-oxide thickness and can be reduced by a factor of two reaching a value below 100 mV/dec for devices with oxide thicknesses smaller than 5 nm by geometry optimization.

Carbon Nanotubes - Redefining the World of Electronics, 2021

Single-walled carbon nanotubes (SWCNTs) have been considered as one of the most promising electronic materials for the next-generation electronics in the more Moore era. Sub-10 nm SWCNT-field effect transistors (FETs) have been realized with several performances exceeding those of Si-based FETs at the same feature size. Several industrial initiatives have attempted to implement SWCNT electronics in integrated circuit (IC) chips. Here, the recent advances in SWCNT electronics are reviewed from in-depth understanding of the fundamental electronic structures, the carrier transport mechanisms, and the metal/SWCNT contact properties. In particular, the subthreshold switching properties are highlighted for low-power, energy-efficient device operations. State-of-the-art low-power SWCNT-based electronics and the key strategies to realize low-voltage and low-power operations are outlined. Finally, the essential challenges and prospects from the material preparation, device fabrication, and large-scale ICs integration for future SWCNT-based electronics are foregrounded.

Microelectronic Engineering, 2002

We present recent experiments on carbon nanotube field-effect transistors and their characteristics and compare the performance of these devices with state-of-the-art silicon MOSFETs. By reducing the gate dielectric film thickness and working with high-k dielectric materials such as HfO , we are able to effectively 2 reduce the operational voltages below 1 V. The electrical characteristics obtained clearly indicate excellent device performance in both the on-and off-state wit of the nanotube transistor. On / off-current ratios of almost 4 10 are achieved along with a maximum transconductance of around 425 mS/mm and drive currents of 270 mA/mm at V 2V 5 2 0.6 V. Since device parameters are not fully optimized, significant performance gs th improvements can be expected making carbon nanotubes particularly promising as building blocks for future nanoelectronics. 

2007

A carbon nanotube eld eect transistor (CNTFET) has been studied based on the Schrodinger{Poisson formalism. To improve the saturation range in the output charac-teristics, new structures for CNTFETs are proposed. These structures are simulated and compared with the conventional structure. Simulations show that these structures have a wider output saturation range. With this, larger drain-source voltage (V ds) can be used, which results in higher output power. In the digital circuits, higher V ds increases noise immunity.

Nano letters, 2005

Short channel ( approximately 80 nm) n-type single-walled carbon nanotube (SWNT) field-effect transistors (FETs) with potassium (K) doped source and drain regions and high-kappa gate dielectrics (ALD HfO(2)) are obtained. For nanotubes with diameter approximately 1.6 nm and band gap approximately 0.55 eV, we obtain n-MOSFET-like devices exhibiting high on-currents due to chemically suppressed Schottky barriers at the contacts, subthreshold swing of 70 mV/decade, negligible ambipolar conduction, and high on/off ratios up to 10(6) at a bias voltage of 0.5 V. The results compare favorably with the state-of-the-art silicon n-MOSFETs and demonstrate the potential of SWNTs for future complementary electronics. The effects of doping level on the electrical characteristics of the nanotube devices are discussed.

2006

The performance of carbon nanotube field-effect transistors has been studied based on the non-equilibrium Green's function formalism. The effects of elastic and inelastic scattering and the impact of parameters, such as electron-phonon coupling strength and phonon energy, on the device performance are analyzed. The effect of scaling of the source-gate spacer, drain-gate spacer, and gate length is studied. The results for devices with different barrier heights at the metal-CNT interface are discussed.